Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912793 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
178 |
| auto[1] |
5602328 |
1 |
|
|
T19 |
13 |
|
T23 |
205 |
|
T1 |
28352 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11182972 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
280 |
| auto[1] |
2332149 |
1 |
|
|
T23 |
103 |
|
T1 |
17101 |
|
T2 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7949059 |
1 |
|
|
T19 |
58 |
|
T22 |
203 |
|
T23 |
123 |
| auto[1] |
5566062 |
1 |
|
|
T19 |
2 |
|
T23 |
260 |
|
T1 |
27813 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1619561 |
1 |
|
|
T19 |
2 |
|
T23 |
64 |
|
T1 |
5174 |
| auto[1] |
auto[0] |
auto[1] |
1166302 |
1 |
|
|
T23 |
72 |
|
T1 |
8397 |
|
T2 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1614352 |
1 |
|
|
T23 |
93 |
|
T1 |
5538 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1165847 |
1 |
|
|
T23 |
31 |
|
T1 |
8704 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |