Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7908442 |
1 |
|
|
T19 |
46 |
|
T22 |
203 |
|
T23 |
197 |
| auto[1] |
5606679 |
1 |
|
|
T19 |
14 |
|
T23 |
186 |
|
T1 |
27774 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11160129 |
1 |
|
|
T19 |
56 |
|
T22 |
203 |
|
T23 |
253 |
| auto[1] |
2354992 |
1 |
|
|
T19 |
4 |
|
T23 |
130 |
|
T1 |
17210 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892015 |
1 |
|
|
T19 |
50 |
|
T22 |
203 |
|
T23 |
167 |
| auto[1] |
5623106 |
1 |
|
|
T19 |
10 |
|
T23 |
216 |
|
T1 |
28145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1626842 |
1 |
|
|
T19 |
6 |
|
T23 |
38 |
|
T1 |
5701 |
| auto[1] |
auto[0] |
auto[1] |
1175939 |
1 |
|
|
T19 |
2 |
|
T23 |
61 |
|
T1 |
8899 |
| auto[1] |
auto[1] |
auto[0] |
1641272 |
1 |
|
|
T23 |
48 |
|
T1 |
5234 |
|
T2 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1179053 |
1 |
|
|
T19 |
2 |
|
T23 |
69 |
|
T1 |
8311 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |