Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880394 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
255 |
| auto[1] |
5634727 |
1 |
|
|
T19 |
12 |
|
T23 |
128 |
|
T1 |
28899 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11172552 |
1 |
|
|
T19 |
55 |
|
T22 |
203 |
|
T23 |
289 |
| auto[1] |
2342569 |
1 |
|
|
T19 |
5 |
|
T23 |
94 |
|
T1 |
17500 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7908135 |
1 |
|
|
T19 |
50 |
|
T22 |
203 |
|
T23 |
227 |
| auto[1] |
5606986 |
1 |
|
|
T19 |
10 |
|
T23 |
156 |
|
T1 |
28471 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1623848 |
1 |
|
|
T19 |
5 |
|
T23 |
34 |
|
T1 |
5394 |
| auto[1] |
auto[0] |
auto[1] |
1170435 |
1 |
|
|
T19 |
5 |
|
T23 |
63 |
|
T1 |
8549 |
| auto[1] |
auto[1] |
auto[0] |
1640569 |
1 |
|
|
T23 |
28 |
|
T1 |
5577 |
|
T12 |
7195 |
| auto[1] |
auto[1] |
auto[1] |
1172134 |
1 |
|
|
T23 |
31 |
|
T1 |
8951 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |