Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904648 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
150 |
| auto[1] |
5610473 |
1 |
|
|
T19 |
13 |
|
T23 |
233 |
|
T1 |
29499 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11176738 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
323 |
| auto[1] |
2338383 |
1 |
|
|
T23 |
60 |
|
T1 |
16602 |
|
T2 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7935125 |
1 |
|
|
T19 |
55 |
|
T22 |
203 |
|
T23 |
236 |
| auto[1] |
5579996 |
1 |
|
|
T19 |
5 |
|
T23 |
147 |
|
T1 |
27232 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1621387 |
1 |
|
|
T19 |
5 |
|
T23 |
47 |
|
T1 |
5217 |
| auto[1] |
auto[0] |
auto[1] |
1168664 |
1 |
|
|
T23 |
18 |
|
T1 |
8042 |
|
T2 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1620226 |
1 |
|
|
T23 |
40 |
|
T1 |
5413 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1169719 |
1 |
|
|
T23 |
42 |
|
T1 |
8560 |
|
T12 |
5801 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |