Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906481 |
1 |
|
|
T19 |
43 |
|
T22 |
203 |
|
T23 |
165 |
| auto[1] |
5608640 |
1 |
|
|
T19 |
17 |
|
T23 |
218 |
|
T1 |
27279 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11176692 |
1 |
|
|
T19 |
55 |
|
T22 |
203 |
|
T23 |
235 |
| auto[1] |
2338429 |
1 |
|
|
T19 |
5 |
|
T23 |
148 |
|
T1 |
16894 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7929704 |
1 |
|
|
T19 |
51 |
|
T22 |
203 |
|
T23 |
163 |
| auto[1] |
5585417 |
1 |
|
|
T19 |
9 |
|
T23 |
220 |
|
T1 |
27691 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1620405 |
1 |
|
|
T19 |
4 |
|
T23 |
31 |
|
T1 |
5734 |
| auto[1] |
auto[0] |
auto[1] |
1162821 |
1 |
|
|
T19 |
4 |
|
T23 |
57 |
|
T1 |
9075 |
| auto[1] |
auto[1] |
auto[0] |
1626583 |
1 |
|
|
T23 |
41 |
|
T1 |
5063 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1175608 |
1 |
|
|
T19 |
1 |
|
T23 |
91 |
|
T1 |
7819 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |