Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7896754 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
201 |
| auto[1] |
5618367 |
1 |
|
|
T19 |
22 |
|
T23 |
182 |
|
T1 |
28262 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12800192 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
366 |
| auto[1] |
714929 |
1 |
|
|
T23 |
17 |
|
T1 |
3590 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7927580 |
1 |
|
|
T19 |
44 |
|
T22 |
203 |
|
T23 |
207 |
| auto[1] |
5587541 |
1 |
|
|
T19 |
16 |
|
T23 |
176 |
|
T1 |
28011 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2425650 |
1 |
|
|
T19 |
16 |
|
T23 |
87 |
|
T1 |
12182 |
| auto[1] |
auto[0] |
auto[1] |
354147 |
1 |
|
|
T23 |
8 |
|
T1 |
1760 |
|
T12 |
2030 |
| auto[1] |
auto[1] |
auto[0] |
2446962 |
1 |
|
|
T23 |
72 |
|
T1 |
12239 |
|
T2 |
16 |
| auto[1] |
auto[1] |
auto[1] |
360782 |
1 |
|
|
T23 |
9 |
|
T1 |
1830 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |