Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903526 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
153 |
| auto[1] |
5611595 |
1 |
|
|
T19 |
22 |
|
T23 |
230 |
|
T1 |
28225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11173059 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
281 |
| auto[1] |
2342062 |
1 |
|
|
T23 |
102 |
|
T1 |
17179 |
|
T12 |
10335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922194 |
1 |
|
|
T19 |
58 |
|
T22 |
203 |
|
T23 |
178 |
| auto[1] |
5592927 |
1 |
|
|
T19 |
2 |
|
T23 |
205 |
|
T1 |
28055 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1622220 |
1 |
|
|
T23 |
40 |
|
T1 |
5502 |
|
T2 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1168525 |
1 |
|
|
T23 |
32 |
|
T1 |
8643 |
|
T12 |
5207 |
| auto[1] |
auto[1] |
auto[0] |
1628645 |
1 |
|
|
T19 |
2 |
|
T23 |
63 |
|
T1 |
5374 |
| auto[1] |
auto[1] |
auto[1] |
1173537 |
1 |
|
|
T23 |
70 |
|
T1 |
8536 |
|
T12 |
5128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |