Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7897385 |
1 |
|
|
T19 |
46 |
|
T22 |
203 |
|
T23 |
188 |
| auto[1] |
5617736 |
1 |
|
|
T19 |
14 |
|
T23 |
195 |
|
T1 |
28336 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11169081 |
1 |
|
|
T19 |
53 |
|
T22 |
203 |
|
T23 |
322 |
| auto[1] |
2346040 |
1 |
|
|
T19 |
7 |
|
T23 |
61 |
|
T1 |
18491 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902988 |
1 |
|
|
T19 |
45 |
|
T22 |
203 |
|
T23 |
201 |
| auto[1] |
5612133 |
1 |
|
|
T19 |
15 |
|
T23 |
182 |
|
T1 |
30357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1623999 |
1 |
|
|
T19 |
6 |
|
T23 |
55 |
|
T1 |
6096 |
| auto[1] |
auto[0] |
auto[1] |
1173090 |
1 |
|
|
T19 |
7 |
|
T23 |
24 |
|
T1 |
9529 |
| auto[1] |
auto[1] |
auto[0] |
1642094 |
1 |
|
|
T19 |
2 |
|
T23 |
66 |
|
T1 |
5770 |
| auto[1] |
auto[1] |
auto[1] |
1172950 |
1 |
|
|
T23 |
37 |
|
T1 |
8962 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |