Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7886842 |
1 |
|
|
T19 |
51 |
|
T22 |
203 |
|
T23 |
176 |
| auto[1] |
5628279 |
1 |
|
|
T19 |
9 |
|
T23 |
207 |
|
T1 |
28269 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11167142 |
1 |
|
|
T19 |
58 |
|
T22 |
203 |
|
T23 |
313 |
| auto[1] |
2347979 |
1 |
|
|
T19 |
2 |
|
T23 |
70 |
|
T1 |
17226 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902355 |
1 |
|
|
T19 |
50 |
|
T22 |
203 |
|
T23 |
226 |
| auto[1] |
5612766 |
1 |
|
|
T19 |
10 |
|
T23 |
157 |
|
T1 |
28179 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1629615 |
1 |
|
|
T19 |
8 |
|
T23 |
29 |
|
T1 |
5690 |
| auto[1] |
auto[0] |
auto[1] |
1170805 |
1 |
|
|
T19 |
2 |
|
T23 |
37 |
|
T1 |
8635 |
| auto[1] |
auto[1] |
auto[0] |
1635172 |
1 |
|
|
T23 |
58 |
|
T1 |
5263 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1177174 |
1 |
|
|
T23 |
33 |
|
T1 |
8591 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |