Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881962 |
1 |
|
|
T19 |
57 |
|
T22 |
203 |
|
T23 |
165 |
| auto[1] |
5633159 |
1 |
|
|
T19 |
3 |
|
T23 |
218 |
|
T1 |
28223 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12795757 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
719364 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
3612 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904648 |
1 |
|
|
T19 |
42 |
|
T22 |
203 |
|
T23 |
175 |
| auto[1] |
5610473 |
1 |
|
|
T19 |
18 |
|
T23 |
208 |
|
T1 |
28140 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2438352 |
1 |
|
|
T19 |
17 |
|
T23 |
96 |
|
T1 |
12323 |
| auto[1] |
auto[0] |
auto[1] |
359388 |
1 |
|
|
T19 |
1 |
|
T23 |
4 |
|
T1 |
1900 |
| auto[1] |
auto[1] |
auto[0] |
2452757 |
1 |
|
|
T23 |
102 |
|
T1 |
12205 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[1] |
359976 |
1 |
|
|
T23 |
6 |
|
T1 |
1712 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |