Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7908980 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
200 |
| auto[1] |
5606141 |
1 |
|
|
T19 |
13 |
|
T23 |
183 |
|
T1 |
28104 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12803238 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
367 |
| auto[1] |
711883 |
1 |
|
|
T19 |
1 |
|
T23 |
16 |
|
T1 |
3602 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7947807 |
1 |
|
|
T19 |
32 |
|
T22 |
203 |
|
T23 |
136 |
| auto[1] |
5567314 |
1 |
|
|
T19 |
28 |
|
T23 |
247 |
|
T1 |
28218 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2415179 |
1 |
|
|
T19 |
16 |
|
T23 |
112 |
|
T1 |
11690 |
| auto[1] |
auto[0] |
auto[1] |
353892 |
1 |
|
|
T19 |
1 |
|
T23 |
7 |
|
T1 |
1744 |
| auto[1] |
auto[1] |
auto[0] |
2440252 |
1 |
|
|
T19 |
11 |
|
T23 |
119 |
|
T1 |
12926 |
| auto[1] |
auto[1] |
auto[1] |
357991 |
1 |
|
|
T23 |
9 |
|
T1 |
1858 |
|
T12 |
1905 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |