Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7890296 |
1 |
|
|
T19 |
26 |
|
T22 |
203 |
|
T23 |
205 |
| auto[1] |
5624825 |
1 |
|
|
T19 |
34 |
|
T23 |
178 |
|
T1 |
29314 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12795889 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
375 |
| auto[1] |
719232 |
1 |
|
|
T23 |
8 |
|
T1 |
3339 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7900738 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
228 |
| auto[1] |
5614383 |
1 |
|
|
T19 |
13 |
|
T23 |
155 |
|
T1 |
26654 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2430624 |
1 |
|
|
T19 |
4 |
|
T23 |
74 |
|
T1 |
11336 |
| auto[1] |
auto[0] |
auto[1] |
356603 |
1 |
|
|
T23 |
4 |
|
T1 |
1709 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2464527 |
1 |
|
|
T19 |
9 |
|
T23 |
73 |
|
T1 |
11979 |
| auto[1] |
auto[1] |
auto[1] |
362629 |
1 |
|
|
T23 |
4 |
|
T1 |
1630 |
|
T12 |
2110 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |