Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7924585 |
1 |
|
|
T19 |
51 |
|
T22 |
203 |
|
T23 |
168 |
| auto[1] |
5590536 |
1 |
|
|
T19 |
9 |
|
T23 |
215 |
|
T1 |
29097 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12799589 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
715532 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
3662 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919215 |
1 |
|
|
T19 |
35 |
|
T22 |
203 |
|
T23 |
234 |
| auto[1] |
5595906 |
1 |
|
|
T19 |
25 |
|
T23 |
149 |
|
T1 |
28684 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2452782 |
1 |
|
|
T19 |
16 |
|
T23 |
66 |
|
T1 |
12536 |
| auto[1] |
auto[0] |
auto[1] |
360501 |
1 |
|
|
T19 |
1 |
|
T23 |
4 |
|
T1 |
1834 |
| auto[1] |
auto[1] |
auto[0] |
2427592 |
1 |
|
|
T19 |
8 |
|
T23 |
73 |
|
T1 |
12486 |
| auto[1] |
auto[1] |
auto[1] |
355031 |
1 |
|
|
T23 |
6 |
|
T1 |
1828 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |