Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7893760 |
1 |
|
|
T19 |
36 |
|
T22 |
203 |
|
T23 |
208 |
| auto[1] |
5621361 |
1 |
|
|
T19 |
24 |
|
T23 |
175 |
|
T1 |
26477 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12800012 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
371 |
| auto[1] |
715109 |
1 |
|
|
T23 |
12 |
|
T1 |
3718 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7920328 |
1 |
|
|
T19 |
43 |
|
T22 |
203 |
|
T23 |
137 |
| auto[1] |
5594793 |
1 |
|
|
T19 |
17 |
|
T23 |
246 |
|
T1 |
28325 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2441107 |
1 |
|
|
T19 |
13 |
|
T23 |
118 |
|
T1 |
12895 |
| auto[1] |
auto[0] |
auto[1] |
357377 |
1 |
|
|
T23 |
7 |
|
T1 |
1996 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2438577 |
1 |
|
|
T19 |
4 |
|
T23 |
116 |
|
T1 |
11712 |
| auto[1] |
auto[1] |
auto[1] |
357732 |
1 |
|
|
T23 |
5 |
|
T1 |
1722 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |