Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T765 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1700309636 Jun 06 12:42:04 PM PDT 24 Jun 06 12:42:06 PM PDT 24 33927498 ps
T766 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3513345967 Jun 06 12:42:03 PM PDT 24 Jun 06 12:42:04 PM PDT 24 18522517 ps
T767 /workspace/coverage/cover_reg_top/29.gpio_intr_test.918202267 Jun 06 12:42:34 PM PDT 24 Jun 06 12:42:36 PM PDT 24 17691782 ps
T91 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3757807436 Jun 06 12:42:34 PM PDT 24 Jun 06 12:42:36 PM PDT 24 31196920 ps
T768 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.372965380 Jun 06 12:42:23 PM PDT 24 Jun 06 12:42:25 PM PDT 24 36953314 ps
T43 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3420368618 Jun 06 12:42:22 PM PDT 24 Jun 06 12:42:24 PM PDT 24 418805131 ps
T769 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3753768164 Jun 06 12:42:06 PM PDT 24 Jun 06 12:42:08 PM PDT 24 45840036 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2535976887 Jun 06 12:41:44 PM PDT 24 Jun 06 12:41:45 PM PDT 24 15908786 ps
T771 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3224771393 Jun 06 12:42:04 PM PDT 24 Jun 06 12:42:06 PM PDT 24 35271056 ps
T78 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3330205447 Jun 06 12:42:23 PM PDT 24 Jun 06 12:42:24 PM PDT 24 97544366 ps
T772 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.192257169 Jun 06 12:41:52 PM PDT 24 Jun 06 12:41:54 PM PDT 24 31297420 ps
T773 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2663346237 Jun 06 12:42:15 PM PDT 24 Jun 06 12:42:17 PM PDT 24 177169624 ps
T79 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3769102573 Jun 06 12:41:34 PM PDT 24 Jun 06 12:41:36 PM PDT 24 21479135 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3447597689 Jun 06 12:41:34 PM PDT 24 Jun 06 12:41:36 PM PDT 24 16198833 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2128488267 Jun 06 12:41:53 PM PDT 24 Jun 06 12:41:55 PM PDT 24 82925770 ps
T776 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.930286878 Jun 06 12:41:48 PM PDT 24 Jun 06 12:41:50 PM PDT 24 18707570 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2507507435 Jun 06 12:42:30 PM PDT 24 Jun 06 12:42:31 PM PDT 24 12967410 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1838639870 Jun 06 12:41:45 PM PDT 24 Jun 06 12:41:48 PM PDT 24 376757803 ps
T779 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.666234161 Jun 06 12:42:15 PM PDT 24 Jun 06 12:42:18 PM PDT 24 32922037 ps
T780 /workspace/coverage/cover_reg_top/28.gpio_intr_test.4270711796 Jun 06 12:42:34 PM PDT 24 Jun 06 12:42:36 PM PDT 24 11653408 ps
T781 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2420001770 Jun 06 12:41:53 PM PDT 24 Jun 06 12:41:55 PM PDT 24 49364934 ps
T782 /workspace/coverage/cover_reg_top/23.gpio_intr_test.336218076 Jun 06 12:42:34 PM PDT 24 Jun 06 12:42:36 PM PDT 24 100806310 ps
T783 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2572072876 Jun 06 12:42:36 PM PDT 24 Jun 06 12:42:37 PM PDT 24 25468212 ps
T80 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2795467839 Jun 06 12:42:20 PM PDT 24 Jun 06 12:42:21 PM PDT 24 25421200 ps
T784 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2828854349 Jun 06 12:42:20 PM PDT 24 Jun 06 12:42:22 PM PDT 24 87660559 ps
T785 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1126407367 Jun 06 12:42:06 PM PDT 24 Jun 06 12:42:08 PM PDT 24 69655441 ps
T92 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.379251279 Jun 06 12:41:35 PM PDT 24 Jun 06 12:41:36 PM PDT 24 437027420 ps
T786 /workspace/coverage/cover_reg_top/34.gpio_intr_test.4150370749 Jun 06 12:42:34 PM PDT 24 Jun 06 12:42:35 PM PDT 24 82408306 ps
T787 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1494661208 Jun 06 12:42:33 PM PDT 24 Jun 06 12:42:35 PM PDT 24 16025218 ps
T788 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3432134478 Jun 06 12:42:04 PM PDT 24 Jun 06 12:42:06 PM PDT 24 19163175 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.527294743 Jun 06 12:41:42 PM PDT 24 Jun 06 12:41:44 PM PDT 24 21959803 ps
T790 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4097300500 Jun 06 12:42:09 PM PDT 24 Jun 06 12:42:13 PM PDT 24 463663286 ps
T791 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.588124443 Jun 06 12:42:22 PM PDT 24 Jun 06 12:42:23 PM PDT 24 22910907 ps
T792 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3112454797 Jun 06 12:41:53 PM PDT 24 Jun 06 12:41:55 PM PDT 24 34258458 ps
T793 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1374511271 Jun 06 12:41:51 PM PDT 24 Jun 06 12:41:53 PM PDT 24 119092438 ps
T794 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.948322388 Jun 06 12:41:44 PM PDT 24 Jun 06 12:41:49 PM PDT 24 265406479 ps
T795 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2256691627 Jun 06 12:42:33 PM PDT 24 Jun 06 12:42:34 PM PDT 24 39261750 ps
T796 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1272774057 Jun 06 12:41:54 PM PDT 24 Jun 06 12:41:56 PM PDT 24 72611375 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3288688689 Jun 06 12:41:43 PM PDT 24 Jun 06 12:41:44 PM PDT 24 109714090 ps
T797 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3353407600 Jun 06 12:41:42 PM PDT 24 Jun 06 12:41:44 PM PDT 24 791663888 ps
T798 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1840922706 Jun 06 12:42:15 PM PDT 24 Jun 06 12:42:17 PM PDT 24 115776436 ps
T799 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2273018476 Jun 06 12:41:45 PM PDT 24 Jun 06 12:41:47 PM PDT 24 107733998 ps
T800 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4290567389 Jun 06 12:42:24 PM PDT 24 Jun 06 12:42:26 PM PDT 24 13905211 ps
T801 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1420337605 Jun 06 12:42:23 PM PDT 24 Jun 06 12:42:26 PM PDT 24 470859485 ps
T82 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1792584593 Jun 06 12:42:24 PM PDT 24 Jun 06 12:42:25 PM PDT 24 41784189 ps
T83 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1573002735 Jun 06 12:41:42 PM PDT 24 Jun 06 12:41:43 PM PDT 24 13049766 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3676649220 Jun 06 12:42:22 PM PDT 24 Jun 06 12:42:25 PM PDT 24 48555286 ps
T803 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2698870180 Jun 06 12:42:37 PM PDT 24 Jun 06 12:42:38 PM PDT 24 14716117 ps
T804 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.923975178 Jun 06 12:42:06 PM PDT 24 Jun 06 12:42:08 PM PDT 24 30507932 ps
T805 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2967267539 Jun 06 12:42:13 PM PDT 24 Jun 06 12:42:15 PM PDT 24 39098928 ps
T806 /workspace/coverage/cover_reg_top/3.gpio_intr_test.4135631584 Jun 06 12:41:43 PM PDT 24 Jun 06 12:41:44 PM PDT 24 41902974 ps
T807 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2413301303 Jun 06 12:42:22 PM PDT 24 Jun 06 12:42:24 PM PDT 24 193790051 ps
T808 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3071302610 Jun 06 12:42:33 PM PDT 24 Jun 06 12:42:35 PM PDT 24 109260632 ps
T809 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2181058775 Jun 06 12:42:23 PM PDT 24 Jun 06 12:42:25 PM PDT 24 28992630 ps
T84 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.554704920 Jun 06 12:41:34 PM PDT 24 Jun 06 12:41:36 PM PDT 24 31881924 ps
T810 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3024423787 Jun 06 12:41:53 PM PDT 24 Jun 06 12:41:55 PM PDT 24 120337402 ps
T811 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2049204344 Jun 06 12:41:47 PM PDT 24 Jun 06 12:41:48 PM PDT 24 63980193 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_intr_test.890271407 Jun 06 12:41:53 PM PDT 24 Jun 06 12:41:55 PM PDT 24 28867886 ps
T813 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2704685593 Jun 06 12:42:37 PM PDT 24 Jun 06 12:42:38 PM PDT 24 14523301 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4138432569 Jun 06 12:41:34 PM PDT 24 Jun 06 12:41:37 PM PDT 24 148672939 ps
T815 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1164646573 Jun 06 12:41:46 PM PDT 24 Jun 06 12:41:48 PM PDT 24 66104995 ps
T816 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2535442293 Jun 06 12:42:06 PM PDT 24 Jun 06 12:42:08 PM PDT 24 15740615 ps
T817 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1829356165 Jun 06 12:42:15 PM PDT 24 Jun 06 12:42:18 PM PDT 24 108990600 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3129780571 Jun 06 12:41:48 PM PDT 24 Jun 06 12:41:49 PM PDT 24 13924508 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.735283698 Jun 06 12:42:25 PM PDT 24 Jun 06 12:42:27 PM PDT 24 33449764 ps
T85 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1566283716 Jun 06 12:41:44 PM PDT 24 Jun 06 12:41:46 PM PDT 24 11464296 ps
T86 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.708366326 Jun 06 12:41:46 PM PDT 24 Jun 06 12:41:47 PM PDT 24 66838294 ps
T820 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3163506438 Jun 06 12:42:34 PM PDT 24 Jun 06 12:42:36 PM PDT 24 19216051 ps
T821 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3154595969 Jun 06 12:42:14 PM PDT 24 Jun 06 12:42:16 PM PDT 24 42763344 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.680887120 Jun 06 12:41:49 PM PDT 24 Jun 06 12:41:50 PM PDT 24 75286754 ps
T823 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.783591743 Jun 06 12:42:30 PM PDT 24 Jun 06 12:42:32 PM PDT 24 90232075 ps
T824 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3355584258 Jun 06 12:42:35 PM PDT 24 Jun 06 12:42:37 PM PDT 24 42149055 ps
T825 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3858647817 Jun 06 12:42:21 PM PDT 24 Jun 06 12:42:22 PM PDT 24 17361333 ps
T826 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.770812563 Jun 06 12:42:14 PM PDT 24 Jun 06 12:42:16 PM PDT 24 48080614 ps
T827 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.105388001 Jun 06 12:42:15 PM PDT 24 Jun 06 12:42:17 PM PDT 24 44858732 ps
T828 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2562521372 Jun 06 12:42:37 PM PDT 24 Jun 06 12:42:38 PM PDT 24 49935192 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.949196323 Jun 06 12:41:45 PM PDT 24 Jun 06 12:41:47 PM PDT 24 15244459 ps
T830 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3026540039 Jun 06 12:42:19 PM PDT 24 Jun 06 12:42:20 PM PDT 24 27973269 ps
T831 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2380525684 Jun 06 12:42:42 PM PDT 24 Jun 06 12:42:43 PM PDT 24 14412371 ps
T832 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2111645616 Jun 06 12:42:32 PM PDT 24 Jun 06 12:42:33 PM PDT 24 23478750 ps
T833 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2025279381 Jun 06 12:42:23 PM PDT 24 Jun 06 12:42:25 PM PDT 24 11540521 ps
T87 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.391911061 Jun 06 12:42:08 PM PDT 24 Jun 06 12:42:10 PM PDT 24 122555734 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.691666933 Jun 06 12:41:44 PM PDT 24 Jun 06 12:41:46 PM PDT 24 91625008 ps
T835 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2850273459 Jun 06 12:41:34 PM PDT 24 Jun 06 12:41:36 PM PDT 24 36474531 ps
T836 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2610006655 Jun 06 12:41:43 PM PDT 24 Jun 06 12:41:45 PM PDT 24 12679863 ps
T110 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2285935163 Jun 06 12:41:35 PM PDT 24 Jun 06 12:41:37 PM PDT 24 85417270 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4182515619 Jun 06 12:41:54 PM PDT 24 Jun 06 12:41:58 PM PDT 24 54830076 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3332676264 Jun 06 12:41:40 PM PDT 24 Jun 06 12:41:41 PM PDT 24 37132190 ps
T839 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3044378290 Jun 06 12:42:22 PM PDT 24 Jun 06 12:42:23 PM PDT 24 21620654 ps
T840 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4038305600 Jun 06 12:42:12 PM PDT 24 Jun 06 12:42:14 PM PDT 24 368309921 ps
T841 /workspace/coverage/cover_reg_top/35.gpio_intr_test.804357219 Jun 06 12:42:35 PM PDT 24 Jun 06 12:42:37 PM PDT 24 27412678 ps
T842 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.751535787 Jun 06 12:42:51 PM PDT 24 Jun 06 12:42:53 PM PDT 24 58943952 ps
T843 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.731509100 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:05 PM PDT 24 42214996 ps
T844 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2018089348 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 152421321 ps
T845 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1652334010 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 93729649 ps
T846 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.244132866 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:46 PM PDT 24 132511746 ps
T847 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3054106795 Jun 06 12:42:37 PM PDT 24 Jun 06 12:42:39 PM PDT 24 116884726 ps
T848 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2803597424 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:08 PM PDT 24 50658443 ps
T849 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2543804889 Jun 06 12:42:38 PM PDT 24 Jun 06 12:42:40 PM PDT 24 43925794 ps
T850 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3625461039 Jun 06 12:42:44 PM PDT 24 Jun 06 12:42:47 PM PDT 24 67485558 ps
T851 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1192957850 Jun 06 12:42:51 PM PDT 24 Jun 06 12:42:53 PM PDT 24 68685276 ps
T852 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2106555987 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 35983106 ps
T853 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1501674112 Jun 06 12:42:49 PM PDT 24 Jun 06 12:42:51 PM PDT 24 204062906 ps
T854 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032152953 Jun 06 12:42:55 PM PDT 24 Jun 06 12:42:57 PM PDT 24 59088452 ps
T855 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3583431056 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:08 PM PDT 24 81534450 ps
T856 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1171257028 Jun 06 12:42:56 PM PDT 24 Jun 06 12:42:58 PM PDT 24 354364531 ps
T857 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2965629742 Jun 06 12:42:44 PM PDT 24 Jun 06 12:42:46 PM PDT 24 42300356 ps
T858 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.631186598 Jun 06 12:42:37 PM PDT 24 Jun 06 12:42:39 PM PDT 24 187299665 ps
T859 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.276236841 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:07 PM PDT 24 29694426 ps
T860 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2151002776 Jun 06 12:42:36 PM PDT 24 Jun 06 12:42:38 PM PDT 24 48821358 ps
T861 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126870029 Jun 06 12:43:10 PM PDT 24 Jun 06 12:43:12 PM PDT 24 102261844 ps
T862 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3920492537 Jun 06 12:42:57 PM PDT 24 Jun 06 12:42:58 PM PDT 24 383473333 ps
T863 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.919974499 Jun 06 12:42:49 PM PDT 24 Jun 06 12:42:51 PM PDT 24 449673100 ps
T864 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2627178608 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:07 PM PDT 24 284827074 ps
T865 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.948868406 Jun 06 12:43:07 PM PDT 24 Jun 06 12:43:09 PM PDT 24 66464208 ps
T866 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.710578187 Jun 06 12:42:52 PM PDT 24 Jun 06 12:42:54 PM PDT 24 149366971 ps
T867 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2348443087 Jun 06 12:42:44 PM PDT 24 Jun 06 12:42:47 PM PDT 24 143619027 ps
T868 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1215158479 Jun 06 12:42:45 PM PDT 24 Jun 06 12:42:48 PM PDT 24 88750368 ps
T869 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.624101562 Jun 06 12:42:38 PM PDT 24 Jun 06 12:42:40 PM PDT 24 34070234 ps
T870 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1916885218 Jun 06 12:42:45 PM PDT 24 Jun 06 12:42:48 PM PDT 24 103782154 ps
T871 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3274432424 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:08 PM PDT 24 196202651 ps
T872 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2773730087 Jun 06 12:42:45 PM PDT 24 Jun 06 12:42:48 PM PDT 24 29059762 ps
T873 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837405366 Jun 06 12:42:52 PM PDT 24 Jun 06 12:42:54 PM PDT 24 107552825 ps
T874 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2978384183 Jun 06 12:42:53 PM PDT 24 Jun 06 12:42:55 PM PDT 24 23560520 ps
T875 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.510317454 Jun 06 12:43:03 PM PDT 24 Jun 06 12:43:05 PM PDT 24 90708719 ps
T876 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.670922653 Jun 06 12:42:49 PM PDT 24 Jun 06 12:42:51 PM PDT 24 274785963 ps
T877 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1349475066 Jun 06 12:42:56 PM PDT 24 Jun 06 12:42:58 PM PDT 24 35092702 ps
T878 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.185672719 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:46 PM PDT 24 55684096 ps
T879 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2549087717 Jun 06 12:42:55 PM PDT 24 Jun 06 12:42:57 PM PDT 24 112195795 ps
T880 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3883833471 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:45 PM PDT 24 30975378 ps
T881 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3455447634 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 254758063 ps
T882 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2578198149 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:06 PM PDT 24 375175914 ps
T883 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.835309985 Jun 06 12:42:55 PM PDT 24 Jun 06 12:42:57 PM PDT 24 37034810 ps
T884 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2285686149 Jun 06 12:43:02 PM PDT 24 Jun 06 12:43:04 PM PDT 24 30806520 ps
T885 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1308605983 Jun 06 12:43:02 PM PDT 24 Jun 06 12:43:03 PM PDT 24 65548032 ps
T886 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466624347 Jun 06 12:43:21 PM PDT 24 Jun 06 12:43:22 PM PDT 24 57276433 ps
T887 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2821311682 Jun 06 12:42:55 PM PDT 24 Jun 06 12:42:57 PM PDT 24 124519346 ps
T888 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2224847743 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:07 PM PDT 24 188241064 ps
T889 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.45086963 Jun 06 12:43:06 PM PDT 24 Jun 06 12:43:08 PM PDT 24 35948818 ps
T890 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2365170662 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 101189767 ps
T891 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1942951841 Jun 06 12:42:44 PM PDT 24 Jun 06 12:42:47 PM PDT 24 247186363 ps
T892 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3730141602 Jun 06 12:42:52 PM PDT 24 Jun 06 12:42:54 PM PDT 24 218498295 ps
T893 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1201011896 Jun 06 12:43:03 PM PDT 24 Jun 06 12:43:04 PM PDT 24 41239579 ps
T894 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3643450426 Jun 06 12:43:10 PM PDT 24 Jun 06 12:43:12 PM PDT 24 115687732 ps
T895 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3828267726 Jun 06 12:42:37 PM PDT 24 Jun 06 12:42:39 PM PDT 24 427569403 ps
T896 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3570805227 Jun 06 12:42:38 PM PDT 24 Jun 06 12:42:40 PM PDT 24 41514066 ps
T897 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.41909209 Jun 06 12:42:55 PM PDT 24 Jun 06 12:42:57 PM PDT 24 140217506 ps
T898 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1134234268 Jun 06 12:42:57 PM PDT 24 Jun 06 12:42:59 PM PDT 24 76649608 ps
T899 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.255856962 Jun 06 12:42:52 PM PDT 24 Jun 06 12:42:54 PM PDT 24 181370499 ps
T900 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2668879590 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:08 PM PDT 24 285759202 ps
T901 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2949018331 Jun 06 12:42:50 PM PDT 24 Jun 06 12:42:52 PM PDT 24 40983592 ps
T902 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2294984049 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 54451389 ps
T903 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3659717616 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:46 PM PDT 24 174395006 ps
T904 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4062856702 Jun 06 12:43:06 PM PDT 24 Jun 06 12:43:08 PM PDT 24 162115691 ps
T905 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3867177485 Jun 06 12:42:45 PM PDT 24 Jun 06 12:42:48 PM PDT 24 153803315 ps
T906 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3953122521 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:06 PM PDT 24 57384618 ps
T907 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3111930277 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:57 PM PDT 24 307227146 ps
T908 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1156808150 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:46 PM PDT 24 35693397 ps
T909 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1583570505 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:06 PM PDT 24 23752596 ps
T910 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3516726764 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:45 PM PDT 24 54970574 ps
T911 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.886984489 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:45 PM PDT 24 180838860 ps
T912 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4293367153 Jun 06 12:42:42 PM PDT 24 Jun 06 12:42:44 PM PDT 24 218374865 ps
T913 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1977278509 Jun 06 12:42:43 PM PDT 24 Jun 06 12:42:46 PM PDT 24 43039080 ps
T914 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1566859411 Jun 06 12:43:05 PM PDT 24 Jun 06 12:43:07 PM PDT 24 147816715 ps
T915 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2286465739 Jun 06 12:43:03 PM PDT 24 Jun 06 12:43:04 PM PDT 24 38427653 ps
T916 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3082322543 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 101941506 ps
T917 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3031364629 Jun 06 12:42:57 PM PDT 24 Jun 06 12:42:59 PM PDT 24 49444287 ps
T918 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2793204867 Jun 06 12:42:38 PM PDT 24 Jun 06 12:42:40 PM PDT 24 46552644 ps
T919 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3813385146 Jun 06 12:42:35 PM PDT 24 Jun 06 12:42:38 PM PDT 24 177400842 ps
T920 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1911015950 Jun 06 12:42:44 PM PDT 24 Jun 06 12:42:46 PM PDT 24 55342847 ps
T921 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1193523703 Jun 06 12:42:53 PM PDT 24 Jun 06 12:42:55 PM PDT 24 161292846 ps
T922 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138297578 Jun 06 12:43:03 PM PDT 24 Jun 06 12:43:05 PM PDT 24 88049252 ps
T923 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2216216773 Jun 06 12:42:39 PM PDT 24 Jun 06 12:42:40 PM PDT 24 219747193 ps
T924 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1006178346 Jun 06 12:42:57 PM PDT 24 Jun 06 12:42:59 PM PDT 24 165573519 ps
T925 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1033699062 Jun 06 12:42:53 PM PDT 24 Jun 06 12:42:56 PM PDT 24 82324779 ps
T926 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1310559022 Jun 06 12:42:53 PM PDT 24 Jun 06 12:42:55 PM PDT 24 37606799 ps
T927 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2909828409 Jun 06 12:42:38 PM PDT 24 Jun 06 12:42:40 PM PDT 24 164511476 ps
T928 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3798816449 Jun 06 12:42:36 PM PDT 24 Jun 06 12:42:38 PM PDT 24 71035124 ps
T929 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1669975333 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:06 PM PDT 24 143976075 ps
T930 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1697194284 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:05 PM PDT 24 49735730 ps
T931 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1541651390 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:06 PM PDT 24 42297358 ps
T932 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2908126165 Jun 06 12:43:03 PM PDT 24 Jun 06 12:43:05 PM PDT 24 37094607 ps
T933 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1074902217 Jun 06 12:42:45 PM PDT 24 Jun 06 12:42:48 PM PDT 24 40357447 ps
T934 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3435633799 Jun 06 12:43:00 PM PDT 24 Jun 06 12:43:02 PM PDT 24 688715985 ps
T935 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3134082183 Jun 06 12:42:41 PM PDT 24 Jun 06 12:42:43 PM PDT 24 575938570 ps
T936 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3569228401 Jun 06 12:42:54 PM PDT 24 Jun 06 12:42:56 PM PDT 24 76623832 ps
T937 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3214439184 Jun 06 12:43:02 PM PDT 24 Jun 06 12:43:04 PM PDT 24 567397122 ps
T938 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3577006461 Jun 06 12:43:04 PM PDT 24 Jun 06 12:43:06 PM PDT 24 124375503 ps
T939 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1020466042 Jun 06 12:42:42 PM PDT 24 Jun 06 12:42:45 PM PDT 24 315301720 ps
T940 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2489737337 Jun 06 12:43:06 PM PDT 24 Jun 06 12:43:08 PM PDT 24 36686170 ps
T941 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.549115309 Jun 06 12:42:53 PM PDT 24 Jun 06 12:42:55 PM PDT 24 281527339 ps

Test location /workspace/coverage/default/38.gpio_full_random.953351565
Short name T2
Test name
Test status
Simulation time 240395668 ps
CPU time 1.01 seconds
Started Jun 06 12:45:42 PM PDT 24
Finished Jun 06 12:45:45 PM PDT 24
Peak memory 197700 kb
Host smart-be2ff123-8b42-49d4-821d-e38a95504f94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953351565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.953351565
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4136213867
Short name T11
Test name
Test status
Simulation time 115807258 ps
CPU time 2.58 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 197240 kb
Host smart-046f5e12-0bce-4546-b9f5-2e94f04bb2e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136213867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4136213867
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.7672757
Short name T16
Test name
Test status
Simulation time 38940827996 ps
CPU time 628.66 seconds
Started Jun 06 12:44:35 PM PDT 24
Finished Jun 06 12:55:04 PM PDT 24
Peak memory 198220 kb
Host smart-713dde1b-b904-42ee-af40-f6cf21da9127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=7672757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.7672757
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.202496147
Short name T30
Test name
Test status
Simulation time 173260189 ps
CPU time 1.44 seconds
Started Jun 06 12:42:12 PM PDT 24
Finished Jun 06 12:42:14 PM PDT 24
Peak memory 197884 kb
Host smart-c7ff61d2-758a-488e-a6bc-b816e6554b7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202496147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.202496147
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2671610309
Short name T68
Test name
Test status
Simulation time 10601771 ps
CPU time 0.59 seconds
Started Jun 06 12:42:16 PM PDT 24
Finished Jun 06 12:42:18 PM PDT 24
Peak memory 194688 kb
Host smart-e962de81-05d5-4fe7-a91a-8d50f5b93654
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671610309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2671610309
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/default/38.gpio_stress_all.288021687
Short name T1
Test name
Test status
Simulation time 9400291129 ps
CPU time 111.56 seconds
Started Jun 06 12:45:50 PM PDT 24
Finished Jun 06 12:47:42 PM PDT 24
Peak memory 198156 kb
Host smart-f18c3049-44b3-4daf-a689-59e776f94213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288021687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.288021687
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.647379015
Short name T178
Test name
Test status
Simulation time 103349092 ps
CPU time 0.58 seconds
Started Jun 06 12:43:46 PM PDT 24
Finished Jun 06 12:43:47 PM PDT 24
Peak memory 193880 kb
Host smart-34227dc2-c434-4b95-9bf7-baf5058ad1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647379015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.647379015
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2142733116
Short name T31
Test name
Test status
Simulation time 271747334 ps
CPU time 0.89 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 213776 kb
Host smart-edf06f94-38e2-4497-8d14-f252bf06ea0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142733116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2142733116
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4038305600
Short name T840
Test name
Test status
Simulation time 368309921 ps
CPU time 1.39 seconds
Started Jun 06 12:42:12 PM PDT 24
Finished Jun 06 12:42:14 PM PDT 24
Peak memory 197688 kb
Host smart-dcba4165-2a8e-48a2-be87-107b91b9bc07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038305600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.4038305600
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3769102573
Short name T79
Test name
Test status
Simulation time 21479135 ps
CPU time 0.84 seconds
Started Jun 06 12:41:34 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 195916 kb
Host smart-a6ab800a-8205-4cf4-90e5-526ed2076ecd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769102573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3769102573
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.379251279
Short name T92
Test name
Test status
Simulation time 437027420 ps
CPU time 0.8 seconds
Started Jun 06 12:41:35 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 196928 kb
Host smart-06e5470c-3e4a-4434-ba2c-f8f9ce9e3f18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379251279 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.379251279
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3420368618
Short name T43
Test name
Test status
Simulation time 418805131 ps
CPU time 1.11 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:24 PM PDT 24
Peak memory 197952 kb
Host smart-53071de2-6d15-4625-b989-2fc78c08f9d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420368618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3420368618
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3275030726
Short name T751
Test name
Test status
Simulation time 94566563 ps
CPU time 1.57 seconds
Started Jun 06 12:41:37 PM PDT 24
Finished Jun 06 12:41:40 PM PDT 24
Peak memory 197808 kb
Host smart-983e0260-f468-4788-b346-8be95a0f16fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275030726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3275030726
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.135480867
Short name T105
Test name
Test status
Simulation time 21367191 ps
CPU time 0.66 seconds
Started Jun 06 12:41:36 PM PDT 24
Finished Jun 06 12:41:37 PM PDT 24
Peak memory 194776 kb
Host smart-1664a936-c256-4c64-9d44-9e09f7842cc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135480867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.135480867
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2850273459
Short name T835
Test name
Test status
Simulation time 36474531 ps
CPU time 0.73 seconds
Started Jun 06 12:41:34 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 197792 kb
Host smart-22fdd97b-e302-42e5-96ae-92d713af869c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850273459 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2850273459
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.140542287
Short name T733
Test name
Test status
Simulation time 11998461 ps
CPU time 0.59 seconds
Started Jun 06 12:41:33 PM PDT 24
Finished Jun 06 12:41:35 PM PDT 24
Peak memory 193088 kb
Host smart-25714c25-b5c2-4dcd-890a-84b8c8ac1d25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140542287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.140542287
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.804990598
Short name T731
Test name
Test status
Simulation time 77421591 ps
CPU time 0.58 seconds
Started Jun 06 12:41:33 PM PDT 24
Finished Jun 06 12:41:35 PM PDT 24
Peak memory 193520 kb
Host smart-a4d8cd8e-a6cf-485c-92a4-2c69c87678a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804990598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.804990598
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4138432569
Short name T814
Test name
Test status
Simulation time 148672939 ps
CPU time 2.27 seconds
Started Jun 06 12:41:34 PM PDT 24
Finished Jun 06 12:41:37 PM PDT 24
Peak memory 197880 kb
Host smart-0b3fa3f8-075e-445e-9fdb-2496de5cd6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138432569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4138432569
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1870953611
Short name T42
Test name
Test status
Simulation time 102410256 ps
CPU time 1.47 seconds
Started Jun 06 12:41:35 PM PDT 24
Finished Jun 06 12:41:38 PM PDT 24
Peak memory 197896 kb
Host smart-00bc4406-839e-4c27-be9c-7dba5d4448d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870953611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1870953611
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.554704920
Short name T84
Test name
Test status
Simulation time 31881924 ps
CPU time 0.65 seconds
Started Jun 06 12:41:34 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 194184 kb
Host smart-116da1ec-6fe2-4e76-ae39-365cb2920292
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554704920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.554704920
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4037959994
Short name T71
Test name
Test status
Simulation time 382943658 ps
CPU time 2.91 seconds
Started Jun 06 12:41:44 PM PDT 24
Finished Jun 06 12:41:48 PM PDT 24
Peak memory 196560 kb
Host smart-d1628b08-0b9c-4173-b133-42ae0e06f989
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037959994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4037959994
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3288688689
Short name T81
Test name
Test status
Simulation time 109714090 ps
CPU time 0.64 seconds
Started Jun 06 12:41:43 PM PDT 24
Finished Jun 06 12:41:44 PM PDT 24
Peak memory 194844 kb
Host smart-6d53b98b-9b9b-4bd8-b1d5-b6986a052e44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288688689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3288688689
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3447597689
Short name T774
Test name
Test status
Simulation time 16198833 ps
CPU time 0.66 seconds
Started Jun 06 12:41:34 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 196928 kb
Host smart-8f8c1c44-dcca-447f-8b54-e7d0c98f66be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447597689 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3447597689
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3589586962
Short name T106
Test name
Test status
Simulation time 15400347 ps
CPU time 0.63 seconds
Started Jun 06 12:41:32 PM PDT 24
Finished Jun 06 12:41:33 PM PDT 24
Peak memory 194592 kb
Host smart-fce10c69-fdf7-4268-adcc-05761e0bc43f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589586962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3589586962
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1605585854
Short name T740
Test name
Test status
Simulation time 13939672 ps
CPU time 0.58 seconds
Started Jun 06 12:41:34 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 194264 kb
Host smart-ed099738-0d0d-4c47-8ded-04f41b01ba0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605585854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1605585854
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2516990710
Short name T88
Test name
Test status
Simulation time 38969290 ps
CPU time 0.72 seconds
Started Jun 06 12:41:35 PM PDT 24
Finished Jun 06 12:41:36 PM PDT 24
Peak memory 195304 kb
Host smart-f8e0d84c-5881-4fb3-848e-8ecc9af03c47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516990710 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2516990710
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3193657534
Short name T727
Test name
Test status
Simulation time 243963425 ps
CPU time 1.46 seconds
Started Jun 06 12:41:35 PM PDT 24
Finished Jun 06 12:41:37 PM PDT 24
Peak memory 197892 kb
Host smart-6a60da56-69f7-4f05-99b6-9bfdf1aff1a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193657534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3193657534
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2285935163
Short name T110
Test name
Test status
Simulation time 85417270 ps
CPU time 1.14 seconds
Started Jun 06 12:41:35 PM PDT 24
Finished Jun 06 12:41:37 PM PDT 24
Peak memory 197888 kb
Host smart-f71dfa2b-707e-4cfb-a2d4-b6c61cc1efd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285935163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2285935163
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.428605375
Short name T737
Test name
Test status
Simulation time 114545186 ps
CPU time 0.92 seconds
Started Jun 06 12:42:05 PM PDT 24
Finished Jun 06 12:42:07 PM PDT 24
Peak memory 197860 kb
Host smart-235f3da5-097e-4e1d-b07d-ccdcd221e807
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428605375 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.428605375
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3753768164
Short name T769
Test name
Test status
Simulation time 45840036 ps
CPU time 0.58 seconds
Started Jun 06 12:42:06 PM PDT 24
Finished Jun 06 12:42:08 PM PDT 24
Peak memory 194652 kb
Host smart-d66deacd-8cb4-48d2-91f3-5bccd12e8922
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753768164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3753768164
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.883299311
Short name T763
Test name
Test status
Simulation time 30360984 ps
CPU time 0.61 seconds
Started Jun 06 12:42:14 PM PDT 24
Finished Jun 06 12:42:16 PM PDT 24
Peak memory 193540 kb
Host smart-15b8666e-663a-4f3f-9e4d-9cdb7c77d0f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883299311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.883299311
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.741504957
Short name T75
Test name
Test status
Simulation time 41194561 ps
CPU time 0.69 seconds
Started Jun 06 12:42:08 PM PDT 24
Finished Jun 06 12:42:09 PM PDT 24
Peak memory 194576 kb
Host smart-45b1dd2a-eb2e-454f-9395-bfa7c66a2ac0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741504957 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.741504957
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.685328946
Short name T755
Test name
Test status
Simulation time 82724124 ps
CPU time 2.46 seconds
Started Jun 06 12:42:12 PM PDT 24
Finished Jun 06 12:42:15 PM PDT 24
Peak memory 197876 kb
Host smart-95f4c3ab-9e9e-4a27-8b2c-5979e359a70d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685328946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.685328946
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.666234161
Short name T779
Test name
Test status
Simulation time 32922037 ps
CPU time 1.48 seconds
Started Jun 06 12:42:15 PM PDT 24
Finished Jun 06 12:42:18 PM PDT 24
Peak memory 197908 kb
Host smart-778456fe-baea-48a2-993b-a7adc84b79d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666234161 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.666234161
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2016232081
Short name T762
Test name
Test status
Simulation time 17923122 ps
CPU time 0.61 seconds
Started Jun 06 12:42:14 PM PDT 24
Finished Jun 06 12:42:16 PM PDT 24
Peak memory 195336 kb
Host smart-6bd631df-a381-4a42-915f-56bc47c98deb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016232081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2016232081
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3622554053
Short name T752
Test name
Test status
Simulation time 15386206 ps
CPU time 0.56 seconds
Started Jun 06 12:42:13 PM PDT 24
Finished Jun 06 12:42:14 PM PDT 24
Peak memory 193560 kb
Host smart-4bc02cf8-5b94-4357-bb3f-292e296fbb52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622554053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3622554053
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3757807436
Short name T91
Test name
Test status
Simulation time 31196920 ps
CPU time 0.71 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 195236 kb
Host smart-afca25ab-de6b-4ed5-9652-5a17f3efabbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757807436 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3757807436
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1829356165
Short name T817
Test name
Test status
Simulation time 108990600 ps
CPU time 2.11 seconds
Started Jun 06 12:42:15 PM PDT 24
Finished Jun 06 12:42:18 PM PDT 24
Peak memory 197968 kb
Host smart-5d5bf9de-1614-4f21-9835-54108ea3057e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829356165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1829356165
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3192128743
Short name T39
Test name
Test status
Simulation time 127521046 ps
CPU time 1.21 seconds
Started Jun 06 12:42:14 PM PDT 24
Finished Jun 06 12:42:16 PM PDT 24
Peak memory 197788 kb
Host smart-99eb7e92-6a84-41f3-801e-f292509bef7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192128743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3192128743
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.770812563
Short name T826
Test name
Test status
Simulation time 48080614 ps
CPU time 0.83 seconds
Started Jun 06 12:42:14 PM PDT 24
Finished Jun 06 12:42:16 PM PDT 24
Peak memory 197760 kb
Host smart-4ec8f764-3468-488e-bb53-8ab540698866
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770812563 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.770812563
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3154595969
Short name T821
Test name
Test status
Simulation time 42763344 ps
CPU time 0.61 seconds
Started Jun 06 12:42:14 PM PDT 24
Finished Jun 06 12:42:16 PM PDT 24
Peak memory 194280 kb
Host smart-d2cf49ad-dc73-4223-af25-5de4a136af91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154595969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3154595969
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1840922706
Short name T798
Test name
Test status
Simulation time 115776436 ps
CPU time 0.59 seconds
Started Jun 06 12:42:15 PM PDT 24
Finished Jun 06 12:42:17 PM PDT 24
Peak memory 194240 kb
Host smart-53177d58-7480-4a35-9a28-4ff4b6377b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840922706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1840922706
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3026540039
Short name T830
Test name
Test status
Simulation time 27973269 ps
CPU time 0.77 seconds
Started Jun 06 12:42:19 PM PDT 24
Finished Jun 06 12:42:20 PM PDT 24
Peak memory 196076 kb
Host smart-65fceb61-86b4-4ffb-b969-9dd7369340b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026540039 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3026540039
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1883018905
Short name T739
Test name
Test status
Simulation time 45061298 ps
CPU time 2.21 seconds
Started Jun 06 12:42:14 PM PDT 24
Finished Jun 06 12:42:17 PM PDT 24
Peak memory 197900 kb
Host smart-dad1f3ed-08d4-4ffd-83de-1cb069b2b4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883018905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1883018905
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2967267539
Short name T805
Test name
Test status
Simulation time 39098928 ps
CPU time 0.98 seconds
Started Jun 06 12:42:13 PM PDT 24
Finished Jun 06 12:42:15 PM PDT 24
Peak memory 197888 kb
Host smart-aef15562-519e-4aba-9e21-39cebdf54b4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967267539 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2967267539
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3858647817
Short name T825
Test name
Test status
Simulation time 17361333 ps
CPU time 0.61 seconds
Started Jun 06 12:42:21 PM PDT 24
Finished Jun 06 12:42:22 PM PDT 24
Peak memory 193688 kb
Host smart-3631630a-5349-47e6-abac-845f399287e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858647817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3858647817
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.105388001
Short name T827
Test name
Test status
Simulation time 44858732 ps
CPU time 0.89 seconds
Started Jun 06 12:42:15 PM PDT 24
Finished Jun 06 12:42:17 PM PDT 24
Peak memory 197492 kb
Host smart-d621fbdd-5d6d-4886-8a70-18cea9310667
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105388001 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.105388001
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2663346237
Short name T773
Test name
Test status
Simulation time 177169624 ps
CPU time 1.23 seconds
Started Jun 06 12:42:15 PM PDT 24
Finished Jun 06 12:42:17 PM PDT 24
Peak memory 197936 kb
Host smart-403bf2f7-2a24-43e5-a08c-adf060dd1960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663346237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2663346237
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2893678224
Short name T38
Test name
Test status
Simulation time 48152666 ps
CPU time 0.91 seconds
Started Jun 06 12:42:11 PM PDT 24
Finished Jun 06 12:42:12 PM PDT 24
Peak memory 197704 kb
Host smart-121d3b90-6e69-4bfc-8e44-e070c9f1034d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893678224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2893678224
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3890975400
Short name T759
Test name
Test status
Simulation time 33020615 ps
CPU time 1.57 seconds
Started Jun 06 12:42:24 PM PDT 24
Finished Jun 06 12:42:27 PM PDT 24
Peak memory 197960 kb
Host smart-41b51aa5-8e11-4116-8ac6-505dc8eef504
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890975400 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3890975400
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2795467839
Short name T80
Test name
Test status
Simulation time 25421200 ps
CPU time 0.63 seconds
Started Jun 06 12:42:20 PM PDT 24
Finished Jun 06 12:42:21 PM PDT 24
Peak memory 194720 kb
Host smart-50a29cdc-d941-4ac3-8b1d-7d2e6a6bb7f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795467839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2795467839
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1828472355
Short name T750
Test name
Test status
Simulation time 18269385 ps
CPU time 0.6 seconds
Started Jun 06 12:42:25 PM PDT 24
Finished Jun 06 12:42:27 PM PDT 24
Peak memory 193604 kb
Host smart-cb606d0f-3a72-48ed-b7d8-a8fc1c9986a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828472355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1828472355
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3044378290
Short name T839
Test name
Test status
Simulation time 21620654 ps
CPU time 0.85 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:23 PM PDT 24
Peak memory 196844 kb
Host smart-2dba9b92-5b35-40b0-aace-8decdf846c87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044378290 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3044378290
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3676649220
Short name T802
Test name
Test status
Simulation time 48555286 ps
CPU time 2.46 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 197908 kb
Host smart-d618017f-454f-4156-b06c-f4c58aa586f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676649220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3676649220
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2534953451
Short name T28
Test name
Test status
Simulation time 1348146932 ps
CPU time 1.14 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:26 PM PDT 24
Peak memory 197904 kb
Host smart-49aae640-0ca7-4c46-8a5f-d8eb2552876c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534953451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2534953451
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2229253120
Short name T744
Test name
Test status
Simulation time 84647851 ps
CPU time 1.1 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 197796 kb
Host smart-cb76beb5-eff1-4381-b2c3-ed1a1ad3c7a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229253120 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2229253120
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2025279381
Short name T833
Test name
Test status
Simulation time 11540521 ps
CPU time 0.59 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 194264 kb
Host smart-96e8034c-cd8e-4966-b75d-d132aecf0a6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025279381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2025279381
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2181058775
Short name T809
Test name
Test status
Simulation time 28992630 ps
CPU time 0.6 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 193600 kb
Host smart-be66d2f6-9434-49c1-9273-65486a189835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181058775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2181058775
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.316330999
Short name T77
Test name
Test status
Simulation time 515314161 ps
CPU time 0.76 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 195816 kb
Host smart-d4cbdfc9-6a83-4219-aa73-deb5a294fc29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316330999 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.316330999
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2919667091
Short name T758
Test name
Test status
Simulation time 49611328 ps
CPU time 1.14 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 197820 kb
Host smart-386ec287-8b30-4f83-ab68-b8e4aa78a891
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919667091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2919667091
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2828854349
Short name T784
Test name
Test status
Simulation time 87660559 ps
CPU time 0.75 seconds
Started Jun 06 12:42:20 PM PDT 24
Finished Jun 06 12:42:22 PM PDT 24
Peak memory 197520 kb
Host smart-b206eb1d-deaf-46a3-9d52-33246b73730a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828854349 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2828854349
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1792584593
Short name T82
Test name
Test status
Simulation time 41784189 ps
CPU time 0.57 seconds
Started Jun 06 12:42:24 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 193152 kb
Host smart-f33daf38-b245-4592-953b-abf935010400
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792584593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1792584593
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3565361989
Short name T748
Test name
Test status
Simulation time 29236991 ps
CPU time 0.58 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 193552 kb
Host smart-5532b44f-baa5-46b1-8ad8-1fc63c0d32be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565361989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3565361989
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2454858007
Short name T90
Test name
Test status
Simulation time 28130350 ps
CPU time 0.75 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:24 PM PDT 24
Peak memory 196704 kb
Host smart-d137787f-1445-498e-b040-727a5df6326b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454858007 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2454858007
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.870243505
Short name T722
Test name
Test status
Simulation time 156593516 ps
CPU time 1.18 seconds
Started Jun 06 12:42:24 PM PDT 24
Finished Jun 06 12:42:26 PM PDT 24
Peak memory 197868 kb
Host smart-969863f1-35a8-47eb-a6f7-6e030ad76307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870243505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.870243505
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2413301303
Short name T807
Test name
Test status
Simulation time 193790051 ps
CPU time 0.89 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:24 PM PDT 24
Peak memory 197604 kb
Host smart-3d33f9ca-f059-47f9-b43c-267ea15550d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413301303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2413301303
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.372965380
Short name T768
Test name
Test status
Simulation time 36953314 ps
CPU time 0.66 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 197432 kb
Host smart-51d5c297-567e-42fa-974d-245c461ae7b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372965380 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.372965380
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4290567389
Short name T800
Test name
Test status
Simulation time 13905211 ps
CPU time 0.62 seconds
Started Jun 06 12:42:24 PM PDT 24
Finished Jun 06 12:42:26 PM PDT 24
Peak memory 194840 kb
Host smart-dbc605f4-247f-40c1-aa63-d74a296c67bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290567389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4290567389
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3839574817
Short name T724
Test name
Test status
Simulation time 18731412 ps
CPU time 0.57 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:23 PM PDT 24
Peak memory 194140 kb
Host smart-2df334ff-a2c7-4512-86b4-2eee7dc34da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839574817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3839574817
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.588124443
Short name T791
Test name
Test status
Simulation time 22910907 ps
CPU time 0.68 seconds
Started Jun 06 12:42:22 PM PDT 24
Finished Jun 06 12:42:23 PM PDT 24
Peak memory 194904 kb
Host smart-6b33c329-41d4-4ffa-be5e-704b4a60c49b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588124443 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.588124443
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1420337605
Short name T801
Test name
Test status
Simulation time 470859485 ps
CPU time 2.36 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:26 PM PDT 24
Peak memory 197792 kb
Host smart-8ec9e7c4-8010-4056-89c0-d7c530bc8b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420337605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1420337605
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1974324979
Short name T109
Test name
Test status
Simulation time 49198600 ps
CPU time 0.83 seconds
Started Jun 06 12:42:24 PM PDT 24
Finished Jun 06 12:42:26 PM PDT 24
Peak memory 197748 kb
Host smart-c14f6ed4-740e-45e5-8927-b315260e85bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974324979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1974324979
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1700620752
Short name T721
Test name
Test status
Simulation time 35238218 ps
CPU time 0.96 seconds
Started Jun 06 12:42:50 PM PDT 24
Finished Jun 06 12:42:52 PM PDT 24
Peak memory 197864 kb
Host smart-ed55a989-04db-4f35-8fc5-20b27dfa7be4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700620752 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1700620752
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3330205447
Short name T78
Test name
Test status
Simulation time 97544366 ps
CPU time 0.58 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:24 PM PDT 24
Peak memory 193252 kb
Host smart-0ab0b70f-0063-4a95-882c-3b0d9642ff61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330205447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3330205447
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2507507435
Short name T777
Test name
Test status
Simulation time 12967410 ps
CPU time 0.59 seconds
Started Jun 06 12:42:30 PM PDT 24
Finished Jun 06 12:42:31 PM PDT 24
Peak memory 193404 kb
Host smart-9d29a54e-4ccd-4f7e-b72d-09acd95df85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507507435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2507507435
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.735283698
Short name T819
Test name
Test status
Simulation time 33449764 ps
CPU time 0.86 seconds
Started Jun 06 12:42:25 PM PDT 24
Finished Jun 06 12:42:27 PM PDT 24
Peak memory 196288 kb
Host smart-1f05b839-7a1d-4ca4-8c69-173b231e5521
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735283698 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.735283698
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1249921822
Short name T734
Test name
Test status
Simulation time 126220041 ps
CPU time 1.69 seconds
Started Jun 06 12:42:30 PM PDT 24
Finished Jun 06 12:42:32 PM PDT 24
Peak memory 197816 kb
Host smart-77bffd5b-8c1c-4d89-b7d1-c3122c43ef5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249921822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1249921822
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3829442576
Short name T37
Test name
Test status
Simulation time 68611930 ps
CPU time 1.14 seconds
Started Jun 06 12:42:24 PM PDT 24
Finished Jun 06 12:42:27 PM PDT 24
Peak memory 197820 kb
Host smart-567ac9c0-e027-45a5-b8de-fe2573526151
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829442576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3829442576
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.603727691
Short name T749
Test name
Test status
Simulation time 39217784 ps
CPU time 1.05 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 197924 kb
Host smart-ef43bfac-ca95-411c-8b9b-897fa8aa6270
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603727691 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.603727691
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2671728309
Short name T103
Test name
Test status
Simulation time 49839645 ps
CPU time 0.63 seconds
Started Jun 06 12:42:23 PM PDT 24
Finished Jun 06 12:42:25 PM PDT 24
Peak memory 195300 kb
Host smart-2f7bd820-87e3-497c-a7a8-a6be81b33a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671728309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2671728309
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2256691627
Short name T795
Test name
Test status
Simulation time 39261750 ps
CPU time 0.57 seconds
Started Jun 06 12:42:33 PM PDT 24
Finished Jun 06 12:42:34 PM PDT 24
Peak memory 194176 kb
Host smart-debc6f57-f763-4ad0-89af-e5f177fb1473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256691627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2256691627
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.783591743
Short name T823
Test name
Test status
Simulation time 90232075 ps
CPU time 0.83 seconds
Started Jun 06 12:42:30 PM PDT 24
Finished Jun 06 12:42:32 PM PDT 24
Peak memory 196460 kb
Host smart-196355aa-a666-4619-910c-90b953bbf717
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783591743 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.783591743
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3603105127
Short name T754
Test name
Test status
Simulation time 990239766 ps
CPU time 2.71 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 197980 kb
Host smart-5797d58a-06bb-47b6-836a-082ffae125d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603105127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3603105127
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.223766125
Short name T108
Test name
Test status
Simulation time 195171571 ps
CPU time 0.9 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 197784 kb
Host smart-b309707a-c7d8-40ba-9c50-a3662c619609
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223766125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.223766125
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.527294743
Short name T789
Test name
Test status
Simulation time 21959803 ps
CPU time 0.66 seconds
Started Jun 06 12:41:42 PM PDT 24
Finished Jun 06 12:41:44 PM PDT 24
Peak memory 194072 kb
Host smart-83838cc0-494d-4be0-ad99-ec64fcc93a0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527294743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.527294743
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.948322388
Short name T794
Test name
Test status
Simulation time 265406479 ps
CPU time 3.51 seconds
Started Jun 06 12:41:44 PM PDT 24
Finished Jun 06 12:41:49 PM PDT 24
Peak memory 197828 kb
Host smart-92d777b8-b911-4678-8893-1d1ae2b1e1c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948322388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.948322388
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.708366326
Short name T86
Test name
Test status
Simulation time 66838294 ps
CPU time 0.65 seconds
Started Jun 06 12:41:46 PM PDT 24
Finished Jun 06 12:41:47 PM PDT 24
Peak memory 194908 kb
Host smart-1ae8f322-d42c-4d5b-8372-9eea5f1bd192
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708366326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.708366326
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2273018476
Short name T799
Test name
Test status
Simulation time 107733998 ps
CPU time 0.88 seconds
Started Jun 06 12:41:45 PM PDT 24
Finished Jun 06 12:41:47 PM PDT 24
Peak memory 197788 kb
Host smart-8fa4f634-c729-47c9-850b-8e7676be9eed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273018476 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2273018476
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1566283716
Short name T85
Test name
Test status
Simulation time 11464296 ps
CPU time 0.61 seconds
Started Jun 06 12:41:44 PM PDT 24
Finished Jun 06 12:41:46 PM PDT 24
Peak memory 194632 kb
Host smart-b22bd325-84d8-4a4c-8cc1-674cf14cc6b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566283716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1566283716
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2535976887
Short name T770
Test name
Test status
Simulation time 15908786 ps
CPU time 0.61 seconds
Started Jun 06 12:41:44 PM PDT 24
Finished Jun 06 12:41:45 PM PDT 24
Peak memory 194288 kb
Host smart-60a4629c-6f37-4bd0-9031-a5e9b7cc4578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535976887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2535976887
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3903565637
Short name T89
Test name
Test status
Simulation time 97757821 ps
CPU time 0.74 seconds
Started Jun 06 12:41:47 PM PDT 24
Finished Jun 06 12:41:49 PM PDT 24
Peak memory 196116 kb
Host smart-438e1be7-1189-435d-99ab-142e8cac4c7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903565637 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3903565637
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.866099424
Short name T757
Test name
Test status
Simulation time 74899856 ps
CPU time 1.94 seconds
Started Jun 06 12:41:47 PM PDT 24
Finished Jun 06 12:41:50 PM PDT 24
Peak memory 197920 kb
Host smart-3dd14199-0617-45ec-a5ae-60282e47a021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866099424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.866099424
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1417649555
Short name T41
Test name
Test status
Simulation time 46756260 ps
CPU time 0.9 seconds
Started Jun 06 12:41:44 PM PDT 24
Finished Jun 06 12:41:45 PM PDT 24
Peak memory 197204 kb
Host smart-9de571d9-989d-44e8-960e-c15a62b51205
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417649555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1417649555
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2111645616
Short name T832
Test name
Test status
Simulation time 23478750 ps
CPU time 0.6 seconds
Started Jun 06 12:42:32 PM PDT 24
Finished Jun 06 12:42:33 PM PDT 24
Peak memory 193572 kb
Host smart-fb743e51-cd12-4a0a-ac71-0e090748aff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111645616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2111645616
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1191481535
Short name T723
Test name
Test status
Simulation time 134787720 ps
CPU time 0.61 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 193648 kb
Host smart-5aff109c-c0c9-4283-b192-979f08286137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191481535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1191481535
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4107778403
Short name T738
Test name
Test status
Simulation time 74385396 ps
CPU time 0.6 seconds
Started Jun 06 12:42:33 PM PDT 24
Finished Jun 06 12:42:34 PM PDT 24
Peak memory 193632 kb
Host smart-d6ae7be6-64b4-4693-bf45-a80294c50926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107778403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4107778403
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.336218076
Short name T782
Test name
Test status
Simulation time 100806310 ps
CPU time 0.58 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 193596 kb
Host smart-dee15ab4-f2a3-4c5a-933b-b0493daf4541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336218076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.336218076
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2060825439
Short name T760
Test name
Test status
Simulation time 57623526 ps
CPU time 0.64 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 194224 kb
Host smart-ef7928a4-8204-478e-828f-58a92ba38afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060825439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2060825439
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2848575121
Short name T729
Test name
Test status
Simulation time 42783186 ps
CPU time 0.59 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:35 PM PDT 24
Peak memory 193600 kb
Host smart-27220067-0ca1-4043-a891-2252cc313bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848575121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2848575121
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.806538126
Short name T725
Test name
Test status
Simulation time 14916944 ps
CPU time 0.61 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:35 PM PDT 24
Peak memory 193500 kb
Host smart-375bfb97-ae31-4418-87d2-5460f9e22d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806538126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.806538126
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2572072876
Short name T783
Test name
Test status
Simulation time 25468212 ps
CPU time 0.59 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 193536 kb
Host smart-6803dbd6-77e4-494d-899c-ca9095a1de0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572072876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2572072876
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4270711796
Short name T780
Test name
Test status
Simulation time 11653408 ps
CPU time 0.58 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 193524 kb
Host smart-6728b971-6246-412e-bcb3-52bc3aeeff54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270711796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4270711796
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.918202267
Short name T767
Test name
Test status
Simulation time 17691782 ps
CPU time 0.61 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 193636 kb
Host smart-4eb2d461-13d3-4855-82c8-d6a674ac613d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918202267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.918202267
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2049204344
Short name T811
Test name
Test status
Simulation time 63980193 ps
CPU time 0.78 seconds
Started Jun 06 12:41:47 PM PDT 24
Finished Jun 06 12:41:48 PM PDT 24
Peak memory 196124 kb
Host smart-12bc7047-61f7-45b1-9566-13aa88c74d86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049204344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2049204344
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1096052484
Short name T104
Test name
Test status
Simulation time 1278578719 ps
CPU time 3.45 seconds
Started Jun 06 12:41:46 PM PDT 24
Finished Jun 06 12:41:50 PM PDT 24
Peak memory 197828 kb
Host smart-561c27e4-eeb9-42a3-a83c-b03241953195
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096052484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1096052484
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3129780571
Short name T818
Test name
Test status
Simulation time 13924508 ps
CPU time 0.6 seconds
Started Jun 06 12:41:48 PM PDT 24
Finished Jun 06 12:41:49 PM PDT 24
Peak memory 194504 kb
Host smart-23238125-b275-462f-a0ef-47e90a693d29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129780571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3129780571
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.680887120
Short name T822
Test name
Test status
Simulation time 75286754 ps
CPU time 0.66 seconds
Started Jun 06 12:41:49 PM PDT 24
Finished Jun 06 12:41:50 PM PDT 24
Peak memory 197028 kb
Host smart-e6032b11-9511-4945-bb00-514cfb80d06a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680887120 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.680887120
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2610006655
Short name T836
Test name
Test status
Simulation time 12679863 ps
CPU time 0.58 seconds
Started Jun 06 12:41:43 PM PDT 24
Finished Jun 06 12:41:45 PM PDT 24
Peak memory 193140 kb
Host smart-826bf1fc-97fb-49ab-b034-15da0e6b108d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610006655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2610006655
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4135631584
Short name T806
Test name
Test status
Simulation time 41902974 ps
CPU time 0.65 seconds
Started Jun 06 12:41:43 PM PDT 24
Finished Jun 06 12:41:44 PM PDT 24
Peak memory 194244 kb
Host smart-8c0bdda1-4f25-4b50-8488-cacff5c2431c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135631584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4135631584
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.949196323
Short name T829
Test name
Test status
Simulation time 15244459 ps
CPU time 0.64 seconds
Started Jun 06 12:41:45 PM PDT 24
Finished Jun 06 12:41:47 PM PDT 24
Peak memory 194644 kb
Host smart-72e5bc26-21e1-4662-946e-168ee4216985
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949196323 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.949196323
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1164646573
Short name T815
Test name
Test status
Simulation time 66104995 ps
CPU time 1.56 seconds
Started Jun 06 12:41:46 PM PDT 24
Finished Jun 06 12:41:48 PM PDT 24
Peak memory 197956 kb
Host smart-c7962bcf-c7cc-4a09-859f-68d39ed6ad93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164646573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1164646573
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.691666933
Short name T834
Test name
Test status
Simulation time 91625008 ps
CPU time 0.86 seconds
Started Jun 06 12:41:44 PM PDT 24
Finished Jun 06 12:41:46 PM PDT 24
Peak memory 197724 kb
Host smart-f8ef3453-44be-4fa7-96aa-447b4a9a437c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691666933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.691666933
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1785470002
Short name T735
Test name
Test status
Simulation time 54728026 ps
CPU time 0.59 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:35 PM PDT 24
Peak memory 193564 kb
Host smart-d95917cc-0057-40d5-947b-23680217872c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785470002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1785470002
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3071302610
Short name T808
Test name
Test status
Simulation time 109260632 ps
CPU time 0.58 seconds
Started Jun 06 12:42:33 PM PDT 24
Finished Jun 06 12:42:35 PM PDT 24
Peak memory 193528 kb
Host smart-bba5714a-6b40-4d31-a2fc-8985273286e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071302610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3071302610
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3355584258
Short name T824
Test name
Test status
Simulation time 42149055 ps
CPU time 0.57 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 193592 kb
Host smart-7ad2fe14-501a-4465-8de4-47d49b763acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355584258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3355584258
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4047014011
Short name T741
Test name
Test status
Simulation time 13582701 ps
CPU time 0.57 seconds
Started Jun 06 12:42:30 PM PDT 24
Finished Jun 06 12:42:31 PM PDT 24
Peak memory 193456 kb
Host smart-e6fef597-604f-4515-9b38-13dab5f0f623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047014011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4047014011
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4150370749
Short name T786
Test name
Test status
Simulation time 82408306 ps
CPU time 0.63 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:35 PM PDT 24
Peak memory 193612 kb
Host smart-93001cc4-3fda-461b-9ed8-a9277bf62f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150370749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4150370749
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.804357219
Short name T841
Test name
Test status
Simulation time 27412678 ps
CPU time 0.6 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 194232 kb
Host smart-2a80e29d-00b7-4464-ad6a-66bf926d08ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804357219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.804357219
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2698870180
Short name T803
Test name
Test status
Simulation time 14716117 ps
CPU time 0.6 seconds
Started Jun 06 12:42:37 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 193560 kb
Host smart-e8906288-38ee-41d4-b067-8f34c93396f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698870180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2698870180
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2704685593
Short name T813
Test name
Test status
Simulation time 14523301 ps
CPU time 0.6 seconds
Started Jun 06 12:42:37 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 194200 kb
Host smart-b123c3c0-ff85-4f2d-a79a-4550fcce5ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704685593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2704685593
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1884467437
Short name T745
Test name
Test status
Simulation time 43960208 ps
CPU time 0.61 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 193556 kb
Host smart-9c15261a-5cfe-4b23-96f0-853122a09661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884467437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1884467437
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1494661208
Short name T787
Test name
Test status
Simulation time 16025218 ps
CPU time 0.61 seconds
Started Jun 06 12:42:33 PM PDT 24
Finished Jun 06 12:42:35 PM PDT 24
Peak memory 193556 kb
Host smart-0ef8dabc-88e5-420e-8abf-e2801ff18431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494661208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1494661208
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1573002735
Short name T83
Test name
Test status
Simulation time 13049766 ps
CPU time 0.65 seconds
Started Jun 06 12:41:42 PM PDT 24
Finished Jun 06 12:41:43 PM PDT 24
Peak memory 194564 kb
Host smart-dfa53cda-4339-4f3b-9485-ff1bdc05872a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573002735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1573002735
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3475500585
Short name T72
Test name
Test status
Simulation time 509756764 ps
CPU time 2.51 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:57 PM PDT 24
Peak memory 196816 kb
Host smart-68e192d8-df72-41e5-826a-eebd08488296
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475500585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3475500585
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2131955338
Short name T69
Test name
Test status
Simulation time 52988810 ps
CPU time 0.66 seconds
Started Jun 06 12:41:45 PM PDT 24
Finished Jun 06 12:41:47 PM PDT 24
Peak memory 194708 kb
Host smart-f93bc72b-ba10-4b3a-83b2-1cb6aba4e0a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131955338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2131955338
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.930286878
Short name T776
Test name
Test status
Simulation time 18707570 ps
CPU time 0.71 seconds
Started Jun 06 12:41:48 PM PDT 24
Finished Jun 06 12:41:50 PM PDT 24
Peak memory 197512 kb
Host smart-20d32371-7758-4cc0-9814-75bd8ab84420
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930286878 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.930286878
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3332676264
Short name T838
Test name
Test status
Simulation time 37132190 ps
CPU time 0.55 seconds
Started Jun 06 12:41:40 PM PDT 24
Finished Jun 06 12:41:41 PM PDT 24
Peak memory 193036 kb
Host smart-37a1cad9-ea8c-4633-aa83-9bad0dfce3f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332676264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3332676264
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1306250193
Short name T756
Test name
Test status
Simulation time 29673579 ps
CPU time 0.6 seconds
Started Jun 06 12:41:42 PM PDT 24
Finished Jun 06 12:41:43 PM PDT 24
Peak memory 194136 kb
Host smart-86c476f4-f399-4ab7-9676-c29e94d122c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306250193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1306250193
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.222367241
Short name T70
Test name
Test status
Simulation time 79174285 ps
CPU time 0.86 seconds
Started Jun 06 12:41:42 PM PDT 24
Finished Jun 06 12:41:44 PM PDT 24
Peak memory 196836 kb
Host smart-f1e8f343-eef5-4c27-865b-8f1172dbd879
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222367241 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.222367241
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1838639870
Short name T778
Test name
Test status
Simulation time 376757803 ps
CPU time 1.91 seconds
Started Jun 06 12:41:45 PM PDT 24
Finished Jun 06 12:41:48 PM PDT 24
Peak memory 197924 kb
Host smart-fce1746e-4830-40fe-98d4-74427e1d4034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838639870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1838639870
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3353407600
Short name T797
Test name
Test status
Simulation time 791663888 ps
CPU time 1.17 seconds
Started Jun 06 12:41:42 PM PDT 24
Finished Jun 06 12:41:44 PM PDT 24
Peak memory 197936 kb
Host smart-43a9cb52-7d7b-4352-8df3-92fa6a11664f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353407600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3353407600
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2380525684
Short name T831
Test name
Test status
Simulation time 14412371 ps
CPU time 0.59 seconds
Started Jun 06 12:42:42 PM PDT 24
Finished Jun 06 12:42:43 PM PDT 24
Peak memory 193500 kb
Host smart-5a3e51d1-a37f-4e45-80cd-4553fddc1db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380525684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2380525684
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1000211653
Short name T742
Test name
Test status
Simulation time 12228849 ps
CPU time 0.59 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 193560 kb
Host smart-b5eb5d43-f48c-41d0-9e5d-262e2a84c156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000211653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1000211653
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2562521372
Short name T828
Test name
Test status
Simulation time 49935192 ps
CPU time 0.58 seconds
Started Jun 06 12:42:37 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 194240 kb
Host smart-fd554ea7-3708-4551-94ca-5547462c57d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562521372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2562521372
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1134369037
Short name T736
Test name
Test status
Simulation time 42470939 ps
CPU time 0.59 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 193580 kb
Host smart-6db924ba-0f02-4de3-b9cd-faa3f808d51e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134369037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1134369037
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.371052054
Short name T761
Test name
Test status
Simulation time 24597363 ps
CPU time 0.6 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:37 PM PDT 24
Peak memory 193624 kb
Host smart-85d2176e-2b0f-4704-9509-7415bc8a8b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371052054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.371052054
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3163506438
Short name T820
Test name
Test status
Simulation time 19216051 ps
CPU time 0.59 seconds
Started Jun 06 12:42:34 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 194224 kb
Host smart-ca1fb9db-90ae-4319-b202-6e5289b8e90b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163506438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3163506438
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3470154069
Short name T747
Test name
Test status
Simulation time 18214998 ps
CPU time 0.6 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 193584 kb
Host smart-0bf90a2e-80da-48d1-95ed-64930b07043c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470154069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3470154069
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1841571497
Short name T743
Test name
Test status
Simulation time 11887211 ps
CPU time 0.67 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 194348 kb
Host smart-acd7f5a6-0117-46ff-a465-fd6b13e9e69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841571497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1841571497
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1064874388
Short name T746
Test name
Test status
Simulation time 40672688 ps
CPU time 0.58 seconds
Started Jun 06 12:42:38 PM PDT 24
Finished Jun 06 12:42:39 PM PDT 24
Peak memory 194236 kb
Host smart-e346e03d-94c0-4b44-939f-50518db8defa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064874388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1064874388
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2696396889
Short name T730
Test name
Test status
Simulation time 20209320 ps
CPU time 0.59 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:36 PM PDT 24
Peak memory 193564 kb
Host smart-9e6002cc-b48e-4176-a08a-da9743ead621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696396889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2696396889
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.192257169
Short name T772
Test name
Test status
Simulation time 31297420 ps
CPU time 0.65 seconds
Started Jun 06 12:41:52 PM PDT 24
Finished Jun 06 12:41:54 PM PDT 24
Peak memory 196964 kb
Host smart-71402cab-bd26-4f78-9262-e072ca69dddb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192257169 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.192257169
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3024423787
Short name T810
Test name
Test status
Simulation time 120337402 ps
CPU time 0.61 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 194576 kb
Host smart-1e0e8901-1af0-4295-ad06-53afee60d0b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024423787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3024423787
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.47998558
Short name T732
Test name
Test status
Simulation time 14153164 ps
CPU time 0.66 seconds
Started Jun 06 12:41:54 PM PDT 24
Finished Jun 06 12:41:56 PM PDT 24
Peak memory 193636 kb
Host smart-7a80a1e0-8098-4a10-92ba-601b53b4370b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47998558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.47998558
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1272774057
Short name T796
Test name
Test status
Simulation time 72611375 ps
CPU time 0.73 seconds
Started Jun 06 12:41:54 PM PDT 24
Finished Jun 06 12:41:56 PM PDT 24
Peak memory 195500 kb
Host smart-9603faa4-c37a-4ac3-a7b9-d8ab5c3c5d37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272774057 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1272774057
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2420001770
Short name T781
Test name
Test status
Simulation time 49364934 ps
CPU time 1.26 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 197964 kb
Host smart-aa9cec60-ccb8-4fe0-b30a-899d001b9bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420001770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2420001770
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3155162296
Short name T29
Test name
Test status
Simulation time 68421399 ps
CPU time 1.17 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 197932 kb
Host smart-f4186dee-ffca-428e-a623-e231f7fe63e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155162296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3155162296
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1374511271
Short name T793
Test name
Test status
Simulation time 119092438 ps
CPU time 1 seconds
Started Jun 06 12:41:51 PM PDT 24
Finished Jun 06 12:41:53 PM PDT 24
Peak memory 197768 kb
Host smart-0971b8ce-6619-4908-af95-55eeaa76486f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374511271 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1374511271
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3628200886
Short name T76
Test name
Test status
Simulation time 13380176 ps
CPU time 0.58 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 194252 kb
Host smart-8133d7df-be37-4420-98f7-73d6363b13eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628200886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3628200886
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.890271407
Short name T812
Test name
Test status
Simulation time 28867886 ps
CPU time 0.6 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 193556 kb
Host smart-92cbda03-bc72-412a-b7be-ed64378de861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890271407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.890271407
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3112454797
Short name T792
Test name
Test status
Simulation time 34258458 ps
CPU time 0.72 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 195956 kb
Host smart-d07276c2-1395-45bb-aa49-b24d673729b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112454797 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3112454797
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4182515619
Short name T837
Test name
Test status
Simulation time 54830076 ps
CPU time 2.64 seconds
Started Jun 06 12:41:54 PM PDT 24
Finished Jun 06 12:41:58 PM PDT 24
Peak memory 197876 kb
Host smart-640ac2e3-6b1e-47ec-9a47-a992bb445e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182515619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4182515619
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2128488267
Short name T775
Test name
Test status
Simulation time 82925770 ps
CPU time 1.21 seconds
Started Jun 06 12:41:53 PM PDT 24
Finished Jun 06 12:41:55 PM PDT 24
Peak memory 197952 kb
Host smart-5a994923-3fe0-430e-bc6b-47747d6561b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128488267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2128488267
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2184881881
Short name T764
Test name
Test status
Simulation time 31841262 ps
CPU time 1.02 seconds
Started Jun 06 12:42:03 PM PDT 24
Finished Jun 06 12:42:04 PM PDT 24
Peak memory 197768 kb
Host smart-de9d8ddb-22db-4a84-bf22-0271a2f68913
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184881881 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2184881881
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3505903689
Short name T107
Test name
Test status
Simulation time 26486582 ps
CPU time 0.6 seconds
Started Jun 06 12:41:52 PM PDT 24
Finished Jun 06 12:41:54 PM PDT 24
Peak memory 194608 kb
Host smart-aaf6d321-d055-492e-807b-5720133ec023
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505903689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3505903689
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.495252379
Short name T753
Test name
Test status
Simulation time 17270039 ps
CPU time 0.61 seconds
Started Jun 06 12:42:02 PM PDT 24
Finished Jun 06 12:42:03 PM PDT 24
Peak memory 194292 kb
Host smart-9c31a7e9-3185-4098-941e-9be820742691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495252379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.495252379
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1515130664
Short name T74
Test name
Test status
Simulation time 116405401 ps
CPU time 0.75 seconds
Started Jun 06 12:41:56 PM PDT 24
Finished Jun 06 12:41:57 PM PDT 24
Peak memory 196012 kb
Host smart-52b3cd2c-56d4-477b-aa0c-ff356193988d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515130664 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1515130664
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.923975178
Short name T804
Test name
Test status
Simulation time 30507932 ps
CPU time 1.54 seconds
Started Jun 06 12:42:06 PM PDT 24
Finished Jun 06 12:42:08 PM PDT 24
Peak memory 197964 kb
Host smart-6a4d14a3-fe3a-47a9-a189-e61c5679020a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923975178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.923975178
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1126407367
Short name T785
Test name
Test status
Simulation time 69655441 ps
CPU time 1.16 seconds
Started Jun 06 12:42:06 PM PDT 24
Finished Jun 06 12:42:08 PM PDT 24
Peak memory 197952 kb
Host smart-52d4a082-65bb-45c6-a46c-631083d5ec35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126407367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1126407367
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.952488083
Short name T726
Test name
Test status
Simulation time 144076549 ps
CPU time 0.96 seconds
Started Jun 06 12:42:05 PM PDT 24
Finished Jun 06 12:42:07 PM PDT 24
Peak memory 197840 kb
Host smart-d62b2329-161a-4499-8db1-dce9e8e0e6b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952488083 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.952488083
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2535442293
Short name T816
Test name
Test status
Simulation time 15740615 ps
CPU time 0.64 seconds
Started Jun 06 12:42:06 PM PDT 24
Finished Jun 06 12:42:08 PM PDT 24
Peak memory 193804 kb
Host smart-48afcf65-a63a-401a-9756-88d6240edb92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535442293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2535442293
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3513345967
Short name T766
Test name
Test status
Simulation time 18522517 ps
CPU time 0.57 seconds
Started Jun 06 12:42:03 PM PDT 24
Finished Jun 06 12:42:04 PM PDT 24
Peak memory 193568 kb
Host smart-aaefd40f-86d0-4cb1-b18c-e79379455a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513345967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3513345967
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1655501222
Short name T73
Test name
Test status
Simulation time 21670270 ps
CPU time 0.68 seconds
Started Jun 06 12:42:04 PM PDT 24
Finished Jun 06 12:42:05 PM PDT 24
Peak memory 194812 kb
Host smart-bb3143aa-332e-4fd6-b197-d54ade747cd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655501222 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1655501222
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4097300500
Short name T790
Test name
Test status
Simulation time 463663286 ps
CPU time 2.99 seconds
Started Jun 06 12:42:09 PM PDT 24
Finished Jun 06 12:42:13 PM PDT 24
Peak memory 197892 kb
Host smart-36820a77-1bd5-48f9-8ed5-89e79580dfe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097300500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4097300500
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2616942955
Short name T40
Test name
Test status
Simulation time 475618753 ps
CPU time 1.5 seconds
Started Jun 06 12:42:08 PM PDT 24
Finished Jun 06 12:42:10 PM PDT 24
Peak memory 197928 kb
Host smart-bc57a4bd-5a01-450f-9bfa-d85c070f3b31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616942955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2616942955
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3224771393
Short name T771
Test name
Test status
Simulation time 35271056 ps
CPU time 0.77 seconds
Started Jun 06 12:42:04 PM PDT 24
Finished Jun 06 12:42:06 PM PDT 24
Peak memory 197776 kb
Host smart-0144c41a-c16a-4fd1-bd9e-39ccd62bf295
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224771393 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3224771393
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.391911061
Short name T87
Test name
Test status
Simulation time 122555734 ps
CPU time 0.55 seconds
Started Jun 06 12:42:08 PM PDT 24
Finished Jun 06 12:42:10 PM PDT 24
Peak memory 193124 kb
Host smart-a8e17178-d162-44da-bb62-139d89ee0a27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391911061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.391911061
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.83745251
Short name T728
Test name
Test status
Simulation time 81734043 ps
CPU time 0.63 seconds
Started Jun 06 12:42:05 PM PDT 24
Finished Jun 06 12:42:07 PM PDT 24
Peak memory 193560 kb
Host smart-09da33d6-81ce-4dd9-b8f8-1618456ee55e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83745251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.83745251
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3432134478
Short name T788
Test name
Test status
Simulation time 19163175 ps
CPU time 0.82 seconds
Started Jun 06 12:42:04 PM PDT 24
Finished Jun 06 12:42:06 PM PDT 24
Peak memory 196960 kb
Host smart-c6e3d7a1-c81e-4c4e-9696-63e212e455b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432134478 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3432134478
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1700309636
Short name T765
Test name
Test status
Simulation time 33927498 ps
CPU time 1.57 seconds
Started Jun 06 12:42:04 PM PDT 24
Finished Jun 06 12:42:06 PM PDT 24
Peak memory 197928 kb
Host smart-6c6ab8d5-c962-452a-9ffd-5383de76800c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700309636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1700309636
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3334244922
Short name T111
Test name
Test status
Simulation time 383428466 ps
CPU time 1.5 seconds
Started Jun 06 12:42:03 PM PDT 24
Finished Jun 06 12:42:05 PM PDT 24
Peak memory 197708 kb
Host smart-63334521-ae3d-4455-ab72-308163ff24b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334244922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3334244922
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1253906092
Short name T402
Test name
Test status
Simulation time 15109168 ps
CPU time 0.57 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:15 PM PDT 24
Peak memory 194024 kb
Host smart-1089cfd6-4be9-4620-9352-f4aff309b032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253906092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1253906092
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2669631243
Short name T387
Test name
Test status
Simulation time 43463304 ps
CPU time 0.77 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:14 PM PDT 24
Peak memory 195148 kb
Host smart-bf6d9e5e-1f5d-4f66-91b7-94182b4d03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669631243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2669631243
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1344886839
Short name T518
Test name
Test status
Simulation time 946007442 ps
CPU time 15.74 seconds
Started Jun 06 12:43:12 PM PDT 24
Finished Jun 06 12:43:29 PM PDT 24
Peak memory 196524 kb
Host smart-ef4ec3f8-1478-4af0-bab4-6d824bf678f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344886839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1344886839
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.218851064
Short name T256
Test name
Test status
Simulation time 152126934 ps
CPU time 0.9 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 195940 kb
Host smart-f62249d2-a43c-436c-84f9-5e401096c089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218851064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.218851064
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1958310427
Short name T411
Test name
Test status
Simulation time 1491214299 ps
CPU time 1.17 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 195828 kb
Host smart-d5e1add4-c639-463e-8d0f-bbd44ecd409b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958310427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1958310427
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1058246132
Short name T112
Test name
Test status
Simulation time 72753235 ps
CPU time 2.7 seconds
Started Jun 06 12:43:16 PM PDT 24
Finished Jun 06 12:43:20 PM PDT 24
Peak memory 198052 kb
Host smart-8805cb3f-edec-4105-ab3f-ea7d6a0a7f0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058246132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1058246132
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1396272322
Short name T198
Test name
Test status
Simulation time 66420611 ps
CPU time 1.48 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:18 PM PDT 24
Peak memory 196012 kb
Host smart-6aca689c-e4c1-4a6d-b389-c4a337199e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396272322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1396272322
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4006517453
Short name T650
Test name
Test status
Simulation time 128068853 ps
CPU time 0.9 seconds
Started Jun 06 12:43:02 PM PDT 24
Finished Jun 06 12:43:03 PM PDT 24
Peak memory 196500 kb
Host smart-99b15cb2-ea41-49a2-a2a7-5b6b9e5548cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006517453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4006517453
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.582783199
Short name T239
Test name
Test status
Simulation time 47844557 ps
CPU time 1.19 seconds
Started Jun 06 12:43:01 PM PDT 24
Finished Jun 06 12:43:03 PM PDT 24
Peak memory 195680 kb
Host smart-9020bf56-1e47-4f70-8bc2-f73828510d4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582783199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.582783199
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3275559587
Short name T448
Test name
Test status
Simulation time 106625238 ps
CPU time 2.12 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:17 PM PDT 24
Peak memory 197912 kb
Host smart-4af5d3e7-fb25-4fe7-9920-09fabbb3306b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275559587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3275559587
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3589532216
Short name T432
Test name
Test status
Simulation time 109907426 ps
CPU time 1.57 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:07 PM PDT 24
Peak memory 196216 kb
Host smart-260ac840-4fde-4c76-adec-39b25ca57db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589532216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3589532216
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2606120365
Short name T618
Test name
Test status
Simulation time 225594628 ps
CPU time 1.13 seconds
Started Jun 06 12:43:06 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 195648 kb
Host smart-0aad91ef-6a9e-4101-b2a0-20e236897013
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606120365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2606120365
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3592203367
Short name T546
Test name
Test status
Simulation time 23201283239 ps
CPU time 112.77 seconds
Started Jun 06 12:43:12 PM PDT 24
Finished Jun 06 12:45:05 PM PDT 24
Peak memory 198156 kb
Host smart-f992ec97-67e1-429c-85c7-1b952b91fe80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592203367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3592203367
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1883785245
Short name T265
Test name
Test status
Simulation time 44538960 ps
CPU time 0.6 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:14 PM PDT 24
Peak memory 193912 kb
Host smart-0e41d61b-1ebc-427f-aabf-1584a7366415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883785245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1883785245
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2096946497
Short name T215
Test name
Test status
Simulation time 86209462 ps
CPU time 0.99 seconds
Started Jun 06 12:43:11 PM PDT 24
Finished Jun 06 12:43:13 PM PDT 24
Peak memory 196664 kb
Host smart-f0d52e62-ccf4-4099-b5eb-830b06ae4894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096946497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2096946497
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3163949088
Short name T455
Test name
Test status
Simulation time 1367072542 ps
CPU time 19.19 seconds
Started Jun 06 12:43:20 PM PDT 24
Finished Jun 06 12:43:40 PM PDT 24
Peak memory 196488 kb
Host smart-ea119df4-34a5-4851-bb40-3fefb1d2a5a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163949088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3163949088
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2786159596
Short name T67
Test name
Test status
Simulation time 135033992 ps
CPU time 0.79 seconds
Started Jun 06 12:43:16 PM PDT 24
Finished Jun 06 12:43:18 PM PDT 24
Peak memory 196448 kb
Host smart-637244d6-362f-4910-8e35-7df051993f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786159596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2786159596
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.543623994
Short name T122
Test name
Test status
Simulation time 54281473 ps
CPU time 0.97 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:17 PM PDT 24
Peak memory 196660 kb
Host smart-d4829939-317b-401c-936d-0939895d0a2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543623994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.543623994
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1519673475
Short name T164
Test name
Test status
Simulation time 70196882 ps
CPU time 0.88 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 196032 kb
Host smart-c069da70-22c4-4518-818a-37d27372c364
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519673475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1519673475
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2873829708
Short name T656
Test name
Test status
Simulation time 99543411 ps
CPU time 2.28 seconds
Started Jun 06 12:43:12 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 196928 kb
Host smart-d63760a6-f895-4f0a-bc72-cdc28e81951a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873829708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2873829708
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1366242332
Short name T584
Test name
Test status
Simulation time 35462301 ps
CPU time 0.69 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:17 PM PDT 24
Peak memory 194888 kb
Host smart-2dd97a4c-286c-4e4f-a457-46ba9aa9014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366242332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1366242332
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1950237648
Short name T252
Test name
Test status
Simulation time 23982274 ps
CPU time 0.86 seconds
Started Jun 06 12:43:12 PM PDT 24
Finished Jun 06 12:43:14 PM PDT 24
Peak memory 195956 kb
Host smart-8967d8a7-d070-4b02-a830-1fdc5a31869e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950237648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1950237648
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2787127631
Short name T701
Test name
Test status
Simulation time 495690349 ps
CPU time 1.86 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:18 PM PDT 24
Peak memory 197932 kb
Host smart-df70ab6d-8253-47bc-a3f1-b9cc4cdb38bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787127631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2787127631
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2301126383
Short name T32
Test name
Test status
Simulation time 340628865 ps
CPU time 0.93 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:15 PM PDT 24
Peak memory 214968 kb
Host smart-08f24af9-b1b8-44e1-af17-345355f722a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301126383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2301126383
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.726493143
Short name T147
Test name
Test status
Simulation time 94008472 ps
CPU time 1.35 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:18 PM PDT 24
Peak memory 196724 kb
Host smart-44cbf153-e69f-429a-b921-2d69ed73a3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726493143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.726493143
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.387128227
Short name T95
Test name
Test status
Simulation time 47578018 ps
CPU time 1.28 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 195940 kb
Host smart-77cb90d6-60e0-445b-afbd-03b53c47b31f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387128227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.387128227
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.548697385
Short name T380
Test name
Test status
Simulation time 6990678470 ps
CPU time 199.1 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:46:34 PM PDT 24
Peak memory 198144 kb
Host smart-80780b1a-159d-47f1-9918-a5ace1ef3cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548697385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.548697385
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.868751710
Short name T636
Test name
Test status
Simulation time 76547430693 ps
CPU time 474.3 seconds
Started Jun 06 12:43:12 PM PDT 24
Finished Jun 06 12:51:07 PM PDT 24
Peak memory 198216 kb
Host smart-489b2108-b7b2-44e8-baae-73ad9f19cefb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=868751710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.868751710
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2181590455
Short name T634
Test name
Test status
Simulation time 81560901 ps
CPU time 0.74 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 195260 kb
Host smart-57b402f1-c257-4fec-a225-ee1562723c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181590455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2181590455
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2879459767
Short name T686
Test name
Test status
Simulation time 936809934 ps
CPU time 25.06 seconds
Started Jun 06 12:43:46 PM PDT 24
Finished Jun 06 12:44:12 PM PDT 24
Peak memory 196936 kb
Host smart-f60eb892-fd65-480b-a4ae-b2b115ad1bbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879459767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2879459767
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1625001114
Short name T301
Test name
Test status
Simulation time 31930441 ps
CPU time 0.7 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:49 PM PDT 24
Peak memory 195556 kb
Host smart-ba81fe1c-bb8d-4063-9334-33a38e117b70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625001114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1625001114
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.888383187
Short name T543
Test name
Test status
Simulation time 155289019 ps
CPU time 0.92 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:49 PM PDT 24
Peak memory 196496 kb
Host smart-4a4a5da9-8457-4e28-b6e4-5661f701e0cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888383187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.888383187
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3889920840
Short name T538
Test name
Test status
Simulation time 207570791 ps
CPU time 2.29 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 197956 kb
Host smart-db102759-e6d2-4a6c-b49e-5bd5a37a2ef6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889920840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3889920840
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2623767554
Short name T659
Test name
Test status
Simulation time 530058245 ps
CPU time 2.99 seconds
Started Jun 06 12:43:50 PM PDT 24
Finished Jun 06 12:43:53 PM PDT 24
Peak memory 197012 kb
Host smart-b59336e5-e323-4492-b5ed-f46617d983dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623767554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2623767554
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2417648723
Short name T613
Test name
Test status
Simulation time 206135501 ps
CPU time 1.27 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:49 PM PDT 24
Peak memory 195864 kb
Host smart-50a80dc6-3c9c-4a40-8582-a6be6726c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417648723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2417648723
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1512153840
Short name T528
Test name
Test status
Simulation time 55228972 ps
CPU time 1.21 seconds
Started Jun 06 12:43:46 PM PDT 24
Finished Jun 06 12:43:48 PM PDT 24
Peak memory 198020 kb
Host smart-695f5ec2-79aa-43b1-8430-77245509f053
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512153840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1512153840
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3221706363
Short name T560
Test name
Test status
Simulation time 377277928 ps
CPU time 1.79 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:51 PM PDT 24
Peak memory 197888 kb
Host smart-3cd619b3-3741-4d06-8bf1-d869cd338c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221706363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3221706363
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1567027785
Short name T366
Test name
Test status
Simulation time 86886800 ps
CPU time 1.12 seconds
Started Jun 06 12:43:51 PM PDT 24
Finished Jun 06 12:43:53 PM PDT 24
Peak memory 195728 kb
Host smart-718fb05e-7d57-4741-ba82-d80b53a9d509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567027785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1567027785
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.668795815
Short name T148
Test name
Test status
Simulation time 491290319 ps
CPU time 1.13 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:49 PM PDT 24
Peak memory 195728 kb
Host smart-698e82b5-5c5e-4c9e-8c3e-9b86de7f1330
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668795815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.668795815
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3879351867
Short name T191
Test name
Test status
Simulation time 23669284072 ps
CPU time 148.12 seconds
Started Jun 06 12:43:50 PM PDT 24
Finished Jun 06 12:46:19 PM PDT 24
Peak memory 198104 kb
Host smart-20cf569c-37b6-4979-8f7f-52f208002334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879351867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3879351867
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4122516454
Short name T35
Test name
Test status
Simulation time 12861075 ps
CPU time 0.59 seconds
Started Jun 06 12:43:56 PM PDT 24
Finished Jun 06 12:43:57 PM PDT 24
Peak memory 194160 kb
Host smart-3a125cec-0b78-4e30-9484-eee685e5989c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122516454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4122516454
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2715800995
Short name T679
Test name
Test status
Simulation time 81662289 ps
CPU time 0.82 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 195364 kb
Host smart-ee4869f7-5e8c-40eb-a700-e617e250b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715800995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2715800995
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3030870632
Short name T196
Test name
Test status
Simulation time 297367822 ps
CPU time 14.66 seconds
Started Jun 06 12:44:03 PM PDT 24
Finished Jun 06 12:44:20 PM PDT 24
Peak memory 196836 kb
Host smart-e87def1b-8456-4ff4-86c1-6dc74aa60ecb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030870632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3030870632
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.302824574
Short name T434
Test name
Test status
Simulation time 92661472 ps
CPU time 1.1 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 196432 kb
Host smart-87e8d3ab-2d05-4e8e-af47-188955f0871e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302824574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.302824574
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2800224452
Short name T192
Test name
Test status
Simulation time 68851035 ps
CPU time 0.76 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 195436 kb
Host smart-372ea8ef-ad55-49d7-9f2a-2c160cd62718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800224452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2800224452
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1082305752
Short name T400
Test name
Test status
Simulation time 157887601 ps
CPU time 1.93 seconds
Started Jun 06 12:43:58 PM PDT 24
Finished Jun 06 12:44:01 PM PDT 24
Peak memory 198044 kb
Host smart-7989ea21-68bc-4dbe-95f8-0346c39d325b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082305752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1082305752
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2871221631
Short name T319
Test name
Test status
Simulation time 404157170 ps
CPU time 3.14 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 195832 kb
Host smart-2b93af32-114e-48f8-aa2b-cf18da8f351d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871221631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2871221631
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4092182690
Short name T376
Test name
Test status
Simulation time 83645265 ps
CPU time 0.91 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 195820 kb
Host smart-ece5c1fa-6dc2-46e8-8466-804dda2978de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092182690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4092182690
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2431012097
Short name T399
Test name
Test status
Simulation time 95767406 ps
CPU time 1.09 seconds
Started Jun 06 12:43:46 PM PDT 24
Finished Jun 06 12:43:48 PM PDT 24
Peak memory 195780 kb
Host smart-843ca252-6eb4-45f4-bc4d-4cbec5a4ccd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431012097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2431012097
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3711606068
Short name T558
Test name
Test status
Simulation time 734642607 ps
CPU time 6.04 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 197940 kb
Host smart-13496ebd-a71c-439b-992f-59a49d673482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711606068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3711606068
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3812598117
Short name T443
Test name
Test status
Simulation time 123469778 ps
CPU time 1.1 seconds
Started Jun 06 12:43:50 PM PDT 24
Finished Jun 06 12:43:51 PM PDT 24
Peak memory 196444 kb
Host smart-ed89c3db-31fe-459d-ba62-03d3340979f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812598117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3812598117
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.636305943
Short name T136
Test name
Test status
Simulation time 80163137 ps
CPU time 1.26 seconds
Started Jun 06 12:43:46 PM PDT 24
Finished Jun 06 12:43:48 PM PDT 24
Peak memory 195796 kb
Host smart-98a15f94-6570-48ce-a468-981156f06216
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636305943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.636305943
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1951653692
Short name T102
Test name
Test status
Simulation time 19820492246 ps
CPU time 66.11 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:45:09 PM PDT 24
Peak memory 198204 kb
Host smart-6b00a4de-90a1-4617-aaf6-8f90ae9fa176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951653692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1951653692
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3363360385
Short name T699
Test name
Test status
Simulation time 43341887 ps
CPU time 0.6 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 194528 kb
Host smart-c8548e5e-9496-40b8-9eba-54ffe2e630b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363360385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3363360385
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3340140450
Short name T614
Test name
Test status
Simulation time 15484878 ps
CPU time 0.63 seconds
Started Jun 06 12:44:03 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 194760 kb
Host smart-e12012a9-6a3a-429d-beea-0b84b026eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340140450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3340140450
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2304771502
Short name T62
Test name
Test status
Simulation time 2237442964 ps
CPU time 25.45 seconds
Started Jun 06 12:43:57 PM PDT 24
Finished Jun 06 12:44:24 PM PDT 24
Peak memory 196808 kb
Host smart-49a1649f-d927-484b-aef6-c2d19e98f964
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304771502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2304771502
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4096157059
Short name T416
Test name
Test status
Simulation time 111744378 ps
CPU time 0.7 seconds
Started Jun 06 12:44:03 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 194800 kb
Host smart-51b39790-1e78-4b5d-aeef-ff6baf044f2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096157059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4096157059
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1654635310
Short name T595
Test name
Test status
Simulation time 67675565 ps
CPU time 1.07 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:01 PM PDT 24
Peak memory 196712 kb
Host smart-7cd4158e-4218-414e-84fa-bfd0e41d2ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654635310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1654635310
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3406560209
Short name T345
Test name
Test status
Simulation time 330915363 ps
CPU time 3.37 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 198028 kb
Host smart-8c034982-2cd4-44ac-877d-cca6f80d4cdb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406560209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3406560209
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2501030849
Short name T549
Test name
Test status
Simulation time 26594256 ps
CPU time 0.94 seconds
Started Jun 06 12:43:58 PM PDT 24
Finished Jun 06 12:44:00 PM PDT 24
Peak memory 195608 kb
Host smart-d6ff7a31-7ae7-499b-a0f2-8dc93cd0d499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501030849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2501030849
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3815466421
Short name T13
Test name
Test status
Simulation time 48253920 ps
CPU time 1.03 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 195920 kb
Host smart-e158f4b3-3b8a-4f4d-b19e-cc6c45915e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815466421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3815466421
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3593824607
Short name T520
Test name
Test status
Simulation time 35220872 ps
CPU time 0.88 seconds
Started Jun 06 12:43:58 PM PDT 24
Finished Jun 06 12:44:00 PM PDT 24
Peak memory 196008 kb
Host smart-0b984bd5-1dfa-4073-9deb-e2858dfba16a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593824607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3593824607
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2912757372
Short name T652
Test name
Test status
Simulation time 123116776 ps
CPU time 3.2 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 197900 kb
Host smart-c496f56a-58d2-4f2c-8661-cde4c57f28f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912757372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2912757372
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.373621546
Short name T241
Test name
Test status
Simulation time 133568640 ps
CPU time 0.79 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 195136 kb
Host smart-55a55cb4-7a6a-41df-8412-22b583c3f00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373621546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.373621546
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2931839313
Short name T51
Test name
Test status
Simulation time 83889809 ps
CPU time 1.26 seconds
Started Jun 06 12:44:56 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 194960 kb
Host smart-1805191a-0ce0-4b4f-8bd1-688680c25cf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931839313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2931839313
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4218548485
Short name T133
Test name
Test status
Simulation time 145334668402 ps
CPU time 128.27 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:46:09 PM PDT 24
Peak memory 198120 kb
Host smart-cc638d34-970c-4434-a7e7-b179fcc9a9e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218548485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4218548485
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1465157218
Short name T642
Test name
Test status
Simulation time 196906309639 ps
CPU time 2539.17 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 01:26:23 PM PDT 24
Peak memory 198208 kb
Host smart-2fe3b812-1289-4b4a-93e3-907170258d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1465157218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1465157218
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3974427984
Short name T231
Test name
Test status
Simulation time 42435617 ps
CPU time 0.58 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:00 PM PDT 24
Peak memory 194768 kb
Host smart-2c94ffc4-0794-4c1a-bdb1-99ca21287792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974427984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3974427984
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3280184168
Short name T677
Test name
Test status
Simulation time 37989015 ps
CPU time 0.89 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 196516 kb
Host smart-8e7f7d67-aa51-484a-b069-1c7968d43130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280184168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3280184168
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3437330
Short name T221
Test name
Test status
Simulation time 875444879 ps
CPU time 23.25 seconds
Started Jun 06 12:44:03 PM PDT 24
Finished Jun 06 12:44:29 PM PDT 24
Peak memory 196172 kb
Host smart-ad3f82b8-67ee-44fb-ad3f-aff4163e7427
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stress.3437330
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.289078753
Short name T6
Test name
Test status
Simulation time 107045068 ps
CPU time 1.07 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 196308 kb
Host smart-c9afc3bb-59de-49ea-89b5-16880d29ee8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289078753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.289078753
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2459668728
Short name T329
Test name
Test status
Simulation time 293181233 ps
CPU time 1.28 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 197176 kb
Host smart-ab0a73dc-76f2-4df7-8767-872236d7d2de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459668728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2459668728
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.454769862
Short name T228
Test name
Test status
Simulation time 656850817 ps
CPU time 3.83 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 197948 kb
Host smart-238a0673-6f8b-4ced-891c-b7c3aca94d28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454769862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.454769862
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2697641847
Short name T15
Test name
Test status
Simulation time 758654960 ps
CPU time 3.23 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 197088 kb
Host smart-b70e0621-98ac-4f33-8b28-af9cd4aecd07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697641847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2697641847
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1860023624
Short name T390
Test name
Test status
Simulation time 132982059 ps
CPU time 0.88 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:05 PM PDT 24
Peak memory 197324 kb
Host smart-e451de45-253d-4fe8-bad5-6982f7b6c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860023624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1860023624
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2978522080
Short name T25
Test name
Test status
Simulation time 18058066 ps
CPU time 0.77 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 195384 kb
Host smart-f40ffa6a-6473-47b2-b0f4-89e652ba0cb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978522080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2978522080
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1484736651
Short name T462
Test name
Test status
Simulation time 53504233 ps
CPU time 2.36 seconds
Started Jun 06 12:44:03 PM PDT 24
Finished Jun 06 12:44:07 PM PDT 24
Peak memory 197892 kb
Host smart-905b8477-4571-4aa0-a1a0-0a890cce53ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484736651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1484736651
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.29364936
Short name T179
Test name
Test status
Simulation time 182316350 ps
CPU time 1 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 196392 kb
Host smart-bf950211-ba49-4d71-8b5a-9fe53320b80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29364936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.29364936
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2963397087
Short name T417
Test name
Test status
Simulation time 111875391 ps
CPU time 1.09 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 195512 kb
Host smart-20dc9024-d975-485e-8719-767a9965e453
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963397087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2963397087
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1658019494
Short name T707
Test name
Test status
Simulation time 6289470658 ps
CPU time 75.5 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:45:19 PM PDT 24
Peak memory 198128 kb
Host smart-74a35222-1a70-46ec-9dcf-5765de79f835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658019494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1658019494
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1016189053
Short name T702
Test name
Test status
Simulation time 104819379636 ps
CPU time 2091.14 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 01:18:53 PM PDT 24
Peak memory 197844 kb
Host smart-a351718a-696f-4e4b-8e5b-dc073ef2c7fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1016189053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1016189053
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.352378852
Short name T208
Test name
Test status
Simulation time 13596436 ps
CPU time 0.55 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:05 PM PDT 24
Peak memory 193748 kb
Host smart-876f682d-b69f-4118-bc49-14b99bc4eac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352378852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.352378852
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1800989774
Short name T96
Test name
Test status
Simulation time 51576759 ps
CPU time 0.77 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 195272 kb
Host smart-7cb5a24c-2fa5-4875-8587-310d7c67c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800989774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1800989774
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.591203189
Short name T306
Test name
Test status
Simulation time 438837726 ps
CPU time 18.7 seconds
Started Jun 06 12:44:03 PM PDT 24
Finished Jun 06 12:44:23 PM PDT 24
Peak memory 196652 kb
Host smart-be75ca8c-ddc0-498e-9afd-d71e91e2aafe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591203189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.591203189
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.4116377832
Short name T470
Test name
Test status
Simulation time 133972667 ps
CPU time 0.78 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 196524 kb
Host smart-1392fd37-efb3-4701-a847-a29f349a68bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116377832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.4116377832
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.91929214
Short name T158
Test name
Test status
Simulation time 154323114 ps
CPU time 1.3 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 196732 kb
Host smart-2e535e8d-d05d-4b41-b1be-092a26442c9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91929214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.91929214
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1379211665
Short name T667
Test name
Test status
Simulation time 132401025 ps
CPU time 2.63 seconds
Started Jun 06 12:44:01 PM PDT 24
Finished Jun 06 12:44:06 PM PDT 24
Peak memory 197980 kb
Host smart-e83f89e1-7088-4130-87af-7596e50638bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379211665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1379211665
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4005636145
Short name T170
Test name
Test status
Simulation time 532720680 ps
CPU time 2.74 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 195640 kb
Host smart-2e9c7650-4b91-4f7c-b245-1be788ff3c43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005636145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4005636145
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.714328695
Short name T643
Test name
Test status
Simulation time 24193192 ps
CPU time 0.93 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 195932 kb
Host smart-a4ac2f8a-f87b-47e7-adc1-82afab65ee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714328695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.714328695
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3165735444
Short name T576
Test name
Test status
Simulation time 100665161 ps
CPU time 1.2 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 197020 kb
Host smart-751d5dc9-b79a-4223-a40b-fbc4cb15ab71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165735444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3165735444
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2150341189
Short name T545
Test name
Test status
Simulation time 85316261 ps
CPU time 1.44 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 197776 kb
Host smart-4bfbf5a8-8600-465a-acbc-af6b9063b09a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150341189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2150341189
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1765663923
Short name T602
Test name
Test status
Simulation time 47383842 ps
CPU time 1.01 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:03 PM PDT 24
Peak memory 195948 kb
Host smart-7bc96dfc-11a4-40b6-b35c-8d7b9734c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765663923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1765663923
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2653417620
Short name T404
Test name
Test status
Simulation time 136765359 ps
CPU time 1.29 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 196688 kb
Host smart-dbef969f-a375-44f8-931c-9c61a566ca64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653417620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2653417620
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3011899562
Short name T137
Test name
Test status
Simulation time 82163082001 ps
CPU time 98.38 seconds
Started Jun 06 12:43:59 PM PDT 24
Finished Jun 06 12:45:38 PM PDT 24
Peak memory 197976 kb
Host smart-7c734440-ca51-4e61-ba8c-d31c3aea2b81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011899562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3011899562
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3187189823
Short name T506
Test name
Test status
Simulation time 14951175 ps
CPU time 0.58 seconds
Started Jun 06 12:44:06 PM PDT 24
Finished Jun 06 12:44:08 PM PDT 24
Peak memory 193884 kb
Host smart-50714422-6084-4507-a484-2fe8da1b22f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187189823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3187189823
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1295126984
Short name T280
Test name
Test status
Simulation time 159090531 ps
CPU time 0.94 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:05 PM PDT 24
Peak memory 195852 kb
Host smart-f07cf926-3ccb-43ed-bc07-583f448de559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295126984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1295126984
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4261708204
Short name T232
Test name
Test status
Simulation time 3301740392 ps
CPU time 22.46 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:26 PM PDT 24
Peak memory 197384 kb
Host smart-52eacd7d-2f50-42a0-af8d-171ac6b741f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261708204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4261708204
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3497329458
Short name T597
Test name
Test status
Simulation time 115972657 ps
CPU time 0.64 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 194588 kb
Host smart-276aacd3-48bd-43b1-a4cc-ef3e0385e477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497329458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3497329458
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3315145140
Short name T358
Test name
Test status
Simulation time 89296481 ps
CPU time 0.84 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 196644 kb
Host smart-4074d3cb-fa51-4d0e-a088-e0a40a786950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315145140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3315145140
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.539417632
Short name T427
Test name
Test status
Simulation time 223631219 ps
CPU time 2.59 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:04 PM PDT 24
Peak memory 197112 kb
Host smart-a12df026-0a73-4905-91fc-cb2456a58c41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539417632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.539417632
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3895480123
Short name T484
Test name
Test status
Simulation time 759171224 ps
CPU time 3.45 seconds
Started Jun 06 12:44:04 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 198016 kb
Host smart-a0d2fc18-8359-4b80-b87b-637d5ffb82f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895480123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3895480123
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.219955512
Short name T696
Test name
Test status
Simulation time 111316908 ps
CPU time 1.06 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:05 PM PDT 24
Peak memory 195724 kb
Host smart-de061d54-df3b-4972-b4a2-d2413c5a67b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219955512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.219955512
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3399728952
Short name T326
Test name
Test status
Simulation time 59184300 ps
CPU time 1.28 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:05 PM PDT 24
Peak memory 198048 kb
Host smart-0926543a-d145-4d80-89e0-d3fef3ecaf01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399728952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3399728952
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3519116824
Short name T436
Test name
Test status
Simulation time 1940634395 ps
CPU time 5.09 seconds
Started Jun 06 12:44:04 PM PDT 24
Finished Jun 06 12:44:10 PM PDT 24
Peak memory 198012 kb
Host smart-5eeac645-9617-4a5a-a2b5-886fb605ab34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519116824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3519116824
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1799391055
Short name T235
Test name
Test status
Simulation time 120492848 ps
CPU time 0.98 seconds
Started Jun 06 12:44:02 PM PDT 24
Finished Jun 06 12:44:05 PM PDT 24
Peak memory 195552 kb
Host smart-35f6f07e-ef9f-407d-952e-78c0248d5751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799391055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1799391055
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4115997873
Short name T260
Test name
Test status
Simulation time 149212403 ps
CPU time 0.94 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 196952 kb
Host smart-abda9067-8eaa-4551-b320-6afb2d5dfb21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115997873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4115997873
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3612067907
Short name T47
Test name
Test status
Simulation time 17082780877 ps
CPU time 91.36 seconds
Started Jun 06 12:44:00 PM PDT 24
Finished Jun 06 12:45:32 PM PDT 24
Peak memory 198064 kb
Host smart-0f87c5b1-c319-433a-a49e-8a42236d1f29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612067907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3612067907
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1464570557
Short name T657
Test name
Test status
Simulation time 12237061 ps
CPU time 0.57 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 194700 kb
Host smart-662dfbb7-c956-426b-94b6-34781e0b5baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464570557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1464570557
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.350633945
Short name T570
Test name
Test status
Simulation time 122121410 ps
CPU time 0.7 seconds
Started Jun 06 12:44:06 PM PDT 24
Finished Jun 06 12:44:08 PM PDT 24
Peak memory 195148 kb
Host smart-c5ef9f1c-4e10-45a2-9ad0-582c9c73e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350633945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.350633945
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2255815921
Short name T529
Test name
Test status
Simulation time 970391771 ps
CPU time 13.02 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:21 PM PDT 24
Peak memory 196880 kb
Host smart-6e4deae9-c870-4cb6-b324-aca593ffec40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255815921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2255815921
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4259820873
Short name T127
Test name
Test status
Simulation time 34667529 ps
CPU time 0.69 seconds
Started Jun 06 12:44:11 PM PDT 24
Finished Jun 06 12:44:13 PM PDT 24
Peak memory 194592 kb
Host smart-05645f4c-3385-42ed-b424-0d2921f4822c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259820873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4259820873
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.397620615
Short name T601
Test name
Test status
Simulation time 79685602 ps
CPU time 1.49 seconds
Started Jun 06 12:44:09 PM PDT 24
Finished Jun 06 12:44:11 PM PDT 24
Peak memory 197032 kb
Host smart-0bffd777-dee9-4600-8765-a573aded2256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397620615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.397620615
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3572813564
Short name T266
Test name
Test status
Simulation time 133052986 ps
CPU time 1.55 seconds
Started Jun 06 12:44:06 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 196284 kb
Host smart-a7d6114b-4d25-4685-8640-c405f30ce7f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572813564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3572813564
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1258558631
Short name T688
Test name
Test status
Simulation time 203156883 ps
CPU time 2.31 seconds
Started Jun 06 12:44:06 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 195724 kb
Host smart-512ceb48-42d1-4662-9a11-c451c1a229eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258558631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1258558631
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3420641877
Short name T245
Test name
Test status
Simulation time 36600582 ps
CPU time 1.36 seconds
Started Jun 06 12:44:10 PM PDT 24
Finished Jun 06 12:44:12 PM PDT 24
Peak memory 197976 kb
Host smart-e95e69f5-cb1b-483e-ae5a-ec9e3ff56359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420641877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3420641877
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2921094223
Short name T687
Test name
Test status
Simulation time 70485508 ps
CPU time 1.08 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 196560 kb
Host smart-3f77ca34-95fc-4518-b1c8-4a479f17ddfd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921094223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2921094223
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3179281922
Short name T485
Test name
Test status
Simulation time 88127109 ps
CPU time 3.99 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:12 PM PDT 24
Peak memory 197820 kb
Host smart-db1e3878-f192-4ac8-bc12-b2c4a35a0f34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179281922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3179281922
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.50339790
Short name T477
Test name
Test status
Simulation time 35573679 ps
CPU time 0.78 seconds
Started Jun 06 12:44:10 PM PDT 24
Finished Jun 06 12:44:11 PM PDT 24
Peak memory 195976 kb
Host smart-85dbc138-f640-46cb-ab21-f04b2edbe6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50339790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.50339790
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1015667635
Short name T515
Test name
Test status
Simulation time 45996201 ps
CPU time 0.95 seconds
Started Jun 06 12:44:09 PM PDT 24
Finished Jun 06 12:44:11 PM PDT 24
Peak memory 195080 kb
Host smart-8e70ebd3-a9cf-4580-ad73-903ec364510f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015667635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1015667635
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.557289044
Short name T9
Test name
Test status
Simulation time 46140152852 ps
CPU time 106.64 seconds
Started Jun 06 12:44:06 PM PDT 24
Finished Jun 06 12:45:54 PM PDT 24
Peak memory 198140 kb
Host smart-faddde9e-7515-43f2-be3d-ed6ea82fbc0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557289044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.557289044
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3046985359
Short name T651
Test name
Test status
Simulation time 37896628 ps
CPU time 0.55 seconds
Started Jun 06 12:44:08 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 193880 kb
Host smart-82c66439-09b3-431f-8e5a-86fac3f341df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046985359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3046985359
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.4267805072
Short name T619
Test name
Test status
Simulation time 62049779 ps
CPU time 0.82 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 196048 kb
Host smart-d0ea3d2f-3413-4a18-9fe1-904823167d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267805072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.4267805072
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.739179618
Short name T453
Test name
Test status
Simulation time 1007456780 ps
CPU time 14.62 seconds
Started Jun 06 12:44:08 PM PDT 24
Finished Jun 06 12:44:24 PM PDT 24
Peak memory 196964 kb
Host smart-c63411dc-cddc-4775-a86e-dab3c17f1772
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739179618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.739179618
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4052298475
Short name T120
Test name
Test status
Simulation time 113323153 ps
CPU time 0.86 seconds
Started Jun 06 12:44:11 PM PDT 24
Finished Jun 06 12:44:13 PM PDT 24
Peak memory 196872 kb
Host smart-7e183cb0-e95e-491a-a46b-33c0a0dbbcc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052298475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4052298475
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.4037190433
Short name T719
Test name
Test status
Simulation time 84256752 ps
CPU time 1.24 seconds
Started Jun 06 12:44:10 PM PDT 24
Finished Jun 06 12:44:12 PM PDT 24
Peak memory 195776 kb
Host smart-5067a41f-146e-4c56-bd57-aadb75e44314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037190433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.4037190433
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1663807668
Short name T649
Test name
Test status
Simulation time 637913291 ps
CPU time 2.64 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:10 PM PDT 24
Peak memory 198040 kb
Host smart-294feb69-9a20-41cf-8960-42318ab940da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663807668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1663807668
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2836471725
Short name T512
Test name
Test status
Simulation time 404283757 ps
CPU time 2.91 seconds
Started Jun 06 12:44:08 PM PDT 24
Finished Jun 06 12:44:12 PM PDT 24
Peak memory 195748 kb
Host smart-c7792f37-31e9-40e4-b28f-bbb75f444822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836471725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2836471725
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1851223153
Short name T248
Test name
Test status
Simulation time 60520058 ps
CPU time 1.28 seconds
Started Jun 06 12:44:05 PM PDT 24
Finished Jun 06 12:44:08 PM PDT 24
Peak memory 196968 kb
Host smart-b2717c5a-0630-47ae-9074-b8b85e13af1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851223153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1851223153
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.224743561
Short name T498
Test name
Test status
Simulation time 89586574 ps
CPU time 1.08 seconds
Started Jun 06 12:44:25 PM PDT 24
Finished Jun 06 12:44:27 PM PDT 24
Peak memory 196748 kb
Host smart-cbb38e05-6af3-47ff-a1de-5ab096f0a292
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224743561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.224743561
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3670122176
Short name T267
Test name
Test status
Simulation time 282239189 ps
CPU time 3.4 seconds
Started Jun 06 12:44:11 PM PDT 24
Finished Jun 06 12:44:16 PM PDT 24
Peak memory 197880 kb
Host smart-83cf9a6a-3259-4c1d-ac91-c415e87ab767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670122176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3670122176
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1678408511
Short name T523
Test name
Test status
Simulation time 27251157 ps
CPU time 0.83 seconds
Started Jun 06 12:44:08 PM PDT 24
Finished Jun 06 12:44:10 PM PDT 24
Peak memory 195204 kb
Host smart-5ccd2ce1-301f-4036-bd92-d6f0e90f9795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678408511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1678408511
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.287068071
Short name T395
Test name
Test status
Simulation time 70137570 ps
CPU time 1.35 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 195536 kb
Host smart-984eb913-a901-4454-afd7-9c8a2858037b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287068071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.287068071
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.99419802
Short name T489
Test name
Test status
Simulation time 49764199084 ps
CPU time 163.35 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:46:52 PM PDT 24
Peak memory 198132 kb
Host smart-8a8ed0b9-0184-4796-93dd-a6cafd14bad1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99419802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gp
io_stress_all.99419802
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1040400966
Short name T685
Test name
Test status
Simulation time 33704892 ps
CPU time 0.56 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:18 PM PDT 24
Peak memory 193884 kb
Host smart-b979554b-2a8d-4eee-b3a2-728eca5523d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040400966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1040400966
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.50460950
Short name T225
Test name
Test status
Simulation time 226655646 ps
CPU time 0.88 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:19 PM PDT 24
Peak memory 196176 kb
Host smart-92d04f8e-3d18-4570-afa4-b6c82759a73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50460950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.50460950
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1584897410
Short name T441
Test name
Test status
Simulation time 407523047 ps
CPU time 19.92 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 196784 kb
Host smart-cb0fb82e-9a2e-47e3-9215-99aa8bffee56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584897410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1584897410
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2089863516
Short name T463
Test name
Test status
Simulation time 275128611 ps
CPU time 0.96 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:21 PM PDT 24
Peak memory 196648 kb
Host smart-3f82b353-4295-4d28-aae6-e3d401ddbcd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089863516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2089863516
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3720448996
Short name T146
Test name
Test status
Simulation time 141840818 ps
CPU time 0.86 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:18 PM PDT 24
Peak memory 195552 kb
Host smart-d99d8d03-85a6-472c-84a7-b9ceefe0f981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720448996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3720448996
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.435889912
Short name T585
Test name
Test status
Simulation time 86474147 ps
CPU time 3.48 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:24 PM PDT 24
Peak memory 197852 kb
Host smart-d02f6ea9-09d8-4e67-a20d-cded9dd98a47
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435889912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.435889912
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1625578359
Short name T458
Test name
Test status
Simulation time 140286234 ps
CPU time 1.16 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:19 PM PDT 24
Peak memory 195608 kb
Host smart-e3882095-0b82-48bf-970a-916febe914c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625578359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1625578359
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1579990848
Short name T166
Test name
Test status
Simulation time 93130859 ps
CPU time 0.95 seconds
Started Jun 06 12:45:09 PM PDT 24
Finished Jun 06 12:45:10 PM PDT 24
Peak memory 195756 kb
Host smart-5bad9b31-7cae-423a-9c78-509fe159716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579990848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1579990848
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1877909091
Short name T342
Test name
Test status
Simulation time 47267161 ps
CPU time 0.93 seconds
Started Jun 06 12:44:08 PM PDT 24
Finished Jun 06 12:44:10 PM PDT 24
Peak memory 196016 kb
Host smart-f7bf1465-189e-4d1e-a183-a5a9085990c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877909091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1877909091
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1524548037
Short name T7
Test name
Test status
Simulation time 629335137 ps
CPU time 5.24 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:44:24 PM PDT 24
Peak memory 197892 kb
Host smart-cb66aded-8440-4dfc-9a5f-c2c2cd450ef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524548037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1524548037
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.106298775
Short name T243
Test name
Test status
Simulation time 114241658 ps
CPU time 1.12 seconds
Started Jun 06 12:45:09 PM PDT 24
Finished Jun 06 12:45:11 PM PDT 24
Peak memory 195588 kb
Host smart-382a7d94-82c4-4a3a-a483-6a9d8ffec599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106298775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.106298775
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2229151564
Short name T174
Test name
Test status
Simulation time 34976901 ps
CPU time 1.1 seconds
Started Jun 06 12:44:07 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 195512 kb
Host smart-760b16d4-d111-487a-a6b9-cc9c21630d94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229151564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2229151564
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2887543194
Short name T20
Test name
Test status
Simulation time 65587867665 ps
CPU time 185.71 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:47:26 PM PDT 24
Peak memory 198172 kb
Host smart-70adb9f9-8345-4005-8c4f-12b38ca9daf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887543194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2887543194
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2567454786
Short name T704
Test name
Test status
Simulation time 176698189835 ps
CPU time 510.62 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:52:48 PM PDT 24
Peak memory 198216 kb
Host smart-e826b22a-3652-49ee-92a5-5e7024fc87e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2567454786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2567454786
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1602040698
Short name T160
Test name
Test status
Simulation time 32873958 ps
CPU time 0.57 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:18 PM PDT 24
Peak memory 193744 kb
Host smart-bc718c91-b6e4-44c8-b1c6-c5a6e6cdaf26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602040698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1602040698
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1311939232
Short name T131
Test name
Test status
Simulation time 45208216 ps
CPU time 0.63 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:44:20 PM PDT 24
Peak memory 194644 kb
Host smart-c92190b7-ff4b-4359-8a93-206e3c8da1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311939232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1311939232
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3301128156
Short name T274
Test name
Test status
Simulation time 937686918 ps
CPU time 26.39 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 196772 kb
Host smart-4ff0bf08-23bd-406b-94b0-b30d732c8a3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301128156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3301128156
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3100203043
Short name T5
Test name
Test status
Simulation time 334879972 ps
CPU time 1.09 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:21 PM PDT 24
Peak memory 197520 kb
Host smart-d0ca6d64-177c-4424-a347-60d7486c90dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100203043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3100203043
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2381853355
Short name T272
Test name
Test status
Simulation time 105831816 ps
CPU time 0.72 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:44:20 PM PDT 24
Peak memory 194352 kb
Host smart-17bccc37-f71f-4918-a046-b5f65f2a14c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381853355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2381853355
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3528329247
Short name T154
Test name
Test status
Simulation time 41712358 ps
CPU time 1.61 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:22 PM PDT 24
Peak memory 196388 kb
Host smart-e75b7649-a02d-4b14-a204-6df7e3bca101
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528329247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3528329247
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3388186562
Short name T540
Test name
Test status
Simulation time 578863811 ps
CPU time 3.11 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:23 PM PDT 24
Peak memory 197088 kb
Host smart-3e001d32-d08c-4f51-96fa-2098d2200203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388186562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3388186562
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3393056517
Short name T617
Test name
Test status
Simulation time 290716689 ps
CPU time 1.33 seconds
Started Jun 06 12:44:23 PM PDT 24
Finished Jun 06 12:44:25 PM PDT 24
Peak memory 197012 kb
Host smart-10b94943-494d-4eb8-9d43-066a4298bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393056517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3393056517
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.411146971
Short name T128
Test name
Test status
Simulation time 68761364 ps
CPU time 0.88 seconds
Started Jun 06 12:44:20 PM PDT 24
Finished Jun 06 12:44:22 PM PDT 24
Peak memory 195812 kb
Host smart-f839b733-e03b-460b-b277-6851c894f98d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411146971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.411146971
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3054620330
Short name T368
Test name
Test status
Simulation time 73788238 ps
CPU time 1.25 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:44:21 PM PDT 24
Peak memory 197804 kb
Host smart-323db83c-c158-4bf9-a32e-94919d487ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054620330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3054620330
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3567476179
Short name T264
Test name
Test status
Simulation time 546847303 ps
CPU time 1.08 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:19 PM PDT 24
Peak memory 195644 kb
Host smart-d3e1ac36-656f-40de-ad61-8ec318e2f361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567476179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3567476179
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1272538485
Short name T439
Test name
Test status
Simulation time 155174300 ps
CPU time 0.93 seconds
Started Jun 06 12:44:23 PM PDT 24
Finished Jun 06 12:44:24 PM PDT 24
Peak memory 195596 kb
Host smart-8d925d3f-9494-45d9-9bd1-dacaf701c549
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272538485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1272538485
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3124483625
Short name T141
Test name
Test status
Simulation time 1946707545 ps
CPU time 54.61 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:45:14 PM PDT 24
Peak memory 197980 kb
Host smart-c20a60ca-b5bd-4cd3-9708-2f12534a2a09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124483625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3124483625
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3146032495
Short name T98
Test name
Test status
Simulation time 338648464886 ps
CPU time 1020.06 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 01:01:18 PM PDT 24
Peak memory 198176 kb
Host smart-9ac7c58c-c98d-449c-abb2-5665f5c3ec7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3146032495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3146032495
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3925484288
Short name T339
Test name
Test status
Simulation time 35163615 ps
CPU time 0.57 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 193952 kb
Host smart-184788f0-713b-4d9d-8377-54b632bb96e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925484288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3925484288
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1109655961
Short name T302
Test name
Test status
Simulation time 39916657 ps
CPU time 0.86 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:17 PM PDT 24
Peak memory 197236 kb
Host smart-b2045bf4-0213-4498-b617-e7d18af73f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109655961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1109655961
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3034709105
Short name T115
Test name
Test status
Simulation time 1766806206 ps
CPU time 17.56 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:32 PM PDT 24
Peak memory 197972 kb
Host smart-d087f69d-6421-4441-b72b-b104025665c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034709105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3034709105
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3087121503
Short name T19
Test name
Test status
Simulation time 92205830 ps
CPU time 0.81 seconds
Started Jun 06 12:43:11 PM PDT 24
Finished Jun 06 12:43:13 PM PDT 24
Peak memory 195732 kb
Host smart-dff82ff0-c622-4964-91a9-a75528e49861
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087121503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3087121503
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.806312909
Short name T162
Test name
Test status
Simulation time 88966840 ps
CPU time 0.81 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 195600 kb
Host smart-5063201b-5cf2-4067-8b25-24a53dc3da52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806312909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.806312909
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.889615915
Short name T680
Test name
Test status
Simulation time 79156322 ps
CPU time 1.13 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 197188 kb
Host smart-40455ef0-4d34-4dfb-87f3-ada450a4ff07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889615915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.889615915
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3658979934
Short name T314
Test name
Test status
Simulation time 451446613 ps
CPU time 2.2 seconds
Started Jun 06 12:43:12 PM PDT 24
Finished Jun 06 12:43:15 PM PDT 24
Peak memory 197964 kb
Host smart-760b1ad3-d554-4ec6-a0e5-ac69e995bb40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658979934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3658979934
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.725560405
Short name T469
Test name
Test status
Simulation time 26596345 ps
CPU time 0.97 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 195964 kb
Host smart-306a908a-40cc-481f-a8c5-91a310ba43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725560405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.725560405
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.57553826
Short name T125
Test name
Test status
Simulation time 24810837 ps
CPU time 0.98 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 196440 kb
Host smart-4e0e3cd3-5050-48a0-a0be-a331908c831b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57553826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_p
ulldown.57553826
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.574932220
Short name T222
Test name
Test status
Simulation time 2093135083 ps
CPU time 5.8 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:21 PM PDT 24
Peak memory 197872 kb
Host smart-68485a97-da8c-4e35-8898-7cb9a48ceef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574932220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.574932220
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2829272340
Short name T45
Test name
Test status
Simulation time 273942951 ps
CPU time 0.91 seconds
Started Jun 06 12:43:20 PM PDT 24
Finished Jun 06 12:43:21 PM PDT 24
Peak memory 213452 kb
Host smart-7c211c89-9a63-4d83-91dc-f126ad6a616e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829272340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2829272340
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3923249313
Short name T269
Test name
Test status
Simulation time 55535228 ps
CPU time 1.02 seconds
Started Jun 06 12:43:15 PM PDT 24
Finished Jun 06 12:43:17 PM PDT 24
Peak memory 195640 kb
Host smart-0dbe2a75-ef82-49e1-bc99-d70acea788d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923249313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3923249313
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.743557110
Short name T587
Test name
Test status
Simulation time 154558645 ps
CPU time 1.32 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 196560 kb
Host smart-2c182573-16eb-47f9-9c1d-70dd7a0d720c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743557110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.743557110
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1667359887
Short name T684
Test name
Test status
Simulation time 7573419176 ps
CPU time 105.34 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:45:01 PM PDT 24
Peak memory 198100 kb
Host smart-e67a4e0d-d2ff-443d-9a6b-711c6ab3c5aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667359887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1667359887
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.4233271449
Short name T382
Test name
Test status
Simulation time 20153621 ps
CPU time 0.58 seconds
Started Jun 06 12:44:27 PM PDT 24
Finished Jun 06 12:44:28 PM PDT 24
Peak memory 193884 kb
Host smart-6a2733ab-130f-48a9-ae42-e7f26e328eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233271449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.4233271449
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.586822060
Short name T197
Test name
Test status
Simulation time 49958150 ps
CPU time 0.9 seconds
Started Jun 06 12:44:16 PM PDT 24
Finished Jun 06 12:44:18 PM PDT 24
Peak memory 195884 kb
Host smart-254ebfc2-7071-4018-9610-8ad1647667f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586822060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.586822060
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4035742724
Short name T676
Test name
Test status
Simulation time 12009034658 ps
CPU time 22.07 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:41 PM PDT 24
Peak memory 196708 kb
Host smart-ca1ce1ae-5718-4711-b43f-e62da5bbc585
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035742724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4035742724
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1501523255
Short name T214
Test name
Test status
Simulation time 128459562 ps
CPU time 0.96 seconds
Started Jun 06 12:44:23 PM PDT 24
Finished Jun 06 12:44:24 PM PDT 24
Peak memory 197264 kb
Host smart-35ad0962-bc13-4747-abfe-50c4ff4dad13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501523255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1501523255
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.230160856
Short name T206
Test name
Test status
Simulation time 26791837 ps
CPU time 0.8 seconds
Started Jun 06 12:44:23 PM PDT 24
Finished Jun 06 12:44:25 PM PDT 24
Peak memory 196308 kb
Host smart-a95cd39a-256e-4679-a3d9-2fa72bffba35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230160856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.230160856
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2628506622
Short name T153
Test name
Test status
Simulation time 954725685 ps
CPU time 3.41 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:44:23 PM PDT 24
Peak memory 197960 kb
Host smart-4ff84684-dcb6-419d-8d91-8e8b623bc940
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628506622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2628506622
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3184698432
Short name T598
Test name
Test status
Simulation time 102832716 ps
CPU time 0.92 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:44:20 PM PDT 24
Peak memory 196148 kb
Host smart-8dbe3885-d1a2-43d6-aab1-95b5c3c979c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184698432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3184698432
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2853840415
Short name T353
Test name
Test status
Simulation time 32272836 ps
CPU time 1.24 seconds
Started Jun 06 12:44:16 PM PDT 24
Finished Jun 06 12:44:18 PM PDT 24
Peak memory 197952 kb
Host smart-c85b2a00-13ff-48b7-85c5-7f851b338bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853840415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2853840415
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4227520056
Short name T583
Test name
Test status
Simulation time 106309585 ps
CPU time 1.1 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:19 PM PDT 24
Peak memory 195836 kb
Host smart-43a4b973-9d29-40be-ad58-45f8039c91e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227520056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4227520056
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.122853748
Short name T371
Test name
Test status
Simulation time 261520237 ps
CPU time 3.73 seconds
Started Jun 06 12:44:19 PM PDT 24
Finished Jun 06 12:44:23 PM PDT 24
Peak memory 197964 kb
Host smart-22f8388e-c3ba-492a-8a15-8b9ca3d36125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122853748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.122853748
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.555468236
Short name T123
Test name
Test status
Simulation time 334249002 ps
CPU time 1.28 seconds
Started Jun 06 12:44:20 PM PDT 24
Finished Jun 06 12:44:22 PM PDT 24
Peak memory 196780 kb
Host smart-11ac7675-9270-4bfc-9672-a914f8a5fd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555468236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.555468236
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2871186243
Short name T117
Test name
Test status
Simulation time 515046682 ps
CPU time 0.94 seconds
Started Jun 06 12:44:17 PM PDT 24
Finished Jun 06 12:44:19 PM PDT 24
Peak memory 197080 kb
Host smart-6f132488-03f1-46d9-af6b-2adf3e784ecd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871186243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2871186243
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2240591796
Short name T449
Test name
Test status
Simulation time 128768974259 ps
CPU time 190.19 seconds
Started Jun 06 12:44:21 PM PDT 24
Finished Jun 06 12:47:32 PM PDT 24
Peak memory 198116 kb
Host smart-2d4c723f-93c4-4fb8-9c93-7f52fe3d8beb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240591796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2240591796
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.672781867
Short name T60
Test name
Test status
Simulation time 24878577800 ps
CPU time 430.06 seconds
Started Jun 06 12:44:18 PM PDT 24
Finished Jun 06 12:51:29 PM PDT 24
Peak memory 198176 kb
Host smart-a1319e0a-dc40-47a3-a1b9-db7f5f0d8233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=672781867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.672781867
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3662107632
Short name T497
Test name
Test status
Simulation time 55110602 ps
CPU time 0.54 seconds
Started Jun 06 12:44:26 PM PDT 24
Finished Jun 06 12:44:27 PM PDT 24
Peak memory 193800 kb
Host smart-9ac7d21a-8b1b-438b-aaa2-8aeae2a20746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662107632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3662107632
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2966605054
Short name T648
Test name
Test status
Simulation time 124751754 ps
CPU time 0.77 seconds
Started Jun 06 12:44:30 PM PDT 24
Finished Jun 06 12:44:31 PM PDT 24
Peak memory 195252 kb
Host smart-6c6d0e60-34c5-4e93-987f-e0994bc33243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966605054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2966605054
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1745306337
Short name T633
Test name
Test status
Simulation time 413330498 ps
CPU time 5.89 seconds
Started Jun 06 12:44:26 PM PDT 24
Finished Jun 06 12:44:33 PM PDT 24
Peak memory 196764 kb
Host smart-70bb0d38-fccc-4512-80aa-66ce6b0a76f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745306337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1745306337
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3405777001
Short name T481
Test name
Test status
Simulation time 69384178 ps
CPU time 1.07 seconds
Started Jun 06 12:44:28 PM PDT 24
Finished Jun 06 12:44:30 PM PDT 24
Peak memory 196548 kb
Host smart-078cb01f-352c-40ab-8517-df9cfb16602c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405777001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3405777001
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.801964732
Short name T360
Test name
Test status
Simulation time 83311610 ps
CPU time 0.78 seconds
Started Jun 06 12:44:26 PM PDT 24
Finished Jun 06 12:44:28 PM PDT 24
Peak memory 196256 kb
Host smart-9ca1fc71-6f08-4489-a1d7-c8972914fec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801964732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.801964732
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2269864501
Short name T631
Test name
Test status
Simulation time 183043787 ps
CPU time 1.05 seconds
Started Jun 06 12:44:29 PM PDT 24
Finished Jun 06 12:44:31 PM PDT 24
Peak memory 196756 kb
Host smart-555094c2-b1da-4276-8a56-3341e86f1900
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269864501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2269864501
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2186648155
Short name T521
Test name
Test status
Simulation time 120043589 ps
CPU time 2.85 seconds
Started Jun 06 12:44:27 PM PDT 24
Finished Jun 06 12:44:31 PM PDT 24
Peak memory 197128 kb
Host smart-941a11d5-75c0-4479-8226-e4694980b256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186648155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2186648155
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1073047663
Short name T185
Test name
Test status
Simulation time 35300796 ps
CPU time 1.29 seconds
Started Jun 06 12:44:27 PM PDT 24
Finished Jun 06 12:44:30 PM PDT 24
Peak memory 198000 kb
Host smart-cd24f077-340b-43a4-bd58-ed84e361558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073047663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1073047663
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4234010434
Short name T621
Test name
Test status
Simulation time 48126410 ps
CPU time 1.16 seconds
Started Jun 06 12:44:27 PM PDT 24
Finished Jun 06 12:44:29 PM PDT 24
Peak memory 196700 kb
Host smart-0d8c0bb9-0a24-462c-a6dc-320b0056a7af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234010434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.4234010434
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3468451011
Short name T414
Test name
Test status
Simulation time 93809038 ps
CPU time 2.21 seconds
Started Jun 06 12:44:28 PM PDT 24
Finished Jun 06 12:44:31 PM PDT 24
Peak memory 197940 kb
Host smart-bc387984-a3b3-49b8-b4b5-7b4f4dc9e6d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468451011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3468451011
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.995684192
Short name T700
Test name
Test status
Simulation time 45811912 ps
CPU time 0.99 seconds
Started Jun 06 12:44:30 PM PDT 24
Finished Jun 06 12:44:33 PM PDT 24
Peak memory 195744 kb
Host smart-50b4c374-b039-49fa-b4ee-82e8354b23e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995684192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.995684192
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2136871860
Short name T495
Test name
Test status
Simulation time 192461845 ps
CPU time 0.98 seconds
Started Jun 06 12:44:31 PM PDT 24
Finished Jun 06 12:44:33 PM PDT 24
Peak memory 195852 kb
Host smart-64d65e6d-979e-411f-b95b-7e0e65dc7482
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136871860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2136871860
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.780457770
Short name T487
Test name
Test status
Simulation time 96691530442 ps
CPU time 152.02 seconds
Started Jun 06 12:44:28 PM PDT 24
Finished Jun 06 12:47:01 PM PDT 24
Peak memory 198128 kb
Host smart-d7a875af-8dfd-4c44-a2c6-5cd286fe553f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780457770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.780457770
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2361711197
Short name T373
Test name
Test status
Simulation time 11755351 ps
CPU time 0.55 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:37 PM PDT 24
Peak memory 194528 kb
Host smart-11525722-8e2b-44d0-99f7-14e8d1d9a92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361711197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2361711197
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1702757236
Short name T673
Test name
Test status
Simulation time 42223163 ps
CPU time 0.92 seconds
Started Jun 06 12:44:38 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 195888 kb
Host smart-f7a74626-31e4-41fb-811d-aeaa77fd05fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702757236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1702757236
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1591861531
Short name T555
Test name
Test status
Simulation time 68684406 ps
CPU time 3.76 seconds
Started Jun 06 12:44:35 PM PDT 24
Finished Jun 06 12:44:39 PM PDT 24
Peak memory 195724 kb
Host smart-fd5846ae-128e-4b47-8d6c-fbb7c3a9af98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591861531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1591861531
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1438761601
Short name T3
Test name
Test status
Simulation time 614198955 ps
CPU time 1.06 seconds
Started Jun 06 12:44:40 PM PDT 24
Finished Jun 06 12:44:42 PM PDT 24
Peak memory 196284 kb
Host smart-2c87bb82-c349-47ee-891c-2e9faa07ffe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438761601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1438761601
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.180316593
Short name T349
Test name
Test status
Simulation time 80372205 ps
CPU time 1.13 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:38 PM PDT 24
Peak memory 196424 kb
Host smart-c8e0519a-eb7e-4499-a479-486a912bb65e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180316593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.180316593
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2392009315
Short name T310
Test name
Test status
Simulation time 35834048 ps
CPU time 0.94 seconds
Started Jun 06 12:44:35 PM PDT 24
Finished Jun 06 12:44:37 PM PDT 24
Peak memory 196136 kb
Host smart-f621d378-794e-4208-9daa-15aabf71e8bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392009315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2392009315
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2056237578
Short name T171
Test name
Test status
Simulation time 119611065 ps
CPU time 3.8 seconds
Started Jun 06 12:44:37 PM PDT 24
Finished Jun 06 12:44:42 PM PDT 24
Peak memory 195800 kb
Host smart-e5c648da-c587-4e0d-a0f1-996b404fba7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056237578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2056237578
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1772569350
Short name T715
Test name
Test status
Simulation time 30288545 ps
CPU time 0.8 seconds
Started Jun 06 12:44:39 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 195424 kb
Host smart-9fbb3906-c969-4f7c-a89f-3c6a22119159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772569350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1772569350
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.605622824
Short name T347
Test name
Test status
Simulation time 19689301 ps
CPU time 0.68 seconds
Started Jun 06 12:44:35 PM PDT 24
Finished Jun 06 12:44:36 PM PDT 24
Peak memory 194316 kb
Host smart-a1205a74-dcb7-45dd-bbc4-7bee3cab9117
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605622824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.605622824
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.736766597
Short name T224
Test name
Test status
Simulation time 1090201205 ps
CPU time 4.11 seconds
Started Jun 06 12:44:40 PM PDT 24
Finished Jun 06 12:44:45 PM PDT 24
Peak memory 197932 kb
Host smart-8fba0dbb-5dc9-4171-a5bc-4d34b3d82210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736766597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.736766597
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.651871664
Short name T547
Test name
Test status
Simulation time 82524267 ps
CPU time 1.23 seconds
Started Jun 06 12:44:26 PM PDT 24
Finished Jun 06 12:44:28 PM PDT 24
Peak memory 196828 kb
Host smart-134ddc8f-6ad4-4be4-a19d-7eef68178325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651871664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.651871664
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.614170878
Short name T140
Test name
Test status
Simulation time 343953930 ps
CPU time 1.25 seconds
Started Jun 06 12:44:38 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 196696 kb
Host smart-0a70bfe2-c625-4f54-8f33-8800458bebb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614170878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.614170878
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2293315152
Short name T488
Test name
Test status
Simulation time 269246202464 ps
CPU time 188.88 seconds
Started Jun 06 12:44:37 PM PDT 24
Finished Jun 06 12:47:47 PM PDT 24
Peak memory 198092 kb
Host smart-84c17871-f7fb-4f85-aef2-0668d29731fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293315152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2293315152
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4141939163
Short name T201
Test name
Test status
Simulation time 63285910 ps
CPU time 0.59 seconds
Started Jun 06 12:44:37 PM PDT 24
Finished Jun 06 12:44:39 PM PDT 24
Peak memory 193904 kb
Host smart-69230229-f946-44e9-9a2d-224fcff1b81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141939163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4141939163
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1588571628
Short name T227
Test name
Test status
Simulation time 19620818 ps
CPU time 0.67 seconds
Started Jun 06 12:44:37 PM PDT 24
Finished Jun 06 12:44:39 PM PDT 24
Peak memory 194816 kb
Host smart-45ad873c-1f05-4039-8d32-d335b19c1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588571628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1588571628
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1540476031
Short name T99
Test name
Test status
Simulation time 497468730 ps
CPU time 12.85 seconds
Started Jun 06 12:44:38 PM PDT 24
Finished Jun 06 12:44:51 PM PDT 24
Peak memory 197960 kb
Host smart-fdd30473-793c-43bc-8c81-cf6f6b159cdf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540476031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1540476031
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2897570303
Short name T273
Test name
Test status
Simulation time 79407509 ps
CPU time 0.75 seconds
Started Jun 06 12:44:37 PM PDT 24
Finished Jun 06 12:44:38 PM PDT 24
Peak memory 195780 kb
Host smart-b70b1ab7-c6b3-4bce-820f-237688640442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897570303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2897570303
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3133672288
Short name T295
Test name
Test status
Simulation time 92012753 ps
CPU time 1.23 seconds
Started Jun 06 12:44:38 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 197960 kb
Host smart-5c4f58c3-3199-4bee-89b3-3643441881ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133672288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3133672288
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3135513281
Short name T277
Test name
Test status
Simulation time 64294502 ps
CPU time 2.51 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 196728 kb
Host smart-b9f4468b-e809-4532-84a0-6c9f501865ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135513281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3135513281
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3985837510
Short name T340
Test name
Test status
Simulation time 54536789 ps
CPU time 0.91 seconds
Started Jun 06 12:44:37 PM PDT 24
Finished Jun 06 12:44:39 PM PDT 24
Peak memory 194492 kb
Host smart-baf99334-5be9-453f-841a-16365ee5e412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985837510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3985837510
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.706404619
Short name T522
Test name
Test status
Simulation time 31896579 ps
CPU time 0.86 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:38 PM PDT 24
Peak memory 195924 kb
Host smart-59a5fb83-a131-4380-95c7-5a6e40356a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706404619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.706404619
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2779561946
Short name T714
Test name
Test status
Simulation time 29415091 ps
CPU time 1.1 seconds
Started Jun 06 12:44:39 PM PDT 24
Finished Jun 06 12:44:41 PM PDT 24
Peak memory 196484 kb
Host smart-f7936137-bc16-487f-ad7c-cde91bffb68f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779561946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2779561946
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3910192083
Short name T475
Test name
Test status
Simulation time 29934269 ps
CPU time 1.45 seconds
Started Jun 06 12:44:38 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 197916 kb
Host smart-f191283b-5d74-40a2-9f31-d6f487f55668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910192083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3910192083
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3283466252
Short name T186
Test name
Test status
Simulation time 226256825 ps
CPU time 1.13 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:38 PM PDT 24
Peak memory 195428 kb
Host smart-a9461d8e-9fcf-4eb7-a5f8-f09cf0e9911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283466252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3283466252
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2012913856
Short name T552
Test name
Test status
Simulation time 39471459 ps
CPU time 0.83 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:38 PM PDT 24
Peak memory 195316 kb
Host smart-ce948427-8940-4f1d-b7ef-10e3418bd6ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012913856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2012913856
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2404936400
Short name T718
Test name
Test status
Simulation time 14694675966 ps
CPU time 212.71 seconds
Started Jun 06 12:44:35 PM PDT 24
Finished Jun 06 12:48:09 PM PDT 24
Peak memory 198104 kb
Host smart-ffbc990b-aca5-4981-b625-daa1244d0537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404936400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2404936400
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3328616701
Short name T706
Test name
Test status
Simulation time 15751000 ps
CPU time 0.58 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 194744 kb
Host smart-ba5f7f57-730b-4279-aad4-0a8a5dfb5f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328616701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3328616701
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1045595173
Short name T567
Test name
Test status
Simulation time 77799010 ps
CPU time 0.67 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:37 PM PDT 24
Peak memory 194104 kb
Host smart-702333f0-08b1-430c-80c3-653579f5a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045595173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1045595173
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2249710586
Short name T177
Test name
Test status
Simulation time 308194734 ps
CPU time 4.03 seconds
Started Jun 06 12:44:43 PM PDT 24
Finished Jun 06 12:44:48 PM PDT 24
Peak memory 195720 kb
Host smart-a169f5c6-6101-4dab-bd33-b5865149bc23
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249710586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2249710586
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.487798403
Short name T14
Test name
Test status
Simulation time 46466565 ps
CPU time 0.81 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:44:46 PM PDT 24
Peak memory 195732 kb
Host smart-54722f7f-f93d-414d-be56-c7dece9bf751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487798403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.487798403
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1009288848
Short name T606
Test name
Test status
Simulation time 25615124 ps
CPU time 0.64 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 194324 kb
Host smart-fb5466a6-fde0-4b8e-ac47-0e5150956ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009288848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1009288848
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.456688644
Short name T705
Test name
Test status
Simulation time 47040093 ps
CPU time 1.86 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 198028 kb
Host smart-18631ebb-4816-406c-b802-c294377c0ef0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456688644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.456688644
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1936245983
Short name T361
Test name
Test status
Simulation time 89542038 ps
CPU time 2.02 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 195788 kb
Host smart-36bf6099-8152-4d9c-b310-957fa4f80a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936245983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1936245983
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3502632081
Short name T580
Test name
Test status
Simulation time 292889327 ps
CPU time 1.3 seconds
Started Jun 06 12:44:35 PM PDT 24
Finished Jun 06 12:44:37 PM PDT 24
Peak memory 195748 kb
Host smart-4a1047cf-6625-4f78-8fd6-ec088030fde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502632081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3502632081
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3995262097
Short name T168
Test name
Test status
Simulation time 90435614 ps
CPU time 0.99 seconds
Started Jun 06 12:44:38 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 195932 kb
Host smart-842c967b-c57d-4066-9d9e-8773561ff111
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995262097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3995262097
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2938427102
Short name T594
Test name
Test status
Simulation time 148893662 ps
CPU time 2.57 seconds
Started Jun 06 12:44:50 PM PDT 24
Finished Jun 06 12:44:53 PM PDT 24
Peak memory 197668 kb
Host smart-73c29fd0-ec95-4de0-854e-532a5f1a57c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938427102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2938427102
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3326212081
Short name T480
Test name
Test status
Simulation time 89153709 ps
CPU time 0.92 seconds
Started Jun 06 12:44:36 PM PDT 24
Finished Jun 06 12:44:38 PM PDT 24
Peak memory 195704 kb
Host smart-36666c70-fee5-4f90-a114-04919cd340aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326212081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3326212081
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3751483728
Short name T620
Test name
Test status
Simulation time 37067735 ps
CPU time 0.93 seconds
Started Jun 06 12:44:39 PM PDT 24
Finished Jun 06 12:44:40 PM PDT 24
Peak memory 195584 kb
Host smart-cbd9fef6-75dd-487e-b2db-a0ad5f4adfc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751483728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3751483728
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3288709089
Short name T356
Test name
Test status
Simulation time 28582245584 ps
CPU time 106.75 seconds
Started Jun 06 12:44:50 PM PDT 24
Finished Jun 06 12:46:37 PM PDT 24
Peak memory 198084 kb
Host smart-d9bdd23d-91c2-45a1-9e6c-153149998731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288709089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3288709089
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3158383337
Short name T27
Test name
Test status
Simulation time 29670088083 ps
CPU time 125.71 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 198180 kb
Host smart-062860a0-e19c-46b5-8d95-05101628ae6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3158383337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3158383337
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2923833264
Short name T429
Test name
Test status
Simulation time 55196049 ps
CPU time 0.58 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:46 PM PDT 24
Peak memory 193880 kb
Host smart-c18b2513-ae7e-4100-8622-6bbe003d9874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923833264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2923833264
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1292764047
Short name T157
Test name
Test status
Simulation time 33927776 ps
CPU time 0.8 seconds
Started Jun 06 12:44:50 PM PDT 24
Finished Jun 06 12:44:51 PM PDT 24
Peak memory 195348 kb
Host smart-017e3625-7699-48c2-ae2e-a97f0d9bc072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292764047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1292764047
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1434477012
Short name T247
Test name
Test status
Simulation time 556430979 ps
CPU time 19.52 seconds
Started Jun 06 12:44:43 PM PDT 24
Finished Jun 06 12:45:03 PM PDT 24
Peak memory 198008 kb
Host smart-53a4ee6b-3a42-422d-842f-6c539c22228c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434477012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1434477012
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3813231441
Short name T155
Test name
Test status
Simulation time 138854543 ps
CPU time 0.79 seconds
Started Jun 06 12:44:46 PM PDT 24
Finished Jun 06 12:44:48 PM PDT 24
Peak memory 194780 kb
Host smart-02ed6625-3697-4230-a574-4ac3c68ba1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813231441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3813231441
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3312005559
Short name T199
Test name
Test status
Simulation time 60797798 ps
CPU time 0.96 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 195888 kb
Host smart-450f221b-4c6b-40ac-949b-c30acc2c1911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312005559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3312005559
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3369551952
Short name T346
Test name
Test status
Simulation time 344948786 ps
CPU time 3.68 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:50 PM PDT 24
Peak memory 197988 kb
Host smart-5ce0d9a0-ee65-4253-9623-cb13874510ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369551952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3369551952
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.223929017
Short name T175
Test name
Test status
Simulation time 160123986 ps
CPU time 3.05 seconds
Started Jun 06 12:44:46 PM PDT 24
Finished Jun 06 12:44:50 PM PDT 24
Peak memory 195728 kb
Host smart-22d2feb6-1dbf-4946-a373-7c61d2a0b755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223929017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
223929017
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2871307
Short name T502
Test name
Test status
Simulation time 19935514 ps
CPU time 0.75 seconds
Started Jun 06 12:44:50 PM PDT 24
Finished Jun 06 12:44:51 PM PDT 24
Peak memory 194968 kb
Host smart-6ea49755-2367-4c90-b9ce-f9a96a648187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2871307
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1427891406
Short name T507
Test name
Test status
Simulation time 178749160 ps
CPU time 1.11 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 195992 kb
Host smart-5231ca5d-043c-4ac2-9e37-ca38e0b9b3f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427891406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1427891406
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.752003680
Short name T420
Test name
Test status
Simulation time 2510373236 ps
CPU time 3.35 seconds
Started Jun 06 12:44:46 PM PDT 24
Finished Jun 06 12:44:50 PM PDT 24
Peak memory 198040 kb
Host smart-e1cd984b-388d-4054-8695-b19c167b61c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752003680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.752003680
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3823227565
Short name T483
Test name
Test status
Simulation time 125194790 ps
CPU time 0.99 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 195720 kb
Host smart-9a61cebb-5bab-4a29-8d80-f783100ee345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823227565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3823227565
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2402450894
Short name T255
Test name
Test status
Simulation time 79808314 ps
CPU time 1.46 seconds
Started Jun 06 12:44:46 PM PDT 24
Finished Jun 06 12:44:48 PM PDT 24
Peak memory 196680 kb
Host smart-47dc509d-2677-42ed-85e2-a56d4a365158
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402450894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2402450894
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3904234238
Short name T440
Test name
Test status
Simulation time 39084371449 ps
CPU time 166.34 seconds
Started Jun 06 12:44:48 PM PDT 24
Finished Jun 06 12:47:35 PM PDT 24
Peak memory 198076 kb
Host smart-1347bc28-b6ab-4da8-94cf-6da0ad653d4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904234238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3904234238
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1644310234
Short name T341
Test name
Test status
Simulation time 32600877 ps
CPU time 0.55 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:54 PM PDT 24
Peak memory 193884 kb
Host smart-c249a690-1bbc-4a84-a5c3-ebbd074beb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644310234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1644310234
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1816978484
Short name T163
Test name
Test status
Simulation time 625998423 ps
CPU time 0.9 seconds
Started Jun 06 12:44:47 PM PDT 24
Finished Jun 06 12:44:48 PM PDT 24
Peak memory 195440 kb
Host smart-c223ae01-26bf-49b4-bfe4-19b3b7b94d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816978484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1816978484
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.551176567
Short name T573
Test name
Test status
Simulation time 467298903 ps
CPU time 5.87 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:52 PM PDT 24
Peak memory 196816 kb
Host smart-ecb1b74b-f287-4678-96ba-3833f4d1916e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551176567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.551176567
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4174890628
Short name T187
Test name
Test status
Simulation time 40717693 ps
CPU time 0.59 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:54 PM PDT 24
Peak memory 195192 kb
Host smart-9b9c0532-86ca-4446-bd63-83eee6fdd82a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174890628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4174890628
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.133991086
Short name T616
Test name
Test status
Simulation time 223997627 ps
CPU time 0.91 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:44:46 PM PDT 24
Peak memory 195964 kb
Host smart-7d2227d6-6274-44df-88f7-9345839b526e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133991086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.133991086
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2372567586
Short name T113
Test name
Test status
Simulation time 862641816 ps
CPU time 2.87 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 198008 kb
Host smart-daa03d71-4e48-4bf8-9446-0a0467b7e735
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372567586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2372567586
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3055525911
Short name T712
Test name
Test status
Simulation time 86465105 ps
CPU time 2.46 seconds
Started Jun 06 12:44:47 PM PDT 24
Finished Jun 06 12:44:50 PM PDT 24
Peak memory 196868 kb
Host smart-9530836c-89aa-4a3f-97cb-b813502e4b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055525911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3055525911
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.836676416
Short name T566
Test name
Test status
Simulation time 620811665 ps
CPU time 1.13 seconds
Started Jun 06 12:44:47 PM PDT 24
Finished Jun 06 12:44:49 PM PDT 24
Peak memory 195912 kb
Host smart-054018ac-7cf4-4c1e-83e6-cc273e273935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836676416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.836676416
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3767088160
Short name T357
Test name
Test status
Simulation time 95692956 ps
CPU time 0.97 seconds
Started Jun 06 12:44:46 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 196640 kb
Host smart-b9d2dc6a-b575-480c-8434-f3f14b67ff56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767088160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3767088160
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.533429366
Short name T450
Test name
Test status
Simulation time 59052056 ps
CPU time 2.75 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:48 PM PDT 24
Peak memory 197904 kb
Host smart-d1f1dc31-673e-4f89-8cac-5f19d4d440de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533429366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.533429366
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.4151367559
Short name T561
Test name
Test status
Simulation time 212737970 ps
CPU time 1.09 seconds
Started Jun 06 12:44:44 PM PDT 24
Finished Jun 06 12:44:46 PM PDT 24
Peak memory 196548 kb
Host smart-9edd5558-c14d-4744-86d2-1c273355a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151367559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.4151367559
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2343251427
Short name T230
Test name
Test status
Simulation time 74256146 ps
CPU time 1.1 seconds
Started Jun 06 12:44:45 PM PDT 24
Finished Jun 06 12:44:47 PM PDT 24
Peak memory 196424 kb
Host smart-4e13332a-f86f-4a77-913a-09ba922789ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343251427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2343251427
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3724811914
Short name T447
Test name
Test status
Simulation time 26526449366 ps
CPU time 159.82 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:47:35 PM PDT 24
Peak memory 198164 kb
Host smart-968af7f3-6d33-4fc4-8d5b-0443168daa9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724811914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3724811914
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3207780990
Short name T49
Test name
Test status
Simulation time 223667540980 ps
CPU time 1171.27 seconds
Started Jun 06 12:44:46 PM PDT 24
Finished Jun 06 01:04:18 PM PDT 24
Peak memory 198104 kb
Host smart-7f4346dc-3ed9-4c0c-8db6-a737e9535887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3207780990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3207780990
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1551978220
Short name T34
Test name
Test status
Simulation time 40664883 ps
CPU time 0.57 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 193860 kb
Host smart-5dcd99bf-dd2c-4294-8b90-5da91fc6f23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551978220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1551978220
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.918110254
Short name T200
Test name
Test status
Simulation time 24756650 ps
CPU time 0.71 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 194108 kb
Host smart-69e70d2d-3c61-4fd0-8c68-f3d1c9471bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918110254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.918110254
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2303210604
Short name T640
Test name
Test status
Simulation time 481187040 ps
CPU time 15.69 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:45:09 PM PDT 24
Peak memory 195468 kb
Host smart-35106208-fd15-4a1d-9cdc-704a3494ebda
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303210604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2303210604
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.257027548
Short name T564
Test name
Test status
Simulation time 30435213 ps
CPU time 0.69 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:55 PM PDT 24
Peak memory 194612 kb
Host smart-91a20f79-4c21-4f84-8da8-e94223947b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257027548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.257027548
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.26896413
Short name T401
Test name
Test status
Simulation time 44840937 ps
CPU time 0.66 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:54 PM PDT 24
Peak memory 194220 kb
Host smart-9263cfac-de21-41fd-aec0-a26de61b9c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.26896413
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3443928042
Short name T500
Test name
Test status
Simulation time 61470236 ps
CPU time 2.34 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 198028 kb
Host smart-10c71912-0435-4289-b3b6-bd655bbf2944
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443928042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3443928042
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2320203769
Short name T134
Test name
Test status
Simulation time 31616202 ps
CPU time 0.87 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 195160 kb
Host smart-feadb04b-8c5a-4bda-8509-0d7b0c935565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320203769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2320203769
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2165758657
Short name T338
Test name
Test status
Simulation time 109625835 ps
CPU time 0.84 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 197392 kb
Host smart-3d319879-21c7-43b7-b022-1fe2740d3c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165758657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2165758657
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3483736397
Short name T590
Test name
Test status
Simulation time 23571225 ps
CPU time 0.92 seconds
Started Jun 06 12:44:48 PM PDT 24
Finished Jun 06 12:44:49 PM PDT 24
Peak memory 196476 kb
Host smart-9ff2b6a0-3fb4-4ed3-a8b4-d9d33ff5625a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483736397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3483736397
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.246972777
Short name T344
Test name
Test status
Simulation time 260847148 ps
CPU time 1.31 seconds
Started Jun 06 12:44:58 PM PDT 24
Finished Jun 06 12:45:00 PM PDT 24
Peak memory 197516 kb
Host smart-5f1128e2-998f-4356-9d76-defe4bbb77b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246972777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.246972777
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.719988715
Short name T556
Test name
Test status
Simulation time 76604869 ps
CPU time 1.24 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:55 PM PDT 24
Peak memory 195676 kb
Host smart-65d45b24-c269-4ad1-8de5-ec125e08e1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719988715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.719988715
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3473004554
Short name T435
Test name
Test status
Simulation time 236197226 ps
CPU time 0.92 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:54 PM PDT 24
Peak memory 195744 kb
Host smart-7df3c7ec-8589-4f2b-8509-6ae1c5610ffd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473004554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3473004554
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.49263904
Short name T607
Test name
Test status
Simulation time 6894376818 ps
CPU time 195.94 seconds
Started Jun 06 12:44:57 PM PDT 24
Finished Jun 06 12:48:13 PM PDT 24
Peak memory 198120 kb
Host smart-784f82ff-5578-4a06-8468-73de4ab347e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49263904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gp
io_stress_all.49263904
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2858647136
Short name T282
Test name
Test status
Simulation time 12334162 ps
CPU time 0.57 seconds
Started Jun 06 12:44:51 PM PDT 24
Finished Jun 06 12:44:52 PM PDT 24
Peak memory 194800 kb
Host smart-44be37c9-9d9b-4b4d-be16-00d9dad1ba04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858647136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2858647136
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2232103316
Short name T550
Test name
Test status
Simulation time 31884906 ps
CPU time 0.9 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 196656 kb
Host smart-7e2233e7-3554-4b8a-b3a3-cd39768f3e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232103316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2232103316
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2797185722
Short name T253
Test name
Test status
Simulation time 594715300 ps
CPU time 20.35 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 196460 kb
Host smart-763e41d8-b8ec-40e0-a13c-1b791d102993
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797185722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2797185722
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4221221586
Short name T513
Test name
Test status
Simulation time 34885153 ps
CPU time 0.69 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 194748 kb
Host smart-fefd6e77-c870-442d-bebb-e60d1f643719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221221586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4221221586
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2184245418
Short name T229
Test name
Test status
Simulation time 74836698 ps
CPU time 1.34 seconds
Started Jun 06 12:44:58 PM PDT 24
Finished Jun 06 12:45:00 PM PDT 24
Peak memory 196920 kb
Host smart-fcbb5985-a72c-4c94-bf37-8009e6eaef0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184245418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2184245418
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1297764771
Short name T281
Test name
Test status
Simulation time 243760810 ps
CPU time 2.45 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 197956 kb
Host smart-adbab23a-5112-48a9-b1ba-eb33f30134b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297764771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1297764771
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3548348683
Short name T628
Test name
Test status
Simulation time 248149059 ps
CPU time 3.69 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:58 PM PDT 24
Peak memory 197948 kb
Host smart-53e8437e-9bc2-467b-8305-8e266e0fb378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548348683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3548348683
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2442030432
Short name T629
Test name
Test status
Simulation time 63757891 ps
CPU time 1.33 seconds
Started Jun 06 12:44:57 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 195732 kb
Host smart-cd834340-258b-4aa2-811d-a2af4d1c081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442030432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2442030432
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3757077110
Short name T292
Test name
Test status
Simulation time 249803956 ps
CPU time 1.18 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:44:55 PM PDT 24
Peak memory 196916 kb
Host smart-fe394b5c-596d-40ce-bbfc-f06714988a01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757077110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3757077110
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2164133701
Short name T467
Test name
Test status
Simulation time 563749401 ps
CPU time 3.96 seconds
Started Jun 06 12:44:54 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 197896 kb
Host smart-ccef8e06-22d0-41fa-a993-19a22276cf73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164133701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2164133701
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.112059182
Short name T114
Test name
Test status
Simulation time 176803673 ps
CPU time 1.33 seconds
Started Jun 06 12:44:57 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 196868 kb
Host smart-baa6ac8f-ab27-4d48-9609-f2b903d69fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112059182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.112059182
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3442868386
Short name T464
Test name
Test status
Simulation time 123875163 ps
CPU time 1.17 seconds
Started Jun 06 12:44:57 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 195648 kb
Host smart-90f3dcb0-d7fc-4977-94ba-9733a44601a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442868386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3442868386
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1920469384
Short name T466
Test name
Test status
Simulation time 4706821706 ps
CPU time 52.03 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:45:48 PM PDT 24
Peak memory 198036 kb
Host smart-8971d618-2d83-4f70-946f-caafd5a91e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920469384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1920469384
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.105303949
Short name T501
Test name
Test status
Simulation time 11002244 ps
CPU time 0.56 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:56 PM PDT 24
Peak memory 194520 kb
Host smart-6d81a19e-ea9f-464b-8131-ef743b6d6601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105303949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.105303949
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.653514633
Short name T569
Test name
Test status
Simulation time 28727664 ps
CPU time 0.6 seconds
Started Jun 06 12:44:56 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 194476 kb
Host smart-abf89c7b-ce83-4155-8c14-6a982831cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653514633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.653514633
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.524774943
Short name T299
Test name
Test status
Simulation time 762210391 ps
CPU time 23.6 seconds
Started Jun 06 12:44:53 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 197916 kb
Host smart-12c94ea5-b69e-4456-9258-498bf99a6df7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524774943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.524774943
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1774758154
Short name T609
Test name
Test status
Simulation time 54914831 ps
CPU time 0.87 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 195896 kb
Host smart-597c52fe-1807-47b1-bff6-35127d56d40c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774758154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1774758154
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2368757356
Short name T709
Test name
Test status
Simulation time 76883947 ps
CPU time 1.16 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 195708 kb
Host smart-eb627803-07f2-4a6f-ac0c-ef8bac4ddd4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368757356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2368757356
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2243579473
Short name T383
Test name
Test status
Simulation time 1176900085 ps
CPU time 2.51 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 198020 kb
Host smart-9bc2b8da-67ff-4b8a-b140-89d7a6ef6481
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243579473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2243579473
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.701029127
Short name T533
Test name
Test status
Simulation time 257647718 ps
CPU time 2.04 seconds
Started Jun 06 12:44:56 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 198040 kb
Host smart-eafc0006-520d-4e01-af20-2718ab790f05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701029127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
701029127
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1534784403
Short name T425
Test name
Test status
Simulation time 135018621 ps
CPU time 0.82 seconds
Started Jun 06 12:44:57 PM PDT 24
Finished Jun 06 12:44:58 PM PDT 24
Peak memory 196064 kb
Host smart-4f6b060c-f090-4011-8c2e-88e7f3cbcfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534784403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1534784403
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3772511614
Short name T574
Test name
Test status
Simulation time 38757877 ps
CPU time 0.88 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 196708 kb
Host smart-c7caae57-b545-42ee-9d5b-24949bb87cde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772511614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3772511614
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2922747725
Short name T287
Test name
Test status
Simulation time 235668459 ps
CPU time 5.51 seconds
Started Jun 06 12:44:56 PM PDT 24
Finished Jun 06 12:45:03 PM PDT 24
Peak memory 197972 kb
Host smart-4653b691-3da4-4104-afd4-18c9bf1c0df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922747725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2922747725
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1291100668
Short name T451
Test name
Test status
Simulation time 100743681 ps
CPU time 1.42 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 196152 kb
Host smart-9aa0458a-9d6f-4afa-9ef3-97096b191d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291100668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1291100668
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.134998772
Short name T335
Test name
Test status
Simulation time 116850936 ps
CPU time 1.19 seconds
Started Jun 06 12:44:57 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 196396 kb
Host smart-d7a800ff-8eac-4b86-82d6-a4046b6ca49e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134998772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.134998772
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.386390836
Short name T682
Test name
Test status
Simulation time 8160458986 ps
CPU time 109.58 seconds
Started Jun 06 12:44:52 PM PDT 24
Finished Jun 06 12:46:42 PM PDT 24
Peak memory 198092 kb
Host smart-159b8355-c2ad-4535-a94b-a51e661aad5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386390836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.386390836
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2102296277
Short name T44
Test name
Test status
Simulation time 13288975 ps
CPU time 0.56 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 193920 kb
Host smart-b32872a3-a1a1-40b9-8f37-3bace6312a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102296277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2102296277
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3480329176
Short name T183
Test name
Test status
Simulation time 148842964 ps
CPU time 0.85 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:43:24 PM PDT 24
Peak memory 195800 kb
Host smart-27b340fd-1be3-40fd-a671-ac804cb5ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480329176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3480329176
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.996517600
Short name T396
Test name
Test status
Simulation time 3259203008 ps
CPU time 19.05 seconds
Started Jun 06 12:43:28 PM PDT 24
Finished Jun 06 12:43:48 PM PDT 24
Peak memory 197004 kb
Host smart-2c67b9e3-be4c-48f8-92fc-d73d2dd62f41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996517600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.996517600
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3471967028
Short name T169
Test name
Test status
Simulation time 259730376 ps
CPU time 0.85 seconds
Started Jun 06 12:43:25 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 195964 kb
Host smart-99d5a5b8-2e4b-4be3-be19-1de48e3a3c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471967028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3471967028
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3592734372
Short name T149
Test name
Test status
Simulation time 96315993 ps
CPU time 0.9 seconds
Started Jun 06 12:43:25 PM PDT 24
Finished Jun 06 12:43:27 PM PDT 24
Peak memory 196724 kb
Host smart-3ed367cd-fe33-4687-8fae-ab40a9f35359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592734372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3592734372
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3154897181
Short name T323
Test name
Test status
Simulation time 54866222 ps
CPU time 1.22 seconds
Started Jun 06 12:43:22 PM PDT 24
Finished Jun 06 12:43:24 PM PDT 24
Peak memory 196468 kb
Host smart-2b1fe682-3ea9-4f74-b3bf-4343263367d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154897181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3154897181
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1066168692
Short name T577
Test name
Test status
Simulation time 508626206 ps
CPU time 2.87 seconds
Started Jun 06 12:43:28 PM PDT 24
Finished Jun 06 12:43:31 PM PDT 24
Peak memory 197064 kb
Host smart-3c18afd4-6b15-45ae-95cd-3b32b53f59b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066168692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1066168692
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.223268527
Short name T263
Test name
Test status
Simulation time 40541872 ps
CPU time 0.97 seconds
Started Jun 06 12:43:20 PM PDT 24
Finished Jun 06 12:43:21 PM PDT 24
Peak memory 195648 kb
Host smart-cd6b3e42-36b4-4aec-ae0d-fe8cf497206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223268527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.223268527
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2047332511
Short name T622
Test name
Test status
Simulation time 231497570 ps
CPU time 1.23 seconds
Started Jun 06 12:43:14 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 196784 kb
Host smart-9eed6dff-0414-4c58-9ae6-0f2a1c0d5605
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047332511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2047332511
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1186012679
Short name T312
Test name
Test status
Simulation time 941143144 ps
CPU time 4.28 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:30 PM PDT 24
Peak memory 197964 kb
Host smart-54f5b5bb-13ee-4521-9d40-70e4d4715699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186012679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1186012679
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.362742816
Short name T33
Test name
Test status
Simulation time 319014263 ps
CPU time 0.93 seconds
Started Jun 06 12:43:22 PM PDT 24
Finished Jun 06 12:43:24 PM PDT 24
Peak memory 214792 kb
Host smart-1e83b7a0-98d0-42d5-b856-b2b6c706a3f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362742816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.362742816
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.773411585
Short name T526
Test name
Test status
Simulation time 138690372 ps
CPU time 1.35 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 197948 kb
Host smart-1f35336e-4e67-44e4-8d0d-837fed6299de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773411585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.773411585
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3478053927
Short name T325
Test name
Test status
Simulation time 48664263 ps
CPU time 1.29 seconds
Started Jun 06 12:43:13 PM PDT 24
Finished Jun 06 12:43:16 PM PDT 24
Peak memory 196640 kb
Host smart-7ccb366c-d394-49a6-bb99-f51b73915ed7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478053927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3478053927
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2363322693
Short name T251
Test name
Test status
Simulation time 7634791469 ps
CPU time 127.84 seconds
Started Jun 06 12:43:26 PM PDT 24
Finished Jun 06 12:45:34 PM PDT 24
Peak memory 198128 kb
Host smart-cb5ae70c-77e2-43ce-8dfc-80ce40bbef0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363322693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2363322693
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1643433824
Short name T375
Test name
Test status
Simulation time 15996691 ps
CPU time 0.6 seconds
Started Jun 06 12:45:03 PM PDT 24
Finished Jun 06 12:45:04 PM PDT 24
Peak memory 193868 kb
Host smart-0488016d-e666-4663-8d84-9d378d3026ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643433824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1643433824
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2460629785
Short name T129
Test name
Test status
Simulation time 25505126 ps
CPU time 0.85 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 196088 kb
Host smart-b0989f41-a1cc-423d-be41-8cf1e5a571cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460629785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2460629785
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2021234650
Short name T514
Test name
Test status
Simulation time 262667006 ps
CPU time 3.73 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:08 PM PDT 24
Peak memory 195420 kb
Host smart-474425c2-9a56-45bd-8d90-988ac48d2cfd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021234650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2021234650
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2431465572
Short name T457
Test name
Test status
Simulation time 59300989 ps
CPU time 0.85 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:05 PM PDT 24
Peak memory 196540 kb
Host smart-54ca0734-5c4a-4ce1-898a-c3e9a08bc7fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431465572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2431465572
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3040385705
Short name T493
Test name
Test status
Simulation time 71415501 ps
CPU time 1.3 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 197096 kb
Host smart-9c2dcbdb-c890-4112-9acd-2f95fe67f81f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040385705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3040385705
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3894131794
Short name T675
Test name
Test status
Simulation time 210248608 ps
CPU time 2.98 seconds
Started Jun 06 12:45:06 PM PDT 24
Finished Jun 06 12:45:09 PM PDT 24
Peak memory 197988 kb
Host smart-fd1b4fe1-bfab-4c30-8a04-11b85f82d3d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894131794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3894131794
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1265587290
Short name T144
Test name
Test status
Simulation time 257187286 ps
CPU time 2.63 seconds
Started Jun 06 12:45:06 PM PDT 24
Finished Jun 06 12:45:09 PM PDT 24
Peak memory 195712 kb
Host smart-19e547c9-a748-441f-b8d3-1de564b98774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265587290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1265587290
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4184515749
Short name T717
Test name
Test status
Simulation time 45185474 ps
CPU time 0.75 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:05 PM PDT 24
Peak memory 195940 kb
Host smart-4c1a6ce9-bc92-4628-9c01-9460e3a37f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184515749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4184515749
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1689111147
Short name T703
Test name
Test status
Simulation time 35155017 ps
CPU time 0.87 seconds
Started Jun 06 12:45:05 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 195568 kb
Host smart-77195368-120e-4547-98af-998eaa5d3a5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689111147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1689111147
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4187236298
Short name T672
Test name
Test status
Simulation time 190753750 ps
CPU time 2.42 seconds
Started Jun 06 12:45:02 PM PDT 24
Finished Jun 06 12:45:05 PM PDT 24
Peak memory 197964 kb
Host smart-68aca847-0d27-4f79-9d61-82442ce479bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187236298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4187236298
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3523010040
Short name T551
Test name
Test status
Simulation time 39977034 ps
CPU time 1.28 seconds
Started Jun 06 12:45:15 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 195452 kb
Host smart-10b6311b-a7c2-4bb7-b580-e9331804d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523010040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3523010040
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.663048269
Short name T465
Test name
Test status
Simulation time 136208122 ps
CPU time 0.8 seconds
Started Jun 06 12:44:55 PM PDT 24
Finished Jun 06 12:44:57 PM PDT 24
Peak memory 195376 kb
Host smart-f1ed3d01-fd91-4948-bcb3-7fa35f78663d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663048269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.663048269
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.652987747
Short name T377
Test name
Test status
Simulation time 13571827971 ps
CPU time 182.23 seconds
Started Jun 06 12:45:05 PM PDT 24
Finished Jun 06 12:48:08 PM PDT 24
Peak memory 198064 kb
Host smart-3106eb22-f9b7-4e6f-ac1c-1f6a1bbadcb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652987747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.652987747
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3987746397
Short name T59
Test name
Test status
Simulation time 411502545701 ps
CPU time 1851.8 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 198168 kb
Host smart-3ee50009-0d50-4096-a346-c285d7c29c64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3987746397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3987746397
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1623920721
Short name T331
Test name
Test status
Simulation time 42756029 ps
CPU time 0.58 seconds
Started Jun 06 12:45:12 PM PDT 24
Finished Jun 06 12:45:13 PM PDT 24
Peak memory 194436 kb
Host smart-6d181e4f-7096-43f8-9fff-e8489e3ce87b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623920721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1623920721
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2394811552
Short name T600
Test name
Test status
Simulation time 57709758 ps
CPU time 0.92 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 195396 kb
Host smart-494edf87-76dd-4217-b719-ea8358c63e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394811552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2394811552
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.291270765
Short name T630
Test name
Test status
Simulation time 228220833 ps
CPU time 3.95 seconds
Started Jun 06 12:45:03 PM PDT 24
Finished Jun 06 12:45:07 PM PDT 24
Peak memory 196588 kb
Host smart-94879ebe-a2a6-4a21-913d-8543c4f43e9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291270765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.291270765
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1217410580
Short name T4
Test name
Test status
Simulation time 178388206 ps
CPU time 1.1 seconds
Started Jun 06 12:45:03 PM PDT 24
Finished Jun 06 12:45:05 PM PDT 24
Peak memory 197848 kb
Host smart-c8d28125-223c-4ee8-98f4-aef38518338e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217410580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1217410580
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.159668926
Short name T364
Test name
Test status
Simulation time 124243132 ps
CPU time 0.79 seconds
Started Jun 06 12:45:06 PM PDT 24
Finished Jun 06 12:45:07 PM PDT 24
Peak memory 195560 kb
Host smart-d61667c6-da4d-4058-bb5b-461b668edb5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159668926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.159668926
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2636953610
Short name T645
Test name
Test status
Simulation time 86295452 ps
CPU time 1.86 seconds
Started Jun 06 12:45:03 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 197912 kb
Host smart-c9fc97fe-691c-4c0a-ae0a-a9fb2d20d6e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636953610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2636953610
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1831368982
Short name T534
Test name
Test status
Simulation time 390154906 ps
CPU time 2.42 seconds
Started Jun 06 12:45:05 PM PDT 24
Finished Jun 06 12:45:08 PM PDT 24
Peak memory 196944 kb
Host smart-98c83abf-5048-4b76-91c2-114d563a1c29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831368982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1831368982
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4046261745
Short name T303
Test name
Test status
Simulation time 142112555 ps
CPU time 1.35 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 196824 kb
Host smart-a2160b87-1803-47d2-86e4-0a35c6fd34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046261745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4046261745
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2168574595
Short name T478
Test name
Test status
Simulation time 37477643 ps
CPU time 1.08 seconds
Started Jun 06 12:45:03 PM PDT 24
Finished Jun 06 12:45:05 PM PDT 24
Peak memory 196020 kb
Host smart-9c97a9c0-338b-466a-8303-33f54d0d090c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168574595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2168574595
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2442601735
Short name T17
Test name
Test status
Simulation time 104124138 ps
CPU time 4.36 seconds
Started Jun 06 12:45:03 PM PDT 24
Finished Jun 06 12:45:08 PM PDT 24
Peak memory 197908 kb
Host smart-15b25904-a43c-46c9-80da-1c5820013f55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442601735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2442601735
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1251930178
Short name T604
Test name
Test status
Simulation time 36959488 ps
CPU time 1.15 seconds
Started Jun 06 12:45:02 PM PDT 24
Finished Jun 06 12:45:04 PM PDT 24
Peak memory 195508 kb
Host smart-83dc5b81-9508-4e61-bba5-a6cbd5643d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251930178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1251930178
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.819660341
Short name T64
Test name
Test status
Simulation time 788827332 ps
CPU time 1.26 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:45:06 PM PDT 24
Peak memory 196136 kb
Host smart-97b66847-fe23-4255-bae6-b56540c51ad8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819660341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.819660341
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1625970261
Short name T290
Test name
Test status
Simulation time 6573575714 ps
CPU time 160.05 seconds
Started Jun 06 12:45:04 PM PDT 24
Finished Jun 06 12:47:45 PM PDT 24
Peak memory 198132 kb
Host smart-ea680530-1ae4-4930-89c5-87d7243aa021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625970261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1625970261
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2045242518
Short name T548
Test name
Test status
Simulation time 10660615 ps
CPU time 0.55 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 193432 kb
Host smart-cee5e6b8-9ef9-4c23-9f02-d9c5f3411f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045242518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2045242518
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1706717967
Short name T55
Test name
Test status
Simulation time 61491508 ps
CPU time 0.97 seconds
Started Jun 06 12:45:12 PM PDT 24
Finished Jun 06 12:45:14 PM PDT 24
Peak memory 195896 kb
Host smart-a7075119-0824-46eb-81c5-d5c10d887b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706717967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1706717967
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3596178120
Short name T205
Test name
Test status
Simulation time 1774785493 ps
CPU time 25.88 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:45:40 PM PDT 24
Peak memory 195428 kb
Host smart-ee2b1ca2-fc69-4703-aadc-491056e394d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596178120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3596178120
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1294798707
Short name T151
Test name
Test status
Simulation time 77331724 ps
CPU time 0.93 seconds
Started Jun 06 12:45:12 PM PDT 24
Finished Jun 06 12:45:13 PM PDT 24
Peak memory 196340 kb
Host smart-1220dd9c-1c07-443a-a3f0-7bda2bd53070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294798707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1294798707
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3091217825
Short name T343
Test name
Test status
Simulation time 98600018 ps
CPU time 0.69 seconds
Started Jun 06 12:45:15 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 195456 kb
Host smart-41cde091-98c9-4437-b8b4-be746b85cdb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091217825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3091217825
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2244513898
Short name T381
Test name
Test status
Simulation time 318300543 ps
CPU time 3.48 seconds
Started Jun 06 12:45:16 PM PDT 24
Finished Jun 06 12:45:20 PM PDT 24
Peak memory 198080 kb
Host smart-f24b82e8-f1c6-4798-9719-e1efd5e0436b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244513898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2244513898
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1747296348
Short name T238
Test name
Test status
Simulation time 231305754 ps
CPU time 2.49 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 197956 kb
Host smart-e09812f5-e392-4fcd-92dd-51f99cfa32c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747296348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1747296348
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1749143512
Short name T403
Test name
Test status
Simulation time 68822038 ps
CPU time 1.14 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 195912 kb
Host smart-91ca4bb2-3127-4e83-8063-8f2e2f470289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749143512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1749143512
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1543731779
Short name T65
Test name
Test status
Simulation time 16904459 ps
CPU time 0.8 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 196068 kb
Host smart-eb047d4e-74ff-4222-95af-cf8e14f926d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543731779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1543731779
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3957954950
Short name T10
Test name
Test status
Simulation time 1291321840 ps
CPU time 2.17 seconds
Started Jun 06 12:45:19 PM PDT 24
Finished Jun 06 12:45:22 PM PDT 24
Peak memory 197836 kb
Host smart-3dbd0d6e-c932-4421-9cd9-c0a123cebac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957954950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3957954950
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2456435406
Short name T446
Test name
Test status
Simulation time 63083303 ps
CPU time 1.26 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 196444 kb
Host smart-2fda655f-b308-4b06-852a-a0f4ba767814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456435406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2456435406
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1265845716
Short name T610
Test name
Test status
Simulation time 101742888 ps
CPU time 0.75 seconds
Started Jun 06 12:45:19 PM PDT 24
Finished Jun 06 12:45:20 PM PDT 24
Peak memory 195232 kb
Host smart-8be029b4-8417-4518-8c7b-d2af55500066
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265845716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1265845716
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4027469966
Short name T327
Test name
Test status
Simulation time 4252626640 ps
CPU time 54.45 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:46:09 PM PDT 24
Peak memory 198160 kb
Host smart-2ff5feec-f454-4719-9475-55dfccd728e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027469966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4027469966
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.172140480
Short name T581
Test name
Test status
Simulation time 12756090 ps
CPU time 0.58 seconds
Started Jun 06 12:45:17 PM PDT 24
Finished Jun 06 12:45:18 PM PDT 24
Peak memory 193876 kb
Host smart-2e86aa99-1821-499b-a5d0-1d895923b722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172140480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.172140480
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1702025112
Short name T218
Test name
Test status
Simulation time 51717229 ps
CPU time 0.9 seconds
Started Jun 06 12:45:12 PM PDT 24
Finished Jun 06 12:45:14 PM PDT 24
Peak memory 197020 kb
Host smart-0267b555-8ddf-4f5f-b9cd-9a5463c95c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702025112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1702025112
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1242113371
Short name T297
Test name
Test status
Simulation time 3036320117 ps
CPU time 18.4 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:45:32 PM PDT 24
Peak memory 196856 kb
Host smart-abc53c40-8cb4-4036-8afc-1b8c91b34eb0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242113371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1242113371
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1295938794
Short name T623
Test name
Test status
Simulation time 575727879 ps
CPU time 1 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 196492 kb
Host smart-dcf1735f-c403-4d35-b544-600e2ac38d63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295938794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1295938794
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3810606322
Short name T490
Test name
Test status
Simulation time 49845519 ps
CPU time 0.69 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 194248 kb
Host smart-accada3a-4ff7-48e3-8193-9257b33cb02e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810606322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3810606322
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1290786551
Short name T308
Test name
Test status
Simulation time 126447224 ps
CPU time 2.67 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 198000 kb
Host smart-c22cbb8f-da19-486c-8ec6-4bbf5daf1ad1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290786551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1290786551
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.4023280734
Short name T654
Test name
Test status
Simulation time 169409657 ps
CPU time 1.29 seconds
Started Jun 06 12:45:17 PM PDT 24
Finished Jun 06 12:45:19 PM PDT 24
Peak memory 195760 kb
Host smart-da95a1e8-4e89-46bf-a340-70f5fc87be0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023280734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.4023280734
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3720657515
Short name T612
Test name
Test status
Simulation time 33158301 ps
CPU time 0.75 seconds
Started Jun 06 12:45:14 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 195384 kb
Host smart-7ad074f0-6cef-43b5-b32e-4e4174ad40e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720657515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3720657515
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1757177164
Short name T639
Test name
Test status
Simulation time 60997516 ps
CPU time 1.35 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 196896 kb
Host smart-f1454e69-af4f-400d-82c2-c26885ae360d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757177164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1757177164
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3119469852
Short name T370
Test name
Test status
Simulation time 660287174 ps
CPU time 2.29 seconds
Started Jun 06 12:45:12 PM PDT 24
Finished Jun 06 12:45:16 PM PDT 24
Peak memory 197928 kb
Host smart-61858494-55ed-4747-839c-a941d8ec4b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119469852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3119469852
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3087689621
Short name T398
Test name
Test status
Simulation time 178017929 ps
CPU time 0.97 seconds
Started Jun 06 12:45:18 PM PDT 24
Finished Jun 06 12:45:20 PM PDT 24
Peak memory 195492 kb
Host smart-5dfecdbc-feeb-4061-b03f-7bc990d1f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087689621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3087689621
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1129687798
Short name T392
Test name
Test status
Simulation time 28280570 ps
CPU time 0.81 seconds
Started Jun 06 12:45:19 PM PDT 24
Finished Jun 06 12:45:21 PM PDT 24
Peak memory 195292 kb
Host smart-2bd6cd07-b2a4-4cd4-af5d-c25a6553776d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129687798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1129687798
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1120930855
Short name T369
Test name
Test status
Simulation time 12604769278 ps
CPU time 114.81 seconds
Started Jun 06 12:45:19 PM PDT 24
Finished Jun 06 12:47:15 PM PDT 24
Peak memory 198072 kb
Host smart-71319dbc-2a9f-42f4-96dc-959739554eb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120930855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1120930855
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2228816787
Short name T242
Test name
Test status
Simulation time 14373488 ps
CPU time 0.58 seconds
Started Jun 06 12:45:22 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 194000 kb
Host smart-3ef76127-918d-4334-acc9-66ecd7f068de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228816787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2228816787
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1245693342
Short name T271
Test name
Test status
Simulation time 128050325 ps
CPU time 0.79 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:45:23 PM PDT 24
Peak memory 195388 kb
Host smart-1422560a-40ef-4e0c-ad8f-6468a1fa68a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245693342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1245693342
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.141065728
Short name T565
Test name
Test status
Simulation time 1020890167 ps
CPU time 13.14 seconds
Started Jun 06 12:45:20 PM PDT 24
Finished Jun 06 12:45:34 PM PDT 24
Peak memory 196944 kb
Host smart-194ff335-9e53-4c41-8a8d-936a028078c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141065728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.141065728
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1968509551
Short name T524
Test name
Test status
Simulation time 297810205 ps
CPU time 1.04 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:25 PM PDT 24
Peak memory 198012 kb
Host smart-81763795-a89d-4b03-aad1-05418520e65e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968509551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1968509551
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.4164306581
Short name T365
Test name
Test status
Simulation time 126848102 ps
CPU time 1.18 seconds
Started Jun 06 12:45:24 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 196568 kb
Host smart-a4f2f4cf-aeac-4a8d-8cab-df3c61079f29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164306581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.4164306581
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1321018388
Short name T644
Test name
Test status
Simulation time 254941543 ps
CPU time 2.36 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 196348 kb
Host smart-ad181cc5-8a1c-40d1-b391-1871cf5e80e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321018388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1321018388
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.177894883
Short name T289
Test name
Test status
Simulation time 376720622 ps
CPU time 2.36 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 197112 kb
Host smart-96847685-822c-4bdc-b563-5d97e2aa5fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177894883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
177894883
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.230526915
Short name T135
Test name
Test status
Simulation time 54853206 ps
CPU time 0.63 seconds
Started Jun 06 12:45:13 PM PDT 24
Finished Jun 06 12:45:15 PM PDT 24
Peak memory 194920 kb
Host smart-e7bab0b8-024f-4cf8-a292-9689171561e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230526915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.230526915
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.618068928
Short name T431
Test name
Test status
Simulation time 84810986 ps
CPU time 0.91 seconds
Started Jun 06 12:45:11 PM PDT 24
Finished Jun 06 12:45:13 PM PDT 24
Peak memory 196444 kb
Host smart-9afd9dd2-9899-4934-aaf3-0b9166358164
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618068928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.618068928
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.705180115
Short name T246
Test name
Test status
Simulation time 28219504 ps
CPU time 1.19 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:25 PM PDT 24
Peak memory 197828 kb
Host smart-987589bf-e8b8-4868-aefd-fdb9c028642e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705180115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.705180115
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.498937637
Short name T678
Test name
Test status
Simulation time 144367908 ps
CPU time 1.27 seconds
Started Jun 06 12:45:15 PM PDT 24
Finished Jun 06 12:45:17 PM PDT 24
Peak memory 195528 kb
Host smart-63413f8b-34ca-4b20-bec9-cd235a66bf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498937637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.498937637
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2994636425
Short name T578
Test name
Test status
Simulation time 188161976 ps
CPU time 1.24 seconds
Started Jun 06 12:45:16 PM PDT 24
Finished Jun 06 12:45:18 PM PDT 24
Peak memory 196352 kb
Host smart-70f63db6-ceb8-48b2-992e-be04007a26ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994636425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2994636425
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1936281098
Short name T66
Test name
Test status
Simulation time 31647262206 ps
CPU time 225.54 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:49:07 PM PDT 24
Peak memory 198172 kb
Host smart-dbcf557b-6f05-40dd-adb3-244e22da89c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936281098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1936281098
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2775409446
Short name T711
Test name
Test status
Simulation time 244888263796 ps
CPU time 1636.76 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 198208 kb
Host smart-20b7ba80-6a3f-40a6-a0f3-ea29e34f6773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2775409446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2775409446
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2913475546
Short name T36
Test name
Test status
Simulation time 14325013 ps
CPU time 0.61 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 193772 kb
Host smart-bb436683-39e3-49ea-97bc-1a303f4958c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913475546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2913475546
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3295335549
Short name T691
Test name
Test status
Simulation time 23102227 ps
CPU time 0.62 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 194812 kb
Host smart-2d80458c-0b9c-4b12-b704-3d8ccb77f2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295335549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3295335549
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.962451896
Short name T355
Test name
Test status
Simulation time 537631523 ps
CPU time 26.99 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:45:49 PM PDT 24
Peak memory 198024 kb
Host smart-5303cf87-b7de-4031-8ac9-ca30e14a6254
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962451896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.962451896
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.228309736
Short name T461
Test name
Test status
Simulation time 55220661 ps
CPU time 0.87 seconds
Started Jun 06 12:45:22 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 195952 kb
Host smart-17e6e1a8-b383-4735-9124-bb828dbef718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228309736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.228309736
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1963457086
Short name T161
Test name
Test status
Simulation time 37277673 ps
CPU time 1.1 seconds
Started Jun 06 12:45:22 PM PDT 24
Finished Jun 06 12:45:24 PM PDT 24
Peak memory 196008 kb
Host smart-7f40601c-be50-40cd-99fd-05a6e1587a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963457086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1963457086
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1585338069
Short name T211
Test name
Test status
Simulation time 102452489 ps
CPU time 2.97 seconds
Started Jun 06 12:45:22 PM PDT 24
Finished Jun 06 12:45:25 PM PDT 24
Peak memory 197936 kb
Host smart-5f33fa13-d7f6-440e-b732-2f2c225c3478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585338069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1585338069
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.995744730
Short name T593
Test name
Test status
Simulation time 56113638 ps
CPU time 1.24 seconds
Started Jun 06 12:45:20 PM PDT 24
Finished Jun 06 12:45:22 PM PDT 24
Peak memory 196464 kb
Host smart-2545c03e-e6ce-40e0-91e1-cdf0a1adc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995744730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.995744730
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1813937201
Short name T54
Test name
Test status
Simulation time 34441415 ps
CPU time 1.33 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:25 PM PDT 24
Peak memory 197000 kb
Host smart-f7d5a47f-2048-4650-bb68-661b16dafe5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813937201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1813937201
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4173892448
Short name T572
Test name
Test status
Simulation time 3923749490 ps
CPU time 4.78 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:28 PM PDT 24
Peak memory 198096 kb
Host smart-63d041a6-0301-43fd-bf93-606de086ba83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173892448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4173892448
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2812437662
Short name T118
Test name
Test status
Simulation time 70150549 ps
CPU time 1.44 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:25 PM PDT 24
Peak memory 196752 kb
Host smart-2c97fa36-1ecf-48d2-ad7d-0845ceb65491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812437662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2812437662
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2395345251
Short name T423
Test name
Test status
Simulation time 45205857 ps
CPU time 0.87 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:45:23 PM PDT 24
Peak memory 196388 kb
Host smart-a41f8585-ba91-40c8-9a26-f88745c1091d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395345251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2395345251
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.29671363
Short name T468
Test name
Test status
Simulation time 2935233879 ps
CPU time 41.7 seconds
Started Jun 06 12:45:21 PM PDT 24
Finished Jun 06 12:46:04 PM PDT 24
Peak memory 198132 kb
Host smart-ae30e4ad-0d53-48e9-b3ab-0224f8fd0345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29671363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gp
io_stress_all.29671363
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.4154098362
Short name T683
Test name
Test status
Simulation time 71984411148 ps
CPU time 1720.26 seconds
Started Jun 06 12:45:22 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 198112 kb
Host smart-99aaa284-fc8c-47bf-9b15-a64d486ad635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4154098362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.4154098362
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1923563930
Short name T336
Test name
Test status
Simulation time 13508952 ps
CPU time 0.59 seconds
Started Jun 06 12:45:31 PM PDT 24
Finished Jun 06 12:45:32 PM PDT 24
Peak memory 193404 kb
Host smart-fcb09a65-a506-4609-83b8-dcb821678aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923563930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1923563930
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1646428469
Short name T571
Test name
Test status
Simulation time 49831982 ps
CPU time 0.96 seconds
Started Jun 06 12:45:24 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 196552 kb
Host smart-671d5f35-8f00-4192-90dc-b1afe79b9fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646428469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1646428469
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1161398617
Short name T210
Test name
Test status
Simulation time 4606877021 ps
CPU time 22.19 seconds
Started Jun 06 12:45:31 PM PDT 24
Finished Jun 06 12:45:54 PM PDT 24
Peak memory 196976 kb
Host smart-5905910f-1139-4af9-bf09-b32c53b57ee9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161398617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1161398617
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2943825958
Short name T626
Test name
Test status
Simulation time 27366361 ps
CPU time 0.66 seconds
Started Jun 06 12:45:33 PM PDT 24
Finished Jun 06 12:45:34 PM PDT 24
Peak memory 194708 kb
Host smart-512bd68c-3599-4dae-af68-59a5d74f4494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943825958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2943825958
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3040516307
Short name T422
Test name
Test status
Simulation time 141257695 ps
CPU time 1.32 seconds
Started Jun 06 12:45:24 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 196884 kb
Host smart-8901678a-20d8-4e78-9416-2e9f7ef8e198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040516307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3040516307
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.601131608
Short name T413
Test name
Test status
Simulation time 117477539 ps
CPU time 1.31 seconds
Started Jun 06 12:45:32 PM PDT 24
Finished Jun 06 12:45:34 PM PDT 24
Peak memory 197884 kb
Host smart-f0886828-78f4-4168-b77a-aef4cc1cf173
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601131608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.601131608
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1089021373
Short name T202
Test name
Test status
Simulation time 656811767 ps
CPU time 2.36 seconds
Started Jun 06 12:45:32 PM PDT 24
Finished Jun 06 12:45:35 PM PDT 24
Peak memory 195828 kb
Host smart-67afab13-b03f-4545-a09b-6b3977dc2779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089021373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1089021373
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.266761842
Short name T472
Test name
Test status
Simulation time 75925398 ps
CPU time 0.96 seconds
Started Jun 06 12:45:24 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 195936 kb
Host smart-082b1c00-4dcc-4f1d-84d4-56cbfe083668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266761842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.266761842
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3361593821
Short name T143
Test name
Test status
Simulation time 149312521 ps
CPU time 0.86 seconds
Started Jun 06 12:45:24 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 195372 kb
Host smart-f173d8d6-d777-47c9-b80d-0f78c1960fd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361593821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3361593821
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.454942759
Short name T207
Test name
Test status
Simulation time 1131913701 ps
CPU time 5.41 seconds
Started Jun 06 12:45:30 PM PDT 24
Finished Jun 06 12:45:36 PM PDT 24
Peak memory 197732 kb
Host smart-77f9e112-d018-43be-9d8b-dfe0e60ded75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454942759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.454942759
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1021605009
Short name T671
Test name
Test status
Simulation time 64768853 ps
CPU time 1.25 seconds
Started Jun 06 12:45:24 PM PDT 24
Finished Jun 06 12:45:26 PM PDT 24
Peak memory 196552 kb
Host smart-b978f763-0256-495f-b453-ca13dbe455fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021605009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1021605009
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1741507926
Short name T233
Test name
Test status
Simulation time 336204829 ps
CPU time 1.31 seconds
Started Jun 06 12:45:23 PM PDT 24
Finished Jun 06 12:45:25 PM PDT 24
Peak memory 195500 kb
Host smart-343d99fe-ad56-480c-9440-0dd4985f31d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741507926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1741507926
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2630681543
Short name T510
Test name
Test status
Simulation time 20948254233 ps
CPU time 120.29 seconds
Started Jun 06 12:45:36 PM PDT 24
Finished Jun 06 12:47:37 PM PDT 24
Peak memory 198188 kb
Host smart-b274cc52-4189-4761-9f2c-d47c29ffe13e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630681543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2630681543
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1483940017
Short name T217
Test name
Test status
Simulation time 63658833 ps
CPU time 0.58 seconds
Started Jun 06 12:45:32 PM PDT 24
Finished Jun 06 12:45:34 PM PDT 24
Peak memory 194088 kb
Host smart-1c59197a-de24-4085-b20a-af84b5d18a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483940017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1483940017
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3740972266
Short name T352
Test name
Test status
Simulation time 94318557 ps
CPU time 0.66 seconds
Started Jun 06 12:45:35 PM PDT 24
Finished Jun 06 12:45:36 PM PDT 24
Peak memory 194044 kb
Host smart-55c4bdfc-a7a6-4f2b-8653-981e25cec902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740972266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3740972266
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2776161257
Short name T286
Test name
Test status
Simulation time 371958037 ps
CPU time 11.39 seconds
Started Jun 06 12:45:30 PM PDT 24
Finished Jun 06 12:45:42 PM PDT 24
Peak memory 197904 kb
Host smart-e9e03c39-b8d0-42cb-8b8f-42def20fd4be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776161257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2776161257
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1410577129
Short name T305
Test name
Test status
Simulation time 355614809 ps
CPU time 1.17 seconds
Started Jun 06 12:45:35 PM PDT 24
Finished Jun 06 12:45:37 PM PDT 24
Peak memory 196660 kb
Host smart-6e5d380a-5748-4402-8dfa-a9fa54d15955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410577129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1410577129
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3386687350
Short name T167
Test name
Test status
Simulation time 87601094 ps
CPU time 1.36 seconds
Started Jun 06 12:45:30 PM PDT 24
Finished Jun 06 12:45:32 PM PDT 24
Peak memory 196828 kb
Host smart-9887fcdc-1c27-4974-9409-87799d5ed377
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386687350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3386687350
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2624269152
Short name T176
Test name
Test status
Simulation time 132503952 ps
CPU time 1.49 seconds
Started Jun 06 12:45:35 PM PDT 24
Finished Jun 06 12:45:37 PM PDT 24
Peak memory 197976 kb
Host smart-c3122bf8-2b39-4f64-b175-90c5168b2677
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624269152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2624269152
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1575053305
Short name T596
Test name
Test status
Simulation time 134982871 ps
CPU time 1.01 seconds
Started Jun 06 12:45:31 PM PDT 24
Finished Jun 06 12:45:33 PM PDT 24
Peak memory 195624 kb
Host smart-ebdec8c8-dcdd-4bd1-879a-813ae4a59a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575053305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1575053305
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2284725813
Short name T482
Test name
Test status
Simulation time 51397633 ps
CPU time 1.22 seconds
Started Jun 06 12:45:32 PM PDT 24
Finished Jun 06 12:45:34 PM PDT 24
Peak memory 197068 kb
Host smart-4d592228-e460-4e4b-97eb-c00705770888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284725813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2284725813
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4040282818
Short name T531
Test name
Test status
Simulation time 55879827 ps
CPU time 0.65 seconds
Started Jun 06 12:45:36 PM PDT 24
Finished Jun 06 12:45:37 PM PDT 24
Peak memory 195008 kb
Host smart-34a10336-2a0a-47c8-9c7e-98adb8bbdd44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040282818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4040282818
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3269137229
Short name T258
Test name
Test status
Simulation time 185140112 ps
CPU time 4.27 seconds
Started Jun 06 12:45:32 PM PDT 24
Finished Jun 06 12:45:37 PM PDT 24
Peak memory 197916 kb
Host smart-e3ec004f-df76-400f-8d6f-378bb988ae7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269137229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3269137229
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.4125751919
Short name T159
Test name
Test status
Simulation time 243774170 ps
CPU time 1 seconds
Started Jun 06 12:45:34 PM PDT 24
Finished Jun 06 12:45:35 PM PDT 24
Peak memory 195528 kb
Host smart-94e88372-a2de-4349-8896-194b53f39dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125751919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.4125751919
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2208543776
Short name T367
Test name
Test status
Simulation time 238365335 ps
CPU time 1.22 seconds
Started Jun 06 12:45:33 PM PDT 24
Finished Jun 06 12:45:35 PM PDT 24
Peak memory 195736 kb
Host smart-c9087032-b351-4f49-a367-429359b08290
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208543776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2208543776
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2260316996
Short name T307
Test name
Test status
Simulation time 43310514953 ps
CPU time 150.01 seconds
Started Jun 06 12:45:34 PM PDT 24
Finished Jun 06 12:48:04 PM PDT 24
Peak memory 198192 kb
Host smart-b40a24ce-0ea4-4ac0-87ea-37d897cec9c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260316996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2260316996
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2742167532
Short name T254
Test name
Test status
Simulation time 67809949 ps
CPU time 0.58 seconds
Started Jun 06 12:45:42 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 194064 kb
Host smart-ea13b933-32da-4514-b993-7e02004013ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742167532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2742167532
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1658347641
Short name T363
Test name
Test status
Simulation time 46568908 ps
CPU time 0.97 seconds
Started Jun 06 12:45:31 PM PDT 24
Finished Jun 06 12:45:33 PM PDT 24
Peak memory 195884 kb
Host smart-0da88349-6700-47d2-bc1c-13d46961e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658347641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1658347641
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4124239024
Short name T586
Test name
Test status
Simulation time 534433374 ps
CPU time 26.02 seconds
Started Jun 06 12:45:34 PM PDT 24
Finished Jun 06 12:46:01 PM PDT 24
Peak memory 195464 kb
Host smart-cfd8b2ff-6512-4cc7-961d-6326876fafa9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124239024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4124239024
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1761802238
Short name T658
Test name
Test status
Simulation time 42523810 ps
CPU time 0.69 seconds
Started Jun 06 12:45:34 PM PDT 24
Finished Jun 06 12:45:36 PM PDT 24
Peak memory 195080 kb
Host smart-dd9d2695-176a-4ead-883a-f9da765d2fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761802238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1761802238
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.422655150
Short name T374
Test name
Test status
Simulation time 165184292 ps
CPU time 1.01 seconds
Started Jun 06 12:45:31 PM PDT 24
Finished Jun 06 12:45:33 PM PDT 24
Peak memory 197364 kb
Host smart-d2cdd98c-cad2-46e9-b2f9-1918a4631af5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422655150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.422655150
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.327272950
Short name T438
Test name
Test status
Simulation time 139276518 ps
CPU time 2.56 seconds
Started Jun 06 12:45:57 PM PDT 24
Finished Jun 06 12:46:00 PM PDT 24
Peak memory 197172 kb
Host smart-eb079ba1-1c88-470c-93c9-4764b8072e44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327272950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
327272950
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3216132147
Short name T603
Test name
Test status
Simulation time 102833820 ps
CPU time 0.81 seconds
Started Jun 06 12:45:30 PM PDT 24
Finished Jun 06 12:45:31 PM PDT 24
Peak memory 196152 kb
Host smart-a635a6b8-88e8-41cb-8436-e0f211926651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216132147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3216132147
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1161180072
Short name T351
Test name
Test status
Simulation time 146778515 ps
CPU time 0.86 seconds
Started Jun 06 12:45:31 PM PDT 24
Finished Jun 06 12:45:32 PM PDT 24
Peak memory 196480 kb
Host smart-272982d1-03f3-44c7-b39c-1d46ed830dbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161180072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1161180072
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.299779803
Short name T407
Test name
Test status
Simulation time 199678578 ps
CPU time 1.95 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 197904 kb
Host smart-79ef75c2-bed8-401d-bbbc-a26087c49fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299779803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.299779803
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.83115328
Short name T563
Test name
Test status
Simulation time 173746222 ps
CPU time 1.03 seconds
Started Jun 06 12:45:35 PM PDT 24
Finished Jun 06 12:45:37 PM PDT 24
Peak memory 195424 kb
Host smart-67cd5634-1b83-4412-96c9-17f2fae7b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83115328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.83115328
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1830205084
Short name T442
Test name
Test status
Simulation time 36989343 ps
CPU time 0.9 seconds
Started Jun 06 12:45:41 PM PDT 24
Finished Jun 06 12:45:43 PM PDT 24
Peak memory 195552 kb
Host smart-5c070191-24cb-4336-a820-ec1e32f02a91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830205084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1830205084
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1859012768
Short name T304
Test name
Test status
Simulation time 14245821 ps
CPU time 0.58 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 194020 kb
Host smart-8190f82b-9dc6-4ad8-941e-31cb52e02ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859012768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1859012768
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4168327846
Short name T276
Test name
Test status
Simulation time 25732894 ps
CPU time 0.79 seconds
Started Jun 06 12:45:41 PM PDT 24
Finished Jun 06 12:45:43 PM PDT 24
Peak memory 195496 kb
Host smart-66a7fb6e-6617-4bab-a9bf-6d4da3d48463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168327846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4168327846
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2368914864
Short name T270
Test name
Test status
Simulation time 717347504 ps
CPU time 12.46 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:57 PM PDT 24
Peak memory 196904 kb
Host smart-b79b3797-6df7-4f37-9adc-e232a89cf26e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368914864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2368914864
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.765959221
Short name T608
Test name
Test status
Simulation time 135630066 ps
CPU time 0.75 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:45 PM PDT 24
Peak memory 195744 kb
Host smart-528d7a24-6b2d-4e02-9ab2-1d3396648a48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765959221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.765959221
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3665712618
Short name T216
Test name
Test status
Simulation time 300793518 ps
CPU time 0.93 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:45 PM PDT 24
Peak memory 195952 kb
Host smart-60214857-2b29-4965-bf10-50ea7815c2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665712618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3665712618
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2393161641
Short name T52
Test name
Test status
Simulation time 291069629 ps
CPU time 3.38 seconds
Started Jun 06 12:45:46 PM PDT 24
Finished Jun 06 12:45:50 PM PDT 24
Peak memory 197972 kb
Host smart-e919410f-0330-43ec-b9b0-e5b2d52064f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393161641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2393161641
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.837951839
Short name T209
Test name
Test status
Simulation time 492232857 ps
CPU time 3.74 seconds
Started Jun 06 12:45:41 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 197984 kb
Host smart-76073c82-e33b-4bb4-a5be-10548bc88484
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837951839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
837951839
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1391963127
Short name T588
Test name
Test status
Simulation time 42444187 ps
CPU time 1.02 seconds
Started Jun 06 12:45:49 PM PDT 24
Finished Jun 06 12:45:50 PM PDT 24
Peak memory 196324 kb
Host smart-f9143c67-b37a-4ea1-ab9a-2c91e827362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391963127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1391963127
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1999670289
Short name T145
Test name
Test status
Simulation time 64229920 ps
CPU time 1.01 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:45 PM PDT 24
Peak memory 196760 kb
Host smart-cc1f2150-e84c-474d-bd22-b49a6bf0fc02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999670289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1999670289
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4035962322
Short name T419
Test name
Test status
Simulation time 178442339 ps
CPU time 1.35 seconds
Started Jun 06 12:45:58 PM PDT 24
Finished Jun 06 12:46:00 PM PDT 24
Peak memory 197992 kb
Host smart-eb0142e6-3876-412f-bc52-f6f88c92aa2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035962322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4035962322
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.906742141
Short name T508
Test name
Test status
Simulation time 119127670 ps
CPU time 1.17 seconds
Started Jun 06 12:45:49 PM PDT 24
Finished Jun 06 12:45:51 PM PDT 24
Peak memory 196420 kb
Host smart-98dd03b2-4c01-488f-99f0-c45acc1ebcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906742141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.906742141
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.4034834956
Short name T259
Test name
Test status
Simulation time 331957517 ps
CPU time 1.41 seconds
Started Jun 06 12:45:45 PM PDT 24
Finished Jun 06 12:45:47 PM PDT 24
Peak memory 196752 kb
Host smart-3228f30f-b304-4f56-96bc-a9cc8050d587
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034834956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.4034834956
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3338814883
Short name T385
Test name
Test status
Simulation time 19610164974 ps
CPU time 130.79 seconds
Started Jun 06 12:45:42 PM PDT 24
Finished Jun 06 12:47:54 PM PDT 24
Peak memory 198096 kb
Host smart-cc1f5022-3fba-4e54-a468-444a5d23f659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338814883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3338814883
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2474530789
Short name T48
Test name
Test status
Simulation time 49695131 ps
CPU time 0.55 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 194608 kb
Host smart-406dd2d0-d7a8-4acc-8814-e5c3e4e886fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474530789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2474530789
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2629945867
Short name T173
Test name
Test status
Simulation time 50271865 ps
CPU time 0.89 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 196656 kb
Host smart-ffa68998-8295-47be-bf23-f3b8bfefc6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629945867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2629945867
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1169940560
Short name T244
Test name
Test status
Simulation time 305334908 ps
CPU time 10.08 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:43:38 PM PDT 24
Peak memory 196876 kb
Host smart-0581f8dd-71d0-4646-bae4-53d4b809722e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169940560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1169940560
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1112435956
Short name T445
Test name
Test status
Simulation time 142638530 ps
CPU time 0.73 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 195812 kb
Host smart-b1fd77ec-3a56-43c2-afbe-445328e1973c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112435956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1112435956
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.904752810
Short name T333
Test name
Test status
Simulation time 44845367 ps
CPU time 0.96 seconds
Started Jun 06 12:43:22 PM PDT 24
Finished Jun 06 12:43:24 PM PDT 24
Peak memory 196860 kb
Host smart-5bf54664-d043-47cd-8080-6492a6577f97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904752810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.904752810
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3173465800
Short name T261
Test name
Test status
Simulation time 160151995 ps
CPU time 1.42 seconds
Started Jun 06 12:43:35 PM PDT 24
Finished Jun 06 12:43:38 PM PDT 24
Peak memory 196256 kb
Host smart-3698eb15-f807-4977-a7d7-3d37f33e719f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173465800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3173465800
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3785196609
Short name T605
Test name
Test status
Simulation time 123677405 ps
CPU time 3.68 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:28 PM PDT 24
Peak memory 195824 kb
Host smart-d96f5eab-6df7-4e38-be5e-7f8a6d450ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785196609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3785196609
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3957135916
Short name T182
Test name
Test status
Simulation time 19462353 ps
CPU time 0.77 seconds
Started Jun 06 12:43:21 PM PDT 24
Finished Jun 06 12:43:22 PM PDT 24
Peak memory 195324 kb
Host smart-b88a3510-cd49-42ac-b3f7-d2db1b3e0222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957135916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3957135916
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2280261396
Short name T190
Test name
Test status
Simulation time 29037782 ps
CPU time 0.71 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:25 PM PDT 24
Peak memory 195380 kb
Host smart-3477f0a6-5de4-421e-acb6-7ff1e42ef220
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280261396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2280261396
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1995602446
Short name T53
Test name
Test status
Simulation time 157487373 ps
CPU time 3.71 seconds
Started Jun 06 12:43:21 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 197904 kb
Host smart-eb1c33f9-74a8-4fa6-aa7c-a80b6812eef8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995602446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1995602446
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.307123485
Short name T46
Test name
Test status
Simulation time 56566640 ps
CPU time 0.89 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:43:28 PM PDT 24
Peak memory 213788 kb
Host smart-17cdece2-eed4-45dc-bff2-68ae0a03b1c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307123485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.307123485
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2614217618
Short name T309
Test name
Test status
Simulation time 217575992 ps
CPU time 1.42 seconds
Started Jun 06 12:43:22 PM PDT 24
Finished Jun 06 12:43:24 PM PDT 24
Peak memory 195456 kb
Host smart-d6423ff9-f66f-42a8-90d8-df3c26a76067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614217618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2614217618
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.787922233
Short name T334
Test name
Test status
Simulation time 37253325 ps
CPU time 0.8 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 195344 kb
Host smart-18211658-5ef0-40ae-bb21-67cb0dbb136e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787922233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.787922233
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1758924368
Short name T693
Test name
Test status
Simulation time 18790890346 ps
CPU time 210.26 seconds
Started Jun 06 12:43:29 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 198164 kb
Host smart-3c5612f8-63c4-43e5-8c61-5baf42622798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758924368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1758924368
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3282821527
Short name T632
Test name
Test status
Simulation time 27151200922 ps
CPU time 796.72 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:56:44 PM PDT 24
Peak memory 198204 kb
Host smart-195b5e95-f7c5-4fbd-afc2-5c85493e4708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3282821527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3282821527
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3982524147
Short name T611
Test name
Test status
Simulation time 36576876 ps
CPU time 0.58 seconds
Started Jun 06 12:45:44 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 194052 kb
Host smart-a8a3d5d0-eae6-428f-8bca-7b680530cb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982524147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3982524147
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.197328576
Short name T509
Test name
Test status
Simulation time 158670926 ps
CPU time 0.65 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 194180 kb
Host smart-12a75fd5-2874-41ea-a54b-2b6ed2774738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197328576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.197328576
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3415591914
Short name T557
Test name
Test status
Simulation time 1522449406 ps
CPU time 10.62 seconds
Started Jun 06 12:45:46 PM PDT 24
Finished Jun 06 12:45:57 PM PDT 24
Peak memory 197984 kb
Host smart-8081df62-36fe-4792-b32f-fe36f9db2da0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415591914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3415591914
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1777491749
Short name T116
Test name
Test status
Simulation time 287582690 ps
CPU time 1.17 seconds
Started Jun 06 12:45:44 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 196532 kb
Host smart-ac910273-b794-4f67-834e-4a06da94e456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777491749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1777491749
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3257465144
Short name T262
Test name
Test status
Simulation time 114072689 ps
CPU time 0.81 seconds
Started Jun 06 12:45:44 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 195424 kb
Host smart-4fa0fc9d-dcad-4935-bd1b-0eb410bb405e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257465144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3257465144
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.190018919
Short name T298
Test name
Test status
Simulation time 254838866 ps
CPU time 2.38 seconds
Started Jun 06 12:45:49 PM PDT 24
Finished Jun 06 12:45:52 PM PDT 24
Peak memory 198016 kb
Host smart-046559d0-97c0-424e-adfa-1e069780ebc0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190018919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.190018919
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.571971173
Short name T474
Test name
Test status
Simulation time 600169973 ps
CPU time 1.39 seconds
Started Jun 06 12:45:42 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 196704 kb
Host smart-694d3345-9376-40e3-81c6-257d8f41b9db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571971173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
571971173
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1677669579
Short name T22
Test name
Test status
Simulation time 135849844 ps
CPU time 0.91 seconds
Started Jun 06 12:45:46 PM PDT 24
Finished Jun 06 12:45:47 PM PDT 24
Peak memory 195892 kb
Host smart-8cf98d9a-bd4c-4989-b8f8-92b2ece4b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677669579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1677669579
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3801666205
Short name T330
Test name
Test status
Simulation time 228674131 ps
CPU time 1.05 seconds
Started Jun 06 12:45:42 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 196508 kb
Host smart-36ad467f-b863-4091-9547-c56eedba934e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801666205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3801666205
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.852648968
Short name T582
Test name
Test status
Simulation time 585474896 ps
CPU time 2.07 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:47 PM PDT 24
Peak memory 197972 kb
Host smart-7cb01d18-1988-4a47-aeda-d00619548d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852648968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.852648968
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.181117210
Short name T332
Test name
Test status
Simulation time 126155140 ps
CPU time 1.03 seconds
Started Jun 06 12:45:50 PM PDT 24
Finished Jun 06 12:45:52 PM PDT 24
Peak memory 196424 kb
Host smart-f52a5f89-441e-49be-bf14-ee193f9d7557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181117210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.181117210
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3775288890
Short name T288
Test name
Test status
Simulation time 130038043 ps
CPU time 1.04 seconds
Started Jun 06 12:45:44 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 195784 kb
Host smart-457bceb4-90f4-4eb7-b51d-53324abab08c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775288890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3775288890
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1142476247
Short name T372
Test name
Test status
Simulation time 75498241242 ps
CPU time 193.9 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:48:58 PM PDT 24
Peak memory 198128 kb
Host smart-b5bde9e2-2989-4bd5-bf17-d3245c57a494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142476247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1142476247
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2169495056
Short name T503
Test name
Test status
Simulation time 55857670 ps
CPU time 0.58 seconds
Started Jun 06 12:45:53 PM PDT 24
Finished Jun 06 12:45:54 PM PDT 24
Peak memory 194172 kb
Host smart-215f2bf7-6237-4376-bc85-adad8822ff2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169495056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2169495056
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.298876254
Short name T473
Test name
Test status
Simulation time 16208075 ps
CPU time 0.66 seconds
Started Jun 06 12:45:45 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 194752 kb
Host smart-1f7c5018-1e96-4e17-aa46-3dc841f1818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298876254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.298876254
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1658035199
Short name T119
Test name
Test status
Simulation time 546579265 ps
CPU time 8.45 seconds
Started Jun 06 12:45:45 PM PDT 24
Finished Jun 06 12:45:54 PM PDT 24
Peak memory 197060 kb
Host smart-a676d467-8dfe-4b09-9cc6-65975397a346
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658035199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1658035199
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2119288690
Short name T18
Test name
Test status
Simulation time 143747350 ps
CPU time 0.93 seconds
Started Jun 06 12:45:52 PM PDT 24
Finished Jun 06 12:45:54 PM PDT 24
Peak memory 197188 kb
Host smart-8b52780e-791f-4720-9162-1b9cd5ae490c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119288690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2119288690
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3975903802
Short name T624
Test name
Test status
Simulation time 49984125 ps
CPU time 1.26 seconds
Started Jun 06 12:45:42 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 198012 kb
Host smart-b7681672-72d1-4216-8564-a996be6e54b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975903802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3975903802
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1292290803
Short name T130
Test name
Test status
Simulation time 52123301 ps
CPU time 2.07 seconds
Started Jun 06 12:45:49 PM PDT 24
Finished Jun 06 12:45:51 PM PDT 24
Peak memory 197964 kb
Host smart-5713d274-6b53-4066-86f8-3dba57f251af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292290803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1292290803
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.940916705
Short name T690
Test name
Test status
Simulation time 121717452 ps
CPU time 2.63 seconds
Started Jun 06 12:45:49 PM PDT 24
Finished Jun 06 12:45:52 PM PDT 24
Peak memory 197240 kb
Host smart-536a02b1-8f58-4379-8b3c-2d8526cf63f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940916705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
940916705
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.8997068
Short name T720
Test name
Test status
Simulation time 15710060 ps
CPU time 0.62 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:44 PM PDT 24
Peak memory 194272 kb
Host smart-263482e7-3d26-445b-9427-8fe5d446a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8997068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.8997068
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1540401900
Short name T300
Test name
Test status
Simulation time 63419335 ps
CPU time 1.27 seconds
Started Jun 06 12:45:43 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 196088 kb
Host smart-fe02cb81-ea7e-4d92-b3c1-ca2ac96bcba3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540401900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1540401900
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3708807374
Short name T562
Test name
Test status
Simulation time 187963954 ps
CPU time 4.48 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:10 PM PDT 24
Peak memory 197896 kb
Host smart-ea874079-4675-4c06-bded-55790eb8d3df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708807374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3708807374
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2132612723
Short name T409
Test name
Test status
Simulation time 25959303 ps
CPU time 0.69 seconds
Started Jun 06 12:45:45 PM PDT 24
Finished Jun 06 12:45:46 PM PDT 24
Peak memory 194896 kb
Host smart-2079c5f3-cc2d-411f-9507-711ad877e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132612723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2132612723
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.290324290
Short name T165
Test name
Test status
Simulation time 75401943 ps
CPU time 1.33 seconds
Started Jun 06 12:45:41 PM PDT 24
Finished Jun 06 12:45:43 PM PDT 24
Peak memory 197976 kb
Host smart-4932a966-9ba0-4fa2-adc0-88bf7acda464
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290324290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.290324290
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2079691404
Short name T456
Test name
Test status
Simulation time 2817002660 ps
CPU time 18.58 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 12:46:14 PM PDT 24
Peak memory 198128 kb
Host smart-45a0b167-2623-420a-8e8e-3755bc5eaa51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079691404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2079691404
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3634377259
Short name T26
Test name
Test status
Simulation time 162207506038 ps
CPU time 1820.15 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 01:16:15 PM PDT 24
Peak memory 198124 kb
Host smart-58db2b38-217e-49e4-9831-9bcefad09945
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3634377259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3634377259
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3059392644
Short name T172
Test name
Test status
Simulation time 19826294 ps
CPU time 0.54 seconds
Started Jun 06 12:45:56 PM PDT 24
Finished Jun 06 12:45:57 PM PDT 24
Peak memory 193780 kb
Host smart-2f545406-347f-4abf-95cf-f9165f4c0498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059392644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3059392644
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1157111391
Short name T405
Test name
Test status
Simulation time 40383646 ps
CPU time 0.61 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 12:45:55 PM PDT 24
Peak memory 194760 kb
Host smart-a645a54a-dd92-41e2-9f1c-25a2d5c68caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157111391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1157111391
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3651029144
Short name T181
Test name
Test status
Simulation time 2287134506 ps
CPU time 17.73 seconds
Started Jun 06 12:45:58 PM PDT 24
Finished Jun 06 12:46:16 PM PDT 24
Peak memory 198028 kb
Host smart-e3451f4d-2045-48be-b947-985dd8557dfc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651029144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3651029144
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3799668969
Short name T320
Test name
Test status
Simulation time 388155620 ps
CPU time 0.77 seconds
Started Jun 06 12:45:56 PM PDT 24
Finished Jun 06 12:45:57 PM PDT 24
Peak memory 195892 kb
Host smart-4e9f0ed3-bf04-4dff-9821-df3e2a4ed704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799668969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3799668969
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2820279491
Short name T479
Test name
Test status
Simulation time 41810197 ps
CPU time 1.24 seconds
Started Jun 06 12:46:01 PM PDT 24
Finished Jun 06 12:46:02 PM PDT 24
Peak memory 195772 kb
Host smart-6d84be36-f9ec-4a00-b2f1-7b30d199dcc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820279491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2820279491
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.24578324
Short name T152
Test name
Test status
Simulation time 47083934 ps
CPU time 1.85 seconds
Started Jun 06 12:45:56 PM PDT 24
Finished Jun 06 12:45:59 PM PDT 24
Peak memory 198028 kb
Host smart-e32d324b-4b40-410a-909a-414dcedc8510
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.gpio_intr_with_filter_rand_intr_event.24578324
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1788704250
Short name T646
Test name
Test status
Simulation time 59051218 ps
CPU time 1.35 seconds
Started Jun 06 12:45:57 PM PDT 24
Finished Jun 06 12:45:59 PM PDT 24
Peak memory 196824 kb
Host smart-cfcd909f-b4d2-4ed4-a96c-74c677cd0684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788704250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1788704250
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3157744039
Short name T100
Test name
Test status
Simulation time 49694201 ps
CPU time 0.79 seconds
Started Jun 06 12:45:55 PM PDT 24
Finished Jun 06 12:45:56 PM PDT 24
Peak memory 195348 kb
Host smart-21b5bd16-8e90-4864-b729-383225926214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157744039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3157744039
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2812636054
Short name T591
Test name
Test status
Simulation time 25611403 ps
CPU time 0.92 seconds
Started Jun 06 12:45:53 PM PDT 24
Finished Jun 06 12:45:55 PM PDT 24
Peak memory 195936 kb
Host smart-a7fcb709-50a0-4d87-96a2-84fedf6a371e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812636054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2812636054
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3859353867
Short name T378
Test name
Test status
Simulation time 5842205815 ps
CPU time 4.54 seconds
Started Jun 06 12:45:53 PM PDT 24
Finished Jun 06 12:45:58 PM PDT 24
Peak memory 198088 kb
Host smart-212d14c3-1ba6-4e89-be7f-868c6b64c64b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859353867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3859353867
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.993396871
Short name T279
Test name
Test status
Simulation time 55225818 ps
CPU time 0.87 seconds
Started Jun 06 12:45:59 PM PDT 24
Finished Jun 06 12:46:00 PM PDT 24
Peak memory 195424 kb
Host smart-3d7a5ae8-f1fa-449f-a26a-95034cfda224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993396871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.993396871
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.4109837301
Short name T315
Test name
Test status
Simulation time 282758220 ps
CPU time 1.3 seconds
Started Jun 06 12:45:55 PM PDT 24
Finished Jun 06 12:45:57 PM PDT 24
Peak memory 195800 kb
Host smart-97f93ebb-1551-4b6c-bd83-6e1108054e73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109837301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.4109837301
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1376758936
Short name T313
Test name
Test status
Simulation time 32898534464 ps
CPU time 151.81 seconds
Started Jun 06 12:46:01 PM PDT 24
Finished Jun 06 12:48:33 PM PDT 24
Peak memory 198100 kb
Host smart-b2cf361f-63fc-4e28-bf46-3bb48851418c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376758936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1376758936
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1589083288
Short name T56
Test name
Test status
Simulation time 85844209694 ps
CPU time 419.34 seconds
Started Jun 06 12:45:56 PM PDT 24
Finished Jun 06 12:52:56 PM PDT 24
Peak memory 198272 kb
Host smart-6db5eb8d-bbda-41b0-b3ed-71c0bf2313d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1589083288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1589083288
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2183607912
Short name T362
Test name
Test status
Simulation time 35705562 ps
CPU time 0.57 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:05 PM PDT 24
Peak memory 193988 kb
Host smart-b8dea774-c9c7-4067-80f6-6c79aa6fe3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183607912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2183607912
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.908532695
Short name T257
Test name
Test status
Simulation time 13966735 ps
CPU time 0.64 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 12:45:55 PM PDT 24
Peak memory 194648 kb
Host smart-5b853ae2-cb52-4fe2-83a8-525b9e13c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908532695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.908532695
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2455830513
Short name T293
Test name
Test status
Simulation time 437311845 ps
CPU time 21.95 seconds
Started Jun 06 12:45:51 PM PDT 24
Finished Jun 06 12:46:14 PM PDT 24
Peak memory 196828 kb
Host smart-da1aafe6-21db-41d7-867d-4e55fbb34a7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455830513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2455830513
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.673551601
Short name T666
Test name
Test status
Simulation time 142291629 ps
CPU time 0.77 seconds
Started Jun 06 12:45:55 PM PDT 24
Finished Jun 06 12:45:56 PM PDT 24
Peak memory 196444 kb
Host smart-8339b012-2741-4102-b8cd-335b7f6c58e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673551601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.673551601
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3343021497
Short name T421
Test name
Test status
Simulation time 77459552 ps
CPU time 1.3 seconds
Started Jun 06 12:45:52 PM PDT 24
Finished Jun 06 12:45:54 PM PDT 24
Peak memory 198028 kb
Host smart-95e4c71e-3b10-4928-a4b2-42b81535972b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343021497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3343021497
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2828603303
Short name T454
Test name
Test status
Simulation time 84820938 ps
CPU time 3.27 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 12:45:58 PM PDT 24
Peak memory 197984 kb
Host smart-b89587a2-ab74-4806-9f7e-a81b89283a96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828603303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2828603303
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.322738729
Short name T674
Test name
Test status
Simulation time 308336729 ps
CPU time 3.48 seconds
Started Jun 06 12:45:56 PM PDT 24
Finished Jun 06 12:46:00 PM PDT 24
Peak memory 195712 kb
Host smart-a6fabe87-7e3a-454d-9eff-3f868ffc1805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322738729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
322738729
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.733028224
Short name T539
Test name
Test status
Simulation time 75577166 ps
CPU time 0.84 seconds
Started Jun 06 12:45:53 PM PDT 24
Finished Jun 06 12:45:55 PM PDT 24
Peak memory 197120 kb
Host smart-79d1a087-810d-4509-ab6d-e70435ef541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733028224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.733028224
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.4120351305
Short name T615
Test name
Test status
Simulation time 104281693 ps
CPU time 0.95 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 12:45:56 PM PDT 24
Peak memory 195936 kb
Host smart-a5f9c6ce-38ad-47e4-bc0b-4cbfcc8e38cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120351305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.4120351305
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4247313892
Short name T8
Test name
Test status
Simulation time 984812948 ps
CPU time 5.6 seconds
Started Jun 06 12:45:55 PM PDT 24
Finished Jun 06 12:46:01 PM PDT 24
Peak memory 197908 kb
Host smart-61ced961-efbf-405f-a0bf-87826cef8835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247313892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4247313892
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2827261994
Short name T359
Test name
Test status
Simulation time 282473027 ps
CPU time 1.31 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 12:45:56 PM PDT 24
Peak memory 197900 kb
Host smart-8c1c126d-c779-48b2-84a0-9737453eda49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827261994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2827261994
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.709068571
Short name T541
Test name
Test status
Simulation time 260336318 ps
CPU time 1.16 seconds
Started Jun 06 12:45:56 PM PDT 24
Finished Jun 06 12:45:58 PM PDT 24
Peak memory 195728 kb
Host smart-dc365e63-cf5a-43e1-b92b-160b60fdb44c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709068571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.709068571
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4284220918
Short name T544
Test name
Test status
Simulation time 23168239265 ps
CPU time 131.43 seconds
Started Jun 06 12:46:01 PM PDT 24
Finished Jun 06 12:48:13 PM PDT 24
Peak memory 198056 kb
Host smart-9b66c424-00e7-4828-a0ed-f71d7d529f55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284220918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4284220918
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2549610423
Short name T61
Test name
Test status
Simulation time 84086693580 ps
CPU time 1595.33 seconds
Started Jun 06 12:45:54 PM PDT 24
Finished Jun 06 01:12:30 PM PDT 24
Peak memory 198216 kb
Host smart-8f304bef-4f7e-467e-a3d2-052b2c1e50d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2549610423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2549610423
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1826353336
Short name T661
Test name
Test status
Simulation time 40874643 ps
CPU time 0.55 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 193784 kb
Host smart-486f4196-dcf5-444d-976a-a3a812538a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826353336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1826353336
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3994957753
Short name T220
Test name
Test status
Simulation time 21669428 ps
CPU time 0.73 seconds
Started Jun 06 12:46:03 PM PDT 24
Finished Jun 06 12:46:05 PM PDT 24
Peak memory 195312 kb
Host smart-5c747576-588a-460c-a606-2f6ec986b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994957753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3994957753
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1803002158
Short name T575
Test name
Test status
Simulation time 5133279730 ps
CPU time 13.77 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:19 PM PDT 24
Peak memory 198100 kb
Host smart-5c51d223-a36f-4765-9f93-d048af75d5a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803002158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1803002158
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3589241337
Short name T226
Test name
Test status
Simulation time 47973144 ps
CPU time 0.75 seconds
Started Jun 06 12:46:05 PM PDT 24
Finished Jun 06 12:46:07 PM PDT 24
Peak memory 194672 kb
Host smart-b9183227-b7b1-42db-a753-b3ee6c07aad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589241337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3589241337
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1404301335
Short name T426
Test name
Test status
Simulation time 110117100 ps
CPU time 1.14 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:07 PM PDT 24
Peak memory 196456 kb
Host smart-03039999-78ef-4ff4-ac2b-43d11ef32291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404301335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1404301335
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1672538490
Short name T553
Test name
Test status
Simulation time 69836773 ps
CPU time 2.64 seconds
Started Jun 06 12:46:02 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 198056 kb
Host smart-827e4e4a-48d3-4324-bd79-cddd79211c7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672538490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1672538490
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3476130523
Short name T486
Test name
Test status
Simulation time 570932704 ps
CPU time 3.43 seconds
Started Jun 06 12:46:16 PM PDT 24
Finished Jun 06 12:46:20 PM PDT 24
Peak memory 196352 kb
Host smart-9c4d2355-b528-4076-b222-4a1eadcd9a6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476130523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3476130523
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2655504138
Short name T311
Test name
Test status
Simulation time 24262708 ps
CPU time 0.93 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:07 PM PDT 24
Peak memory 196616 kb
Host smart-805f52ea-ca1e-4b3f-bb51-6b0fb18b2b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655504138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2655504138
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2805458927
Short name T530
Test name
Test status
Simulation time 36436976 ps
CPU time 0.96 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 195760 kb
Host smart-4ca04ee6-9b0a-401a-982c-f4ac0c828f1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805458927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2805458927
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3428665927
Short name T627
Test name
Test status
Simulation time 542491435 ps
CPU time 2.52 seconds
Started Jun 06 12:46:03 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 197952 kb
Host smart-d0688b63-f3f1-44af-8b42-116082a158a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428665927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3428665927
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3959026694
Short name T527
Test name
Test status
Simulation time 133432163 ps
CPU time 1.32 seconds
Started Jun 06 12:46:03 PM PDT 24
Finished Jun 06 12:46:05 PM PDT 24
Peak memory 196388 kb
Host smart-dbc912cb-b866-4e0a-868d-fdd5daf4139f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959026694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3959026694
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1106265706
Short name T321
Test name
Test status
Simulation time 55828245 ps
CPU time 1.2 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 196508 kb
Host smart-beb844bd-a89c-47c2-92f0-e9d150f7a2a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106265706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1106265706
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4046860711
Short name T492
Test name
Test status
Simulation time 27316312861 ps
CPU time 162.38 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:48:47 PM PDT 24
Peak memory 198164 kb
Host smart-75e07482-55da-4d04-9d0f-f2455b943b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046860711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4046860711
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1325135355
Short name T536
Test name
Test status
Simulation time 20994102 ps
CPU time 0.57 seconds
Started Jun 06 12:46:01 PM PDT 24
Finished Jun 06 12:46:02 PM PDT 24
Peak memory 193776 kb
Host smart-cdbc228f-32f2-4e30-b1f9-feed33a58357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325135355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1325135355
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2510500132
Short name T708
Test name
Test status
Simulation time 142526021 ps
CPU time 0.85 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:07 PM PDT 24
Peak memory 196312 kb
Host smart-d8df111f-34ed-4fd3-b086-ec00430fe525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510500132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2510500132
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2365532143
Short name T324
Test name
Test status
Simulation time 263367651 ps
CPU time 9.01 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:14 PM PDT 24
Peak memory 196832 kb
Host smart-62176245-d30b-4ffb-8910-0c806a19cf68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365532143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2365532143
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1921589424
Short name T132
Test name
Test status
Simulation time 67062860 ps
CPU time 0.6 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 194436 kb
Host smart-c52b3404-332b-4576-9fb1-79011c0bec85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921589424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1921589424
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2517887402
Short name T391
Test name
Test status
Simulation time 90425624 ps
CPU time 1.45 seconds
Started Jun 06 12:46:02 PM PDT 24
Finished Jun 06 12:46:04 PM PDT 24
Peak memory 197076 kb
Host smart-9e6be469-7640-440b-b459-37aaa9c7e24e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517887402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2517887402
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1846423366
Short name T653
Test name
Test status
Simulation time 39142824 ps
CPU time 0.92 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 196644 kb
Host smart-6778ad98-dc36-47c6-b553-290fe3f5792a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846423366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1846423366
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2401555836
Short name T665
Test name
Test status
Simulation time 232945700 ps
CPU time 2.68 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 197096 kb
Host smart-b5142739-9212-472d-b470-fb3b84910d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401555836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2401555836
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3427369645
Short name T415
Test name
Test status
Simulation time 328450146 ps
CPU time 1.07 seconds
Started Jun 06 12:46:03 PM PDT 24
Finished Jun 06 12:46:04 PM PDT 24
Peak memory 195884 kb
Host smart-aa7a2837-6c7c-4105-a1e4-23acf51fcf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427369645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3427369645
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4182937295
Short name T63
Test name
Test status
Simulation time 56227094 ps
CPU time 1.09 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 195912 kb
Host smart-1bc5f290-a929-478e-ab4e-de6df93f654f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182937295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4182937295
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4178687664
Short name T21
Test name
Test status
Simulation time 217250292 ps
CPU time 3.04 seconds
Started Jun 06 12:46:02 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 197908 kb
Host smart-4012811d-09c6-49c0-8f11-abdf8723f4ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178687664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4178687664
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2087472880
Short name T504
Test name
Test status
Simulation time 44343944 ps
CPU time 1.24 seconds
Started Jun 06 12:46:03 PM PDT 24
Finished Jun 06 12:46:05 PM PDT 24
Peak memory 195664 kb
Host smart-d199aa73-1c2a-47a9-941e-404ecfc40160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087472880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2087472880
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.565230743
Short name T318
Test name
Test status
Simulation time 48833139 ps
CPU time 0.86 seconds
Started Jun 06 12:46:05 PM PDT 24
Finished Jun 06 12:46:07 PM PDT 24
Peak memory 195656 kb
Host smart-0a52a1ab-6ceb-4f74-845d-6190bee2fe90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565230743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.565230743
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1782428034
Short name T12
Test name
Test status
Simulation time 13203182706 ps
CPU time 73.12 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:47:19 PM PDT 24
Peak memory 198092 kb
Host smart-d863af11-8033-4bb6-8167-17a323c412b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782428034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1782428034
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3134669178
Short name T397
Test name
Test status
Simulation time 38322623 ps
CPU time 0.56 seconds
Started Jun 06 12:46:12 PM PDT 24
Finished Jun 06 12:46:13 PM PDT 24
Peak memory 194580 kb
Host smart-d7b4fe5a-ee5f-4bef-a1cf-33d74e67adb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134669178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3134669178
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3550818612
Short name T101
Test name
Test status
Simulation time 120555256 ps
CPU time 0.93 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 195688 kb
Host smart-d12c655c-7104-48d0-9840-fd3920f67ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550818612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3550818612
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4130322805
Short name T625
Test name
Test status
Simulation time 276716202 ps
CPU time 7.77 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:13 PM PDT 24
Peak memory 196608 kb
Host smart-8d8526bd-c484-427f-b852-e47346ec0360
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130322805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4130322805
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3345330721
Short name T568
Test name
Test status
Simulation time 85072245 ps
CPU time 0.91 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:46:19 PM PDT 24
Peak memory 197940 kb
Host smart-b8c1dcdf-fbcb-4367-b1d9-32e438b5f678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345330721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3345330721
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3845138774
Short name T23
Test name
Test status
Simulation time 192425919 ps
CPU time 1.42 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:09 PM PDT 24
Peak memory 196920 kb
Host smart-ffba945b-578c-4071-aa0f-817ae7f0fdf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845138774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3845138774
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1350860346
Short name T471
Test name
Test status
Simulation time 282764160 ps
CPU time 2.82 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:10 PM PDT 24
Peak memory 197764 kb
Host smart-5e7c4cc5-d4b4-4f7d-bff6-4f7be66cdab2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350860346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1350860346
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.585767169
Short name T692
Test name
Test status
Simulation time 289987567 ps
CPU time 1.63 seconds
Started Jun 06 12:46:05 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 196364 kb
Host smart-145474d6-2e0b-4531-95a2-e593208f2341
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585767169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
585767169
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.569125798
Short name T589
Test name
Test status
Simulation time 95373128 ps
CPU time 1.25 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 197036 kb
Host smart-58cee3dc-f806-43f2-bde9-32c3a9fc6d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569125798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.569125798
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2916504853
Short name T204
Test name
Test status
Simulation time 49331572 ps
CPU time 0.66 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:05 PM PDT 24
Peak memory 194276 kb
Host smart-384f0ffc-c4ab-4317-8754-54bd6195a44d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916504853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2916504853
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3290901764
Short name T291
Test name
Test status
Simulation time 1743009459 ps
CPU time 4.21 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:20 PM PDT 24
Peak memory 197884 kb
Host smart-f5ff95c0-45b8-4ab0-ad02-ee842481be90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290901764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3290901764
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1622944990
Short name T519
Test name
Test status
Simulation time 107170921 ps
CPU time 0.97 seconds
Started Jun 06 12:46:06 PM PDT 24
Finished Jun 06 12:46:08 PM PDT 24
Peak memory 195352 kb
Host smart-ca8fbbf7-a558-45b3-92e5-1ccac52928a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622944990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1622944990
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.244827826
Short name T223
Test name
Test status
Simulation time 45593280 ps
CPU time 0.89 seconds
Started Jun 06 12:46:04 PM PDT 24
Finished Jun 06 12:46:06 PM PDT 24
Peak memory 196256 kb
Host smart-8f910304-9f93-4666-8e06-9affc206508c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244827826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.244827826
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4149554249
Short name T212
Test name
Test status
Simulation time 2002469124 ps
CPU time 30.18 seconds
Started Jun 06 12:46:13 PM PDT 24
Finished Jun 06 12:46:44 PM PDT 24
Peak memory 197980 kb
Host smart-eb91c0fa-53ae-48ec-8ea8-993817e33d5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149554249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4149554249
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2723099149
Short name T537
Test name
Test status
Simulation time 780869800632 ps
CPU time 2417.11 seconds
Started Jun 06 12:46:20 PM PDT 24
Finished Jun 06 01:26:38 PM PDT 24
Peak memory 198176 kb
Host smart-10b7ea35-2c60-40a1-9407-989c15cb4702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2723099149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2723099149
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3411040853
Short name T195
Test name
Test status
Simulation time 12691404 ps
CPU time 0.63 seconds
Started Jun 06 12:46:14 PM PDT 24
Finished Jun 06 12:46:15 PM PDT 24
Peak memory 194176 kb
Host smart-a63398fb-5e3a-4955-bc7f-e01fbbdc20df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411040853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3411040853
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1197501619
Short name T444
Test name
Test status
Simulation time 95253561 ps
CPU time 0.93 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:46:19 PM PDT 24
Peak memory 197020 kb
Host smart-8956cf06-2493-405c-8bfb-50fcb30c1bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197501619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1197501619
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3043275734
Short name T681
Test name
Test status
Simulation time 2942848104 ps
CPU time 24.98 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:46:43 PM PDT 24
Peak memory 198064 kb
Host smart-27980876-6cf6-4e61-9d83-2b3977a5bfc1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043275734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3043275734
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2500971653
Short name T384
Test name
Test status
Simulation time 55257390 ps
CPU time 0.79 seconds
Started Jun 06 12:46:16 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 196556 kb
Host smart-a2f819d9-dbc0-4fe0-9b63-7597a83d4ce6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500971653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2500971653
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2721473211
Short name T406
Test name
Test status
Simulation time 89909804 ps
CPU time 1.34 seconds
Started Jun 06 12:46:14 PM PDT 24
Finished Jun 06 12:46:16 PM PDT 24
Peak memory 195752 kb
Host smart-34945502-feba-4918-ba16-e3b6dfb6366e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721473211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2721473211
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2816183109
Short name T430
Test name
Test status
Simulation time 186699103 ps
CPU time 3.52 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:19 PM PDT 24
Peak memory 198020 kb
Host smart-4e057738-9271-4bfc-920c-f8a2f0d7d5d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816183109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2816183109
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.715448142
Short name T142
Test name
Test status
Simulation time 151368964 ps
CPU time 2.43 seconds
Started Jun 06 12:46:14 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 195752 kb
Host smart-c2b12a62-3fc3-4d69-873a-092f4d7da4ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715448142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
715448142
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3107686019
Short name T669
Test name
Test status
Simulation time 228513619 ps
CPU time 1.26 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 196044 kb
Host smart-9c4f294d-ebd6-480f-9712-8e1d0b8196b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107686019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3107686019
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2489997658
Short name T139
Test name
Test status
Simulation time 199692158 ps
CPU time 1.25 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 197088 kb
Host smart-2b68f594-7670-4c8b-ac0c-a57e27a19adb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489997658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2489997658
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3172305624
Short name T393
Test name
Test status
Simulation time 131238567 ps
CPU time 5.98 seconds
Started Jun 06 12:46:16 PM PDT 24
Finished Jun 06 12:46:22 PM PDT 24
Peak memory 197900 kb
Host smart-1287694b-598b-4c44-93ae-405d2ebf8efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172305624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3172305624
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.130822640
Short name T394
Test name
Test status
Simulation time 70014703 ps
CPU time 0.81 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:46:18 PM PDT 24
Peak memory 195328 kb
Host smart-8a51ea4b-59ce-446c-bad9-343a6dcb960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130822640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.130822640
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2850660977
Short name T505
Test name
Test status
Simulation time 412513777 ps
CPU time 1.09 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 195660 kb
Host smart-83321cc9-09ce-4aaf-b899-f9ef1b37e64a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850660977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2850660977
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3491218932
Short name T635
Test name
Test status
Simulation time 26974835101 ps
CPU time 157.77 seconds
Started Jun 06 12:46:14 PM PDT 24
Finished Jun 06 12:48:52 PM PDT 24
Peak memory 198164 kb
Host smart-2eb2cf31-096d-47cd-95df-f2d7f068f561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491218932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3491218932
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1578465216
Short name T57
Test name
Test status
Simulation time 49017462617 ps
CPU time 662.41 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:57:20 PM PDT 24
Peak memory 198160 kb
Host smart-4795a653-7c12-4f8a-a7f9-e30d20d5cb42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1578465216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1578465216
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3883375498
Short name T250
Test name
Test status
Simulation time 89006367 ps
CPU time 0.59 seconds
Started Jun 06 12:46:20 PM PDT 24
Finished Jun 06 12:46:22 PM PDT 24
Peak memory 193868 kb
Host smart-fc71822a-429c-4180-b593-d1edd64344c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883375498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3883375498
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3991317465
Short name T203
Test name
Test status
Simulation time 13238618 ps
CPU time 0.6 seconds
Started Jun 06 12:46:14 PM PDT 24
Finished Jun 06 12:46:15 PM PDT 24
Peak memory 193952 kb
Host smart-c6499513-835b-4dbe-a9b0-8888ad417637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991317465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3991317465
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.762103825
Short name T386
Test name
Test status
Simulation time 1961818183 ps
CPU time 14.54 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:46:32 PM PDT 24
Peak memory 196544 kb
Host smart-24186c67-c7c3-49a0-80e7-ca4a92f8c611
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762103825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.762103825
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.776735768
Short name T710
Test name
Test status
Simulation time 915134941 ps
CPU time 0.81 seconds
Started Jun 06 12:46:14 PM PDT 24
Finished Jun 06 12:46:15 PM PDT 24
Peak memory 196672 kb
Host smart-f3b91fef-aac3-4429-9ca7-14a09e36d923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776735768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.776735768
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2759774558
Short name T194
Test name
Test status
Simulation time 22758615 ps
CPU time 0.77 seconds
Started Jun 06 12:46:13 PM PDT 24
Finished Jun 06 12:46:15 PM PDT 24
Peak memory 196064 kb
Host smart-eb73a534-2e6f-4031-9f06-b479f11330df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759774558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2759774558
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.571502725
Short name T542
Test name
Test status
Simulation time 30607696 ps
CPU time 1.17 seconds
Started Jun 06 12:46:12 PM PDT 24
Finished Jun 06 12:46:14 PM PDT 24
Peak memory 196308 kb
Host smart-0aafbcb2-3788-4229-925c-2ab5b598ae8d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571502725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.571502725
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3107678040
Short name T428
Test name
Test status
Simulation time 149386637 ps
CPU time 0.99 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 195608 kb
Host smart-2c8340fa-d647-44f2-a37b-1cc1c0945e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107678040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3107678040
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2697997342
Short name T698
Test name
Test status
Simulation time 336887428 ps
CPU time 1.37 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 195800 kb
Host smart-0de44297-7d67-4c07-bcc9-20ddfd00427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697997342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2697997342
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1150373993
Short name T452
Test name
Test status
Simulation time 197953089 ps
CPU time 0.92 seconds
Started Jun 06 12:46:16 PM PDT 24
Finished Jun 06 12:46:18 PM PDT 24
Peak memory 196524 kb
Host smart-7f65b125-3e26-4c24-9576-407fbc108cf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150373993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1150373993
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2380607543
Short name T379
Test name
Test status
Simulation time 28441501 ps
CPU time 1.37 seconds
Started Jun 06 12:46:16 PM PDT 24
Finished Jun 06 12:46:18 PM PDT 24
Peak memory 197892 kb
Host smart-a45e9af1-26d8-499c-a739-2582f3cf83d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380607543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2380607543
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.129190993
Short name T285
Test name
Test status
Simulation time 65179208 ps
CPU time 1.12 seconds
Started Jun 06 12:46:16 PM PDT 24
Finished Jun 06 12:46:18 PM PDT 24
Peak memory 195732 kb
Host smart-0f622c68-1cec-44ae-bd01-dd040f4bea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129190993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.129190993
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2841461915
Short name T525
Test name
Test status
Simulation time 304292487 ps
CPU time 1.05 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 12:46:17 PM PDT 24
Peak memory 196384 kb
Host smart-4a0d9f6f-a4f4-482c-b6c6-56a7281a14ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841461915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2841461915
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.6329674
Short name T664
Test name
Test status
Simulation time 50542869421 ps
CPU time 194.14 seconds
Started Jun 06 12:46:17 PM PDT 24
Finished Jun 06 12:49:32 PM PDT 24
Peak memory 198128 kb
Host smart-30ab5e04-b044-4f99-b477-105303dcb26d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6329674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpi
o_stress_all.6329674
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.356856670
Short name T58
Test name
Test status
Simulation time 60138874488 ps
CPU time 945.71 seconds
Started Jun 06 12:46:15 PM PDT 24
Finished Jun 06 01:02:02 PM PDT 24
Peak memory 198244 kb
Host smart-e05ff1b8-59db-4123-ad99-9e80075874a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=356856670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.356856670
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1491802530
Short name T516
Test name
Test status
Simulation time 15374939 ps
CPU time 0.57 seconds
Started Jun 06 12:46:24 PM PDT 24
Finished Jun 06 12:46:25 PM PDT 24
Peak memory 193800 kb
Host smart-be82a62d-1989-45da-aca5-5764ff47df4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491802530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1491802530
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.518905839
Short name T124
Test name
Test status
Simulation time 160263934 ps
CPU time 0.92 seconds
Started Jun 06 12:46:22 PM PDT 24
Finished Jun 06 12:46:24 PM PDT 24
Peak memory 195776 kb
Host smart-ea089fda-d372-4f2c-ae91-536dee261cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518905839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.518905839
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.918869432
Short name T599
Test name
Test status
Simulation time 1264808094 ps
CPU time 15.04 seconds
Started Jun 06 12:46:25 PM PDT 24
Finished Jun 06 12:46:41 PM PDT 24
Peak memory 197944 kb
Host smart-783a9f71-02d7-4dfa-9f1a-c3afae47d7b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918869432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.918869432
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.691345238
Short name T418
Test name
Test status
Simulation time 52663156 ps
CPU time 0.86 seconds
Started Jun 06 12:46:26 PM PDT 24
Finished Jun 06 12:46:27 PM PDT 24
Peak memory 195888 kb
Host smart-9aafa141-02dc-450b-ae07-cd4333e4fcf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691345238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.691345238
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.878001206
Short name T532
Test name
Test status
Simulation time 39007893 ps
CPU time 1.07 seconds
Started Jun 06 12:46:26 PM PDT 24
Finished Jun 06 12:46:28 PM PDT 24
Peak memory 196696 kb
Host smart-d988f06f-feb1-4a1c-8c01-e786aa9f5791
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878001206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.878001206
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1720560514
Short name T412
Test name
Test status
Simulation time 116882659 ps
CPU time 1.45 seconds
Started Jun 06 12:46:25 PM PDT 24
Finished Jun 06 12:46:27 PM PDT 24
Peak memory 198004 kb
Host smart-4d152f74-8c1b-4c80-9535-40115accf84b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720560514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1720560514
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2219951609
Short name T459
Test name
Test status
Simulation time 238019175 ps
CPU time 2.73 seconds
Started Jun 06 12:46:28 PM PDT 24
Finished Jun 06 12:46:31 PM PDT 24
Peak memory 196920 kb
Host smart-71ed9c3c-0a10-4c0d-af17-ac9931d7c6d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219951609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2219951609
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.669428560
Short name T559
Test name
Test status
Simulation time 14916941 ps
CPU time 0.7 seconds
Started Jun 06 12:46:27 PM PDT 24
Finished Jun 06 12:46:28 PM PDT 24
Peak memory 194228 kb
Host smart-c774edac-055c-408d-bdef-1323d693a1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669428560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.669428560
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2470918043
Short name T150
Test name
Test status
Simulation time 203290218 ps
CPU time 1.24 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 197012 kb
Host smart-17b8f7fb-6171-4241-9786-d9475bc5fa7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470918043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2470918043
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.811174943
Short name T237
Test name
Test status
Simulation time 249709288 ps
CPU time 3.15 seconds
Started Jun 06 12:46:23 PM PDT 24
Finished Jun 06 12:46:27 PM PDT 24
Peak memory 198008 kb
Host smart-aba3ca7f-70d0-4238-a2ec-456b178ad5f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811174943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.811174943
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.908115146
Short name T592
Test name
Test status
Simulation time 54956488 ps
CPU time 1.01 seconds
Started Jun 06 12:46:24 PM PDT 24
Finished Jun 06 12:46:25 PM PDT 24
Peak memory 196520 kb
Host smart-56a30ac6-f5b5-4253-a2f3-b48860f2b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908115146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.908115146
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.141829760
Short name T476
Test name
Test status
Simulation time 109807682 ps
CPU time 0.96 seconds
Started Jun 06 12:46:27 PM PDT 24
Finished Jun 06 12:46:29 PM PDT 24
Peak memory 195692 kb
Host smart-e11e65c9-64b0-4f14-9150-8e0d6d41a622
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141829760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.141829760
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3074262465
Short name T236
Test name
Test status
Simulation time 5833158163 ps
CPU time 42.9 seconds
Started Jun 06 12:46:24 PM PDT 24
Finished Jun 06 12:47:08 PM PDT 24
Peak memory 198164 kb
Host smart-e552e0fc-6b9d-49e9-887b-c38f6fb55cbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074262465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3074262465
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1601444583
Short name T328
Test name
Test status
Simulation time 100535540 ps
CPU time 0.56 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:43:29 PM PDT 24
Peak memory 195564 kb
Host smart-ec1d5f4e-bf13-4eaa-a728-5c449f3cf74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601444583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1601444583
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2255818499
Short name T278
Test name
Test status
Simulation time 36775743 ps
CPU time 0.83 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 195452 kb
Host smart-c6db1262-175f-4418-a124-e4d75a1fc731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255818499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2255818499
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.345683450
Short name T511
Test name
Test status
Simulation time 733115475 ps
CPU time 18.51 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:44 PM PDT 24
Peak memory 196704 kb
Host smart-a1dfbd42-a6eb-4f5e-8981-25fb47af115d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345683450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.345683450
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3013499022
Short name T337
Test name
Test status
Simulation time 167995886 ps
CPU time 0.82 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:43:25 PM PDT 24
Peak memory 196088 kb
Host smart-fc127d60-bc0e-463c-8b7e-b56c3514faea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013499022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3013499022
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1561867533
Short name T138
Test name
Test status
Simulation time 292608570 ps
CPU time 1.09 seconds
Started Jun 06 12:43:28 PM PDT 24
Finished Jun 06 12:43:30 PM PDT 24
Peak memory 195724 kb
Host smart-2903e514-3503-4f26-abaf-970ce600777c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561867533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1561867533
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3148664703
Short name T713
Test name
Test status
Simulation time 325149483 ps
CPU time 1.81 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:43:29 PM PDT 24
Peak memory 198000 kb
Host smart-eb69dfb6-0bb0-42a5-9f32-80efcdea60f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148664703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3148664703
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1288296866
Short name T184
Test name
Test status
Simulation time 658548144 ps
CPU time 2.8 seconds
Started Jun 06 12:43:25 PM PDT 24
Finished Jun 06 12:43:29 PM PDT 24
Peak memory 196848 kb
Host smart-b3486e05-9ae2-4ed1-8396-086937e8280d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288296866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1288296866
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2729461018
Short name T268
Test name
Test status
Simulation time 29291140 ps
CPU time 0.67 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 195220 kb
Host smart-1a3344c8-d5a0-47ac-809e-b91331c1dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729461018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2729461018
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2257363953
Short name T354
Test name
Test status
Simulation time 57099747 ps
CPU time 1.22 seconds
Started Jun 06 12:43:24 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 195760 kb
Host smart-5b869247-a5df-4ba5-b6eb-a1669c60b2c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257363953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2257363953
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3060568256
Short name T126
Test name
Test status
Simulation time 39855338 ps
CPU time 1.86 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 197352 kb
Host smart-31cf9129-ccee-45d8-a173-1c8a76b5ad0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060568256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3060568256
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4218447209
Short name T180
Test name
Test status
Simulation time 67183251 ps
CPU time 1.14 seconds
Started Jun 06 12:43:25 PM PDT 24
Finished Jun 06 12:43:27 PM PDT 24
Peak memory 196236 kb
Host smart-c22819f9-471d-44b1-90df-f36acaa325b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218447209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4218447209
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.700475865
Short name T660
Test name
Test status
Simulation time 223250618 ps
CPU time 1.04 seconds
Started Jun 06 12:43:22 PM PDT 24
Finished Jun 06 12:43:24 PM PDT 24
Peak memory 195652 kb
Host smart-e1eccf3a-d063-464f-9ef2-15d361200eaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700475865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.700475865
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.79674856
Short name T316
Test name
Test status
Simulation time 45322155547 ps
CPU time 132.37 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:45:37 PM PDT 24
Peak memory 198200 kb
Host smart-4be9a74c-3e40-41e5-a849-bb483b607a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79674856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpi
o_stress_all.79674856
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.430398353
Short name T388
Test name
Test status
Simulation time 30416467 ps
CPU time 0.6 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:35 PM PDT 24
Peak memory 194536 kb
Host smart-e452843e-1c6d-4e3b-b31f-943de13ce801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430398353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.430398353
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2781768612
Short name T50
Test name
Test status
Simulation time 39023345 ps
CPU time 0.64 seconds
Started Jun 06 12:43:35 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 193844 kb
Host smart-29011bc9-d511-4f00-9fea-8d60f7af0c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781768612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2781768612
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1382392130
Short name T638
Test name
Test status
Simulation time 449793493 ps
CPU time 11.32 seconds
Started Jun 06 12:43:35 PM PDT 24
Finished Jun 06 12:43:47 PM PDT 24
Peak memory 197696 kb
Host smart-ec64387a-8f56-4937-9f07-b637650829c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382392130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1382392130
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4084629339
Short name T662
Test name
Test status
Simulation time 46111350 ps
CPU time 0.62 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:43:34 PM PDT 24
Peak memory 195100 kb
Host smart-734020b6-d104-4bc0-9147-272ac1d475c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084629339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4084629339
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3782193325
Short name T389
Test name
Test status
Simulation time 46671296 ps
CPU time 1.21 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:43:25 PM PDT 24
Peak memory 196588 kb
Host smart-2f4af3c8-2866-42b0-b262-4064f9bf46de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782193325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3782193325
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2230852236
Short name T294
Test name
Test status
Simulation time 35836004 ps
CPU time 1.08 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:43:29 PM PDT 24
Peak memory 196412 kb
Host smart-5294e34d-2033-4f8c-a363-be5a1fb5480f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230852236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2230852236
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3267008739
Short name T637
Test name
Test status
Simulation time 86201745 ps
CPU time 2.34 seconds
Started Jun 06 12:43:27 PM PDT 24
Finished Jun 06 12:43:30 PM PDT 24
Peak memory 197088 kb
Host smart-d52b8473-c975-4f11-896b-7a357648d591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267008739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3267008739
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2611614911
Short name T296
Test name
Test status
Simulation time 127075861 ps
CPU time 0.88 seconds
Started Jun 06 12:43:35 PM PDT 24
Finished Jun 06 12:43:37 PM PDT 24
Peak memory 196312 kb
Host smart-444dd415-549e-4bfc-a652-a3e227830036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611614911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2611614911
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3437800466
Short name T410
Test name
Test status
Simulation time 50157762 ps
CPU time 1.01 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:43:25 PM PDT 24
Peak memory 195896 kb
Host smart-9450f7af-b750-4a68-a743-f1df5c9cf6c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437800466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3437800466
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3882697443
Short name T156
Test name
Test status
Simulation time 1437461496 ps
CPU time 3.22 seconds
Started Jun 06 12:43:22 PM PDT 24
Finished Jun 06 12:43:26 PM PDT 24
Peak memory 197920 kb
Host smart-92f27f47-b174-416b-86c9-ea3f8e6cd58b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882697443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3882697443
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.4250004419
Short name T234
Test name
Test status
Simulation time 194715522 ps
CPU time 0.98 seconds
Started Jun 06 12:43:23 PM PDT 24
Finished Jun 06 12:43:25 PM PDT 24
Peak memory 195672 kb
Host smart-5c28f873-1c93-4e8c-a8b0-258f89ec8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250004419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.4250004419
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4059862927
Short name T94
Test name
Test status
Simulation time 479384747 ps
CPU time 1.01 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 195468 kb
Host smart-061101f2-0db1-4a0a-8d6d-28f040201b01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059862927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4059862927
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.491814829
Short name T491
Test name
Test status
Simulation time 3984373115 ps
CPU time 22.1 seconds
Started Jun 06 12:43:37 PM PDT 24
Finished Jun 06 12:44:00 PM PDT 24
Peak memory 198084 kb
Host smart-4a69d19b-3b99-46b3-8a47-7069b18dc86a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491814829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.491814829
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.4079362172
Short name T93
Test name
Test status
Simulation time 22093484006 ps
CPU time 302.81 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:48:36 PM PDT 24
Peak memory 198184 kb
Host smart-45f6488b-81ae-4ada-946a-2926c610eb7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4079362172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.4079362172
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1535780020
Short name T189
Test name
Test status
Simulation time 15074972 ps
CPU time 0.56 seconds
Started Jun 06 12:43:41 PM PDT 24
Finished Jun 06 12:43:42 PM PDT 24
Peak memory 193880 kb
Host smart-2fea8515-6f5f-439b-a5a4-c34ea603475c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535780020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1535780020
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3576595784
Short name T535
Test name
Test status
Simulation time 213583006 ps
CPU time 0.94 seconds
Started Jun 06 12:43:37 PM PDT 24
Finished Jun 06 12:43:39 PM PDT 24
Peak memory 195732 kb
Host smart-1761dc7f-c983-47fe-8153-5e167eb4693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576595784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3576595784
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.156844268
Short name T188
Test name
Test status
Simulation time 2654616107 ps
CPU time 21.95 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:57 PM PDT 24
Peak memory 197060 kb
Host smart-71f811d1-1da3-487a-9176-bc32b11da434
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156844268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.156844268
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.346404642
Short name T554
Test name
Test status
Simulation time 100762467 ps
CPU time 0.8 seconds
Started Jun 06 12:43:30 PM PDT 24
Finished Jun 06 12:43:32 PM PDT 24
Peak memory 196652 kb
Host smart-87b8566a-f86f-4dad-b054-1eed1c576bc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346404642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.346404642
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.713984286
Short name T695
Test name
Test status
Simulation time 82887910 ps
CPU time 1.29 seconds
Started Jun 06 12:43:38 PM PDT 24
Finished Jun 06 12:43:39 PM PDT 24
Peak memory 195704 kb
Host smart-70b2e71e-9686-4aeb-8783-2fd5c9be8d56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713984286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.713984286
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.356093092
Short name T350
Test name
Test status
Simulation time 25550525 ps
CPU time 0.98 seconds
Started Jun 06 12:43:43 PM PDT 24
Finished Jun 06 12:43:44 PM PDT 24
Peak memory 196008 kb
Host smart-46c6cb16-837d-427f-90ce-059c46e84bf0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356093092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.356093092
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3731266658
Short name T193
Test name
Test status
Simulation time 178906621 ps
CPU time 2.7 seconds
Started Jun 06 12:43:31 PM PDT 24
Finished Jun 06 12:43:34 PM PDT 24
Peak memory 196844 kb
Host smart-9ad4d219-e6f7-484f-831c-8571fb52d2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731266658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3731266658
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.387190599
Short name T499
Test name
Test status
Simulation time 99810643 ps
CPU time 1.11 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 195684 kb
Host smart-220c7816-fc8e-4eb0-a644-9ff47d53255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387190599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.387190599
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2808030214
Short name T284
Test name
Test status
Simulation time 105030547 ps
CPU time 0.68 seconds
Started Jun 06 12:43:35 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 195320 kb
Host smart-8836ab63-cfdc-47a5-87ad-7aa3ccc9c0b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808030214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2808030214
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3292507508
Short name T689
Test name
Test status
Simulation time 283248132 ps
CPU time 1.81 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:37 PM PDT 24
Peak memory 197956 kb
Host smart-9b8426a2-4e3c-40d9-bba1-4cf1c670c020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292507508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3292507508
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1567126750
Short name T121
Test name
Test status
Simulation time 171144579 ps
CPU time 0.92 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:43:34 PM PDT 24
Peak memory 196384 kb
Host smart-6576af61-ba5d-42d9-93d4-8a1df6412830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567126750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1567126750
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.755060656
Short name T647
Test name
Test status
Simulation time 91462026 ps
CPU time 1.41 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:35 PM PDT 24
Peak memory 196720 kb
Host smart-1d0fa2d7-ae2c-4284-aefd-3318db1c5e3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755060656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.755060656
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.38506054
Short name T694
Test name
Test status
Simulation time 4985599458 ps
CPU time 28.25 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 198048 kb
Host smart-8834da43-2baa-423d-89eb-7d69bc76f5a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38506054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpi
o_stress_all.38506054
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3238791688
Short name T655
Test name
Test status
Simulation time 21331872 ps
CPU time 0.57 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:34 PM PDT 24
Peak memory 193396 kb
Host smart-3b827a3d-3e93-4ebf-b1e1-d4038ca5a68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238791688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3238791688
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2282858017
Short name T668
Test name
Test status
Simulation time 26349092 ps
CPU time 0.81 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:43:33 PM PDT 24
Peak memory 195404 kb
Host smart-9dc647bf-3078-42d8-b478-0d29a45486df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282858017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2282858017
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.321540693
Short name T424
Test name
Test status
Simulation time 926019217 ps
CPU time 25.4 seconds
Started Jun 06 12:43:36 PM PDT 24
Finished Jun 06 12:44:02 PM PDT 24
Peak memory 195400 kb
Host smart-fe3f034a-5284-44b7-a4d0-95e4d2f6eb3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321540693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.321540693
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.983043081
Short name T213
Test name
Test status
Simulation time 65696294 ps
CPU time 0.81 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 196064 kb
Host smart-ee0649a9-52af-4c9d-b047-0f0ed28c55dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983043081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.983043081
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3408302389
Short name T433
Test name
Test status
Simulation time 27770731 ps
CPU time 0.71 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:35 PM PDT 24
Peak memory 194352 kb
Host smart-62ccd17f-54c4-4ad0-beb5-ce62d1c1eb23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408302389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3408302389
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3530350014
Short name T641
Test name
Test status
Simulation time 70495277 ps
CPU time 2.85 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 197964 kb
Host smart-cdee264a-741a-4125-ac1c-ce5fdd7490ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530350014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3530350014
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.284676674
Short name T97
Test name
Test status
Simulation time 305618219 ps
CPU time 1.96 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:37 PM PDT 24
Peak memory 195912 kb
Host smart-564ca97f-67af-46d5-8696-07ce7e538966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284676674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.284676674
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3497086820
Short name T579
Test name
Test status
Simulation time 34043834 ps
CPU time 0.93 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:43:33 PM PDT 24
Peak memory 195284 kb
Host smart-82a163e9-4533-495a-a323-ab991751ee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497086820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3497086820
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3470510826
Short name T240
Test name
Test status
Simulation time 21089947 ps
CPU time 0.86 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:34 PM PDT 24
Peak memory 195876 kb
Host smart-164fba33-91b7-4e2d-a2ee-8327b56fa4c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470510826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3470510826
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.400980493
Short name T460
Test name
Test status
Simulation time 111303126 ps
CPU time 5.07 seconds
Started Jun 06 12:43:32 PM PDT 24
Finished Jun 06 12:43:38 PM PDT 24
Peak memory 197840 kb
Host smart-312e7fc5-78eb-4427-a2c8-5d9a54ee951d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400980493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.400980493
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.987019484
Short name T275
Test name
Test status
Simulation time 243629835 ps
CPU time 1.2 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:35 PM PDT 24
Peak memory 195728 kb
Host smart-33207d0f-d556-484e-809a-3fb49a8452c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987019484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.987019484
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.106508807
Short name T219
Test name
Test status
Simulation time 91127943 ps
CPU time 1.42 seconds
Started Jun 06 12:43:33 PM PDT 24
Finished Jun 06 12:43:36 PM PDT 24
Peak memory 196600 kb
Host smart-4a5ca10a-bedf-4bf6-bb70-8cb6fc606541
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106508807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.106508807
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.12726386
Short name T317
Test name
Test status
Simulation time 19617958389 ps
CPU time 136.08 seconds
Started Jun 06 12:43:34 PM PDT 24
Finished Jun 06 12:45:51 PM PDT 24
Peak memory 198060 kb
Host smart-a3ba78e7-7b0e-4574-80e6-51d7cd291e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpi
o_stress_all.12726386
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3417172834
Short name T322
Test name
Test status
Simulation time 160319544 ps
CPU time 0.58 seconds
Started Jun 06 12:43:54 PM PDT 24
Finished Jun 06 12:43:55 PM PDT 24
Peak memory 194520 kb
Host smart-79a5a3d9-c94d-4cb2-83a0-3d2fcc1d2e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417172834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3417172834
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3682520591
Short name T24
Test name
Test status
Simulation time 113273407 ps
CPU time 0.89 seconds
Started Jun 06 12:43:50 PM PDT 24
Finished Jun 06 12:43:51 PM PDT 24
Peak memory 195768 kb
Host smart-1c0d5377-5430-4ddf-9296-ff12e12ded05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682520591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3682520591
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3493701865
Short name T697
Test name
Test status
Simulation time 2864786870 ps
CPU time 21.11 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:44:09 PM PDT 24
Peak memory 198084 kb
Host smart-14cb19fc-51eb-481d-857d-ee3b5aad0211
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493701865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3493701865
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2914563661
Short name T496
Test name
Test status
Simulation time 116912503 ps
CPU time 0.74 seconds
Started Jun 06 12:43:46 PM PDT 24
Finished Jun 06 12:43:48 PM PDT 24
Peak memory 196508 kb
Host smart-b321e4bd-8d09-4b88-8613-32260741a647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914563661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2914563661
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.877937222
Short name T249
Test name
Test status
Simulation time 34309941 ps
CPU time 1.02 seconds
Started Jun 06 12:43:50 PM PDT 24
Finished Jun 06 12:43:52 PM PDT 24
Peak memory 196680 kb
Host smart-9a768074-e156-44bc-a1bb-4123080e2d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877937222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.877937222
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2167525136
Short name T437
Test name
Test status
Simulation time 228468092 ps
CPU time 2.6 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:51 PM PDT 24
Peak memory 197924 kb
Host smart-50dd5ce2-5ce1-435c-9613-6997069de926
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167525136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2167525136
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2856467577
Short name T517
Test name
Test status
Simulation time 636985628 ps
CPU time 3.01 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:52 PM PDT 24
Peak memory 198060 kb
Host smart-c00bca17-ce4a-4286-9178-5f0cb44432d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856467577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2856467577
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2201583043
Short name T408
Test name
Test status
Simulation time 42376274 ps
CPU time 1.09 seconds
Started Jun 06 12:43:48 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 196580 kb
Host smart-c17980b2-d493-470a-bc6d-ca61003d5dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201583043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2201583043
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3446941951
Short name T348
Test name
Test status
Simulation time 26037015 ps
CPU time 0.72 seconds
Started Jun 06 12:43:49 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 196108 kb
Host smart-d701fd7f-1976-4588-b3d7-d77d6b017a5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446941951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3446941951
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.4134725329
Short name T663
Test name
Test status
Simulation time 613327905 ps
CPU time 4.03 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:52 PM PDT 24
Peak memory 197840 kb
Host smart-617f634c-041d-45b4-8764-9bfbea68000d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134725329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.4134725329
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2719601798
Short name T494
Test name
Test status
Simulation time 211946606 ps
CPU time 1.35 seconds
Started Jun 06 12:43:47 PM PDT 24
Finished Jun 06 12:43:50 PM PDT 24
Peak memory 196640 kb
Host smart-1705a8bc-db17-4679-82dc-e6b1e64e8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719601798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2719601798
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.181146712
Short name T283
Test name
Test status
Simulation time 76426152 ps
CPU time 1.13 seconds
Started Jun 06 12:43:49 PM PDT 24
Finished Jun 06 12:43:51 PM PDT 24
Peak memory 195512 kb
Host smart-adf2eff0-70d2-4121-9157-efde1e1619f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181146712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.181146712
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1129229111
Short name T716
Test name
Test status
Simulation time 7159389380 ps
CPU time 45.77 seconds
Started Jun 06 12:43:49 PM PDT 24
Finished Jun 06 12:44:35 PM PDT 24
Peak memory 198108 kb
Host smart-b13e6875-a1fd-4a47-a34a-35212e929109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129229111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1129229111
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2396087537
Short name T670
Test name
Test status
Simulation time 165883546863 ps
CPU time 1001.3 seconds
Started Jun 06 12:43:49 PM PDT 24
Finished Jun 06 01:00:31 PM PDT 24
Peak memory 198260 kb
Host smart-cf449abc-fbe2-4717-86e4-0638e02ac9c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2396087537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2396087537
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3570805227
Short name T896
Test name
Test status
Simulation time 41514066 ps
CPU time 0.82 seconds
Started Jun 06 12:42:38 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 196404 kb
Host smart-30388bf8-4e8a-4c32-8ac3-337a1cbd3ef6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3570805227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3570805227
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2909828409
Short name T927
Test name
Test status
Simulation time 164511476 ps
CPU time 1.34 seconds
Started Jun 06 12:42:38 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 197008 kb
Host smart-cb5b30a0-727e-47da-87e2-5b66114fbe2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909828409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2909828409
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2543804889
Short name T849
Test name
Test status
Simulation time 43925794 ps
CPU time 0.91 seconds
Started Jun 06 12:42:38 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 195820 kb
Host smart-3752847f-75b2-4e9d-a320-be2c16c2ae24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2543804889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2543804889
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3054106795
Short name T847
Test name
Test status
Simulation time 116884726 ps
CPU time 1.31 seconds
Started Jun 06 12:42:37 PM PDT 24
Finished Jun 06 12:42:39 PM PDT 24
Peak memory 198064 kb
Host smart-f4143a89-019e-4cc8-9474-b6f1f59835c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054106795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3054106795
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.751535787
Short name T842
Test name
Test status
Simulation time 58943952 ps
CPU time 1.17 seconds
Started Jun 06 12:42:51 PM PDT 24
Finished Jun 06 12:42:53 PM PDT 24
Peak memory 197028 kb
Host smart-d9a16cf7-4ff6-48ee-ab39-3b8a2fa0e858
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=751535787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.751535787
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4293367153
Short name T912
Test name
Test status
Simulation time 218374865 ps
CPU time 1.03 seconds
Started Jun 06 12:42:42 PM PDT 24
Finished Jun 06 12:42:44 PM PDT 24
Peak memory 196856 kb
Host smart-9b657ab3-41bc-403f-bdb8-9859f70f9116
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293367153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4293367153
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3867177485
Short name T905
Test name
Test status
Simulation time 153803315 ps
CPU time 0.96 seconds
Started Jun 06 12:42:45 PM PDT 24
Finished Jun 06 12:42:48 PM PDT 24
Peak memory 196548 kb
Host smart-a24452e8-9e07-4428-a88d-9a382f981bbf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3867177485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3867177485
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3625461039
Short name T850
Test name
Test status
Simulation time 67485558 ps
CPU time 1.31 seconds
Started Jun 06 12:42:44 PM PDT 24
Finished Jun 06 12:42:47 PM PDT 24
Peak memory 197212 kb
Host smart-b65f49c3-05b9-4763-9ca5-25218974c720
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625461039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3625461039
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1977278509
Short name T913
Test name
Test status
Simulation time 43039080 ps
CPU time 1.26 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 195752 kb
Host smart-7cc1a5a7-74e5-4877-ba0e-96e525bc5aa8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1977278509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1977278509
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.886984489
Short name T911
Test name
Test status
Simulation time 180838860 ps
CPU time 1.36 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:45 PM PDT 24
Peak memory 196444 kb
Host smart-da43c03a-6390-4e78-86bf-84fcade886a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886984489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.886984489
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1501674112
Short name T853
Test name
Test status
Simulation time 204062906 ps
CPU time 1 seconds
Started Jun 06 12:42:49 PM PDT 24
Finished Jun 06 12:42:51 PM PDT 24
Peak memory 196648 kb
Host smart-e1452982-3d90-4445-aa31-763e640fe697
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1501674112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1501674112
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.919974499
Short name T863
Test name
Test status
Simulation time 449673100 ps
CPU time 1.35 seconds
Started Jun 06 12:42:49 PM PDT 24
Finished Jun 06 12:42:51 PM PDT 24
Peak memory 196704 kb
Host smart-87e335bf-cef2-494a-bea0-cab515fd7214
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919974499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.919974499
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1074902217
Short name T933
Test name
Test status
Simulation time 40357447 ps
CPU time 1.22 seconds
Started Jun 06 12:42:45 PM PDT 24
Finished Jun 06 12:42:48 PM PDT 24
Peak memory 196708 kb
Host smart-033c82ff-6e96-4f98-aa5c-1994ab4c9217
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1074902217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1074902217
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2216216773
Short name T923
Test name
Test status
Simulation time 219747193 ps
CPU time 1.1 seconds
Started Jun 06 12:42:39 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 196688 kb
Host smart-74cec66a-9ae2-4d8f-b7ca-f7c082035dc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216216773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2216216773
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.244132866
Short name T846
Test name
Test status
Simulation time 132511746 ps
CPU time 0.78 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 195668 kb
Host smart-e6b64379-13b4-4349-a08f-b3af52c4670a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=244132866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.244132866
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2965629742
Short name T857
Test name
Test status
Simulation time 42300356 ps
CPU time 0.69 seconds
Started Jun 06 12:42:44 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 194468 kb
Host smart-c21e376c-d683-4ed5-9fd1-c5d5c1f33025
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965629742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2965629742
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1020466042
Short name T939
Test name
Test status
Simulation time 315301720 ps
CPU time 1.5 seconds
Started Jun 06 12:42:42 PM PDT 24
Finished Jun 06 12:42:45 PM PDT 24
Peak memory 197060 kb
Host smart-0e6103af-cf2f-40bd-8b8d-3a88a0d56071
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1020466042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1020466042
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1215158479
Short name T868
Test name
Test status
Simulation time 88750368 ps
CPU time 1.27 seconds
Started Jun 06 12:42:45 PM PDT 24
Finished Jun 06 12:42:48 PM PDT 24
Peak memory 198104 kb
Host smart-35b5b0ef-5eb4-47fb-b633-b6b0389fce81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215158479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1215158479
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2773730087
Short name T872
Test name
Test status
Simulation time 29059762 ps
CPU time 0.84 seconds
Started Jun 06 12:42:45 PM PDT 24
Finished Jun 06 12:42:48 PM PDT 24
Peak memory 195456 kb
Host smart-2f988c1a-e65d-4f7d-9a1f-19af3391cd5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2773730087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2773730087
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.185672719
Short name T878
Test name
Test status
Simulation time 55684096 ps
CPU time 1.19 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 195952 kb
Host smart-618af42f-de5f-42b3-baaa-48c4c6b8db37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185672719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.185672719
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3659717616
Short name T903
Test name
Test status
Simulation time 174395006 ps
CPU time 1.48 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 198216 kb
Host smart-d8c63954-b95f-49e1-b3ea-6365b04bb24a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3659717616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3659717616
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3516726764
Short name T910
Test name
Test status
Simulation time 54970574 ps
CPU time 0.99 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:45 PM PDT 24
Peak memory 195852 kb
Host smart-f61f407f-4482-44d2-8b8f-ce4d3d077145
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516726764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3516726764
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2978384183
Short name T874
Test name
Test status
Simulation time 23560520 ps
CPU time 0.8 seconds
Started Jun 06 12:42:53 PM PDT 24
Finished Jun 06 12:42:55 PM PDT 24
Peak memory 195700 kb
Host smart-37476dd2-6f15-4b4d-b264-637ec241d813
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978384183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2978384183
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1192957850
Short name T851
Test name
Test status
Simulation time 68685276 ps
CPU time 1.18 seconds
Started Jun 06 12:42:51 PM PDT 24
Finished Jun 06 12:42:53 PM PDT 24
Peak memory 198008 kb
Host smart-f3cea8ce-3e8d-4787-a388-ce71dbb04717
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192957850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1192957850
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3828267726
Short name T895
Test name
Test status
Simulation time 427569403 ps
CPU time 1.02 seconds
Started Jun 06 12:42:37 PM PDT 24
Finished Jun 06 12:42:39 PM PDT 24
Peak memory 196668 kb
Host smart-e4a92d58-2a55-4382-8707-b1da324b14ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3828267726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3828267726
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2793204867
Short name T918
Test name
Test status
Simulation time 46552644 ps
CPU time 1.07 seconds
Started Jun 06 12:42:38 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 195848 kb
Host smart-6704d653-d293-46c6-ba19-f08a4b8963ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793204867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2793204867
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2549087717
Short name T879
Test name
Test status
Simulation time 112195795 ps
CPU time 1.06 seconds
Started Jun 06 12:42:55 PM PDT 24
Finished Jun 06 12:42:57 PM PDT 24
Peak memory 196700 kb
Host smart-e11b2b4d-01b3-4a40-859c-f42f89bc938e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2549087717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2549087717
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3111930277
Short name T907
Test name
Test status
Simulation time 307227146 ps
CPU time 1.37 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:57 PM PDT 24
Peak memory 196972 kb
Host smart-981854d4-47f1-4966-846c-9d824257cc19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111930277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3111930277
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1033699062
Short name T925
Test name
Test status
Simulation time 82324779 ps
CPU time 1.56 seconds
Started Jun 06 12:42:53 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 196752 kb
Host smart-03489090-ac0d-4ac9-b662-a1ad9cec2e09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1033699062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1033699062
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3435633799
Short name T934
Test name
Test status
Simulation time 688715985 ps
CPU time 1.45 seconds
Started Jun 06 12:43:00 PM PDT 24
Finished Jun 06 12:43:02 PM PDT 24
Peak memory 196408 kb
Host smart-cb7d2577-55f9-4990-aee8-a5d2dfd8a438
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435633799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3435633799
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1006178346
Short name T924
Test name
Test status
Simulation time 165573519 ps
CPU time 1.28 seconds
Started Jun 06 12:42:57 PM PDT 24
Finished Jun 06 12:42:59 PM PDT 24
Peak memory 195844 kb
Host smart-740dc5ee-8829-4de4-b5d5-382c59e605e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1006178346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1006178346
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466624347
Short name T886
Test name
Test status
Simulation time 57276433 ps
CPU time 1.12 seconds
Started Jun 06 12:43:21 PM PDT 24
Finished Jun 06 12:43:22 PM PDT 24
Peak memory 198236 kb
Host smart-9219e2e5-964e-4c41-8550-9f81cd7e57bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466624347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2466624347
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3569228401
Short name T936
Test name
Test status
Simulation time 76623832 ps
CPU time 1.18 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 196840 kb
Host smart-299ff2e9-71a9-4cc8-916e-3ca7a5567303
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3569228401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3569228401
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1134234268
Short name T898
Test name
Test status
Simulation time 76649608 ps
CPU time 1.31 seconds
Started Jun 06 12:42:57 PM PDT 24
Finished Jun 06 12:42:59 PM PDT 24
Peak memory 196832 kb
Host smart-0d5b45f7-d57d-4d3c-8fc6-e295db8ecfa1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134234268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1134234268
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1193523703
Short name T921
Test name
Test status
Simulation time 161292846 ps
CPU time 1.33 seconds
Started Jun 06 12:42:53 PM PDT 24
Finished Jun 06 12:42:55 PM PDT 24
Peak memory 196864 kb
Host smart-18cdabc7-7397-411a-815e-064d5af0ca2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1193523703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1193523703
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3031364629
Short name T917
Test name
Test status
Simulation time 49444287 ps
CPU time 0.81 seconds
Started Jun 06 12:42:57 PM PDT 24
Finished Jun 06 12:42:59 PM PDT 24
Peak memory 196460 kb
Host smart-dce5bfb1-01e6-4211-9258-fa2a668b461f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031364629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3031364629
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2294984049
Short name T902
Test name
Test status
Simulation time 54451389 ps
CPU time 1.04 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 196760 kb
Host smart-a91521bb-6440-4579-8896-85683d1b9c29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2294984049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2294984049
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032152953
Short name T854
Test name
Test status
Simulation time 59088452 ps
CPU time 1.19 seconds
Started Jun 06 12:42:55 PM PDT 24
Finished Jun 06 12:42:57 PM PDT 24
Peak memory 196108 kb
Host smart-04cace04-964b-419a-97ea-b3e72fbc2a68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032152953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2032152953
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3920492537
Short name T862
Test name
Test status
Simulation time 383473333 ps
CPU time 0.94 seconds
Started Jun 06 12:42:57 PM PDT 24
Finished Jun 06 12:42:58 PM PDT 24
Peak memory 196844 kb
Host smart-91115c7e-9d32-4c10-aea6-c259a181b58a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3920492537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3920492537
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1310559022
Short name T926
Test name
Test status
Simulation time 37606799 ps
CPU time 1.13 seconds
Started Jun 06 12:42:53 PM PDT 24
Finished Jun 06 12:42:55 PM PDT 24
Peak memory 196052 kb
Host smart-f48b1708-bf01-4bb4-8110-0be6cd4c91ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310559022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1310559022
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2018089348
Short name T844
Test name
Test status
Simulation time 152421321 ps
CPU time 1.3 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 196744 kb
Host smart-cff76195-35f0-414b-8ee6-e1feba40551b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2018089348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2018089348
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3730141602
Short name T892
Test name
Test status
Simulation time 218498295 ps
CPU time 1.17 seconds
Started Jun 06 12:42:52 PM PDT 24
Finished Jun 06 12:42:54 PM PDT 24
Peak memory 196604 kb
Host smart-a8ca1268-ec42-4217-9a33-b906ff445bda
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730141602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3730141602
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1652334010
Short name T845
Test name
Test status
Simulation time 93729649 ps
CPU time 1.33 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 197380 kb
Host smart-296a9951-7a87-4a76-908c-e473bdb3434c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1652334010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1652334010
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2821311682
Short name T887
Test name
Test status
Simulation time 124519346 ps
CPU time 0.84 seconds
Started Jun 06 12:42:55 PM PDT 24
Finished Jun 06 12:42:57 PM PDT 24
Peak memory 195560 kb
Host smart-166274b3-e785-4bfd-9b2f-792a0ffcc985
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821311682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2821311682
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.710578187
Short name T866
Test name
Test status
Simulation time 149366971 ps
CPU time 1.12 seconds
Started Jun 06 12:42:52 PM PDT 24
Finished Jun 06 12:42:54 PM PDT 24
Peak memory 196744 kb
Host smart-a600133a-46d4-4c46-be57-ca51b5a9ad28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=710578187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.710578187
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837405366
Short name T873
Test name
Test status
Simulation time 107552825 ps
CPU time 1.27 seconds
Started Jun 06 12:42:52 PM PDT 24
Finished Jun 06 12:42:54 PM PDT 24
Peak memory 197204 kb
Host smart-c013eeac-2f1c-450b-9323-30fe0ea822cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837405366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.837405366
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3798816449
Short name T928
Test name
Test status
Simulation time 71035124 ps
CPU time 0.93 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 196692 kb
Host smart-ac958d7f-5a55-4e91-88bb-33e880cf5a6d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3798816449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3798816449
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3134082183
Short name T935
Test name
Test status
Simulation time 575938570 ps
CPU time 0.98 seconds
Started Jun 06 12:42:41 PM PDT 24
Finished Jun 06 12:42:43 PM PDT 24
Peak memory 196612 kb
Host smart-9fb89d45-60f1-4e1a-b54e-4bd519edec47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134082183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3134082183
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2106555987
Short name T852
Test name
Test status
Simulation time 35983106 ps
CPU time 0.96 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 196684 kb
Host smart-864f9f9a-94f8-420f-a958-4865aac876a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2106555987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2106555987
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.41909209
Short name T897
Test name
Test status
Simulation time 140217506 ps
CPU time 1.35 seconds
Started Jun 06 12:42:55 PM PDT 24
Finished Jun 06 12:42:57 PM PDT 24
Peak memory 198200 kb
Host smart-18a50c28-bf8d-44e8-9471-e5b48a1f6456
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41909209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.41909209
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.835309985
Short name T883
Test name
Test status
Simulation time 37034810 ps
CPU time 1.04 seconds
Started Jun 06 12:42:55 PM PDT 24
Finished Jun 06 12:42:57 PM PDT 24
Peak memory 197024 kb
Host smart-f0e34c19-22bd-47ca-9ff6-465c65f9448d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=835309985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.835309985
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1349475066
Short name T877
Test name
Test status
Simulation time 35092702 ps
CPU time 1.18 seconds
Started Jun 06 12:42:56 PM PDT 24
Finished Jun 06 12:42:58 PM PDT 24
Peak memory 196828 kb
Host smart-c29a83ae-fd5a-459c-be15-323bf96f8a8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349475066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1349475066
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1171257028
Short name T856
Test name
Test status
Simulation time 354364531 ps
CPU time 0.92 seconds
Started Jun 06 12:42:56 PM PDT 24
Finished Jun 06 12:42:58 PM PDT 24
Peak memory 196640 kb
Host smart-fb93d54c-aabd-4095-bdc2-bd444834cab9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1171257028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1171257028
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.549115309
Short name T941
Test name
Test status
Simulation time 281527339 ps
CPU time 1.22 seconds
Started Jun 06 12:42:53 PM PDT 24
Finished Jun 06 12:42:55 PM PDT 24
Peak memory 195816 kb
Host smart-4e946ef0-50a2-459c-ad69-b7750742c077
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549115309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.549115309
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.255856962
Short name T899
Test name
Test status
Simulation time 181370499 ps
CPU time 1 seconds
Started Jun 06 12:42:52 PM PDT 24
Finished Jun 06 12:42:54 PM PDT 24
Peak memory 196576 kb
Host smart-51a89c6c-fb3d-4bd0-8cc7-fa049792ca25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=255856962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.255856962
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3455447634
Short name T881
Test name
Test status
Simulation time 254758063 ps
CPU time 1.37 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 198172 kb
Host smart-977fe291-b613-40da-bdb8-705be9794c89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455447634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3455447634
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3082322543
Short name T916
Test name
Test status
Simulation time 101941506 ps
CPU time 1.21 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 196924 kb
Host smart-8378d5e1-fd19-4573-9a84-ad6991ad2286
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3082322543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3082322543
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2365170662
Short name T890
Test name
Test status
Simulation time 101189767 ps
CPU time 1.01 seconds
Started Jun 06 12:42:54 PM PDT 24
Finished Jun 06 12:42:56 PM PDT 24
Peak memory 195976 kb
Host smart-721e2809-a255-4ff4-8e2a-9f46d68681f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365170662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2365170662
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2224847743
Short name T888
Test name
Test status
Simulation time 188241064 ps
CPU time 1.35 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:07 PM PDT 24
Peak memory 196876 kb
Host smart-087da13c-28b5-41e6-838e-5f74faec821f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2224847743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2224847743
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1697194284
Short name T930
Test name
Test status
Simulation time 49735730 ps
CPU time 1.25 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:05 PM PDT 24
Peak memory 196880 kb
Host smart-4fbc8e95-8acd-4e80-a73f-5d537f1ad13e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697194284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1697194284
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2286465739
Short name T915
Test name
Test status
Simulation time 38427653 ps
CPU time 1.18 seconds
Started Jun 06 12:43:03 PM PDT 24
Finished Jun 06 12:43:04 PM PDT 24
Peak memory 196712 kb
Host smart-261344ec-2db9-408f-bf53-29ad353ad31f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2286465739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2286465739
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1566859411
Short name T914
Test name
Test status
Simulation time 147816715 ps
CPU time 1.26 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:07 PM PDT 24
Peak memory 196760 kb
Host smart-777b1ee3-2e6b-4df8-8dc1-485366ba95c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566859411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1566859411
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3577006461
Short name T938
Test name
Test status
Simulation time 124375503 ps
CPU time 1.22 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:06 PM PDT 24
Peak memory 197148 kb
Host smart-d5c7eaae-56e5-4bad-8508-03edd5b08e21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3577006461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3577006461
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2578198149
Short name T882
Test name
Test status
Simulation time 375175914 ps
CPU time 0.92 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:06 PM PDT 24
Peak memory 196736 kb
Host smart-9c17ed80-3eb0-4074-a601-a7d74df33846
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578198149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2578198149
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2285686149
Short name T884
Test name
Test status
Simulation time 30806520 ps
CPU time 0.92 seconds
Started Jun 06 12:43:02 PM PDT 24
Finished Jun 06 12:43:04 PM PDT 24
Peak memory 196536 kb
Host smart-16d725f2-3b1c-4c27-bac3-3985abc53773
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2285686149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2285686149
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126870029
Short name T861
Test name
Test status
Simulation time 102261844 ps
CPU time 1.2 seconds
Started Jun 06 12:43:10 PM PDT 24
Finished Jun 06 12:43:12 PM PDT 24
Peak memory 196016 kb
Host smart-dabdc364-444a-4446-b435-4b535a9b9660
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126870029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4126870029
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3953122521
Short name T906
Test name
Test status
Simulation time 57384618 ps
CPU time 0.99 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:06 PM PDT 24
Peak memory 195800 kb
Host smart-81472d9c-e2ab-4acd-b1fd-52720ce04865
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3953122521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3953122521
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1669975333
Short name T929
Test name
Test status
Simulation time 143976075 ps
CPU time 1.23 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:06 PM PDT 24
Peak memory 195964 kb
Host smart-eef45aeb-e489-45ab-8bcb-289175129271
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669975333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1669975333
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.631186598
Short name T858
Test name
Test status
Simulation time 187299665 ps
CPU time 1.24 seconds
Started Jun 06 12:42:37 PM PDT 24
Finished Jun 06 12:42:39 PM PDT 24
Peak memory 196836 kb
Host smart-8aad8d62-b298-40ef-8d12-6d187d9a8477
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=631186598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.631186598
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.624101562
Short name T869
Test name
Test status
Simulation time 34070234 ps
CPU time 0.84 seconds
Started Jun 06 12:42:38 PM PDT 24
Finished Jun 06 12:42:40 PM PDT 24
Peak memory 196288 kb
Host smart-26d08f42-c0bd-4cc6-a18d-368cd6e5ef57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624101562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.624101562
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2908126165
Short name T932
Test name
Test status
Simulation time 37094607 ps
CPU time 0.99 seconds
Started Jun 06 12:43:03 PM PDT 24
Finished Jun 06 12:43:05 PM PDT 24
Peak memory 196920 kb
Host smart-e3f704c2-e961-4474-bf8a-338ea74d7298
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2908126165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2908126165
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.510317454
Short name T875
Test name
Test status
Simulation time 90708719 ps
CPU time 1.3 seconds
Started Jun 06 12:43:03 PM PDT 24
Finished Jun 06 12:43:05 PM PDT 24
Peak memory 196980 kb
Host smart-4a993747-7c0b-4100-a49a-045f89b6ac13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510317454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.510317454
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1583570505
Short name T909
Test name
Test status
Simulation time 23752596 ps
CPU time 0.82 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:06 PM PDT 24
Peak memory 195600 kb
Host smart-bcca0f42-3329-4d21-ba91-8ca27106401e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1583570505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1583570505
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.948868406
Short name T865
Test name
Test status
Simulation time 66464208 ps
CPU time 1.07 seconds
Started Jun 06 12:43:07 PM PDT 24
Finished Jun 06 12:43:09 PM PDT 24
Peak memory 196568 kb
Host smart-2cc755e4-f366-4a78-a9e9-26c673cd4dd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948868406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.948868406
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1308605983
Short name T885
Test name
Test status
Simulation time 65548032 ps
CPU time 1.15 seconds
Started Jun 06 12:43:02 PM PDT 24
Finished Jun 06 12:43:03 PM PDT 24
Peak memory 196788 kb
Host smart-d63199dd-a988-49f7-928b-c6a5e62470d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1308605983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1308605983
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.276236841
Short name T859
Test name
Test status
Simulation time 29694426 ps
CPU time 0.96 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:07 PM PDT 24
Peak memory 198040 kb
Host smart-8c3eabbc-1a28-41b8-b8fa-cdb6237a1cce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276236841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.276236841
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2627178608
Short name T864
Test name
Test status
Simulation time 284827074 ps
CPU time 1.3 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:07 PM PDT 24
Peak memory 198152 kb
Host smart-2012546b-ffda-4181-b5db-4759f61f73e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2627178608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2627178608
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2668879590
Short name T900
Test name
Test status
Simulation time 285759202 ps
CPU time 1.51 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 196964 kb
Host smart-e52aa732-d70a-4900-8a14-2b3cc413536a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668879590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2668879590
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3583431056
Short name T855
Test name
Test status
Simulation time 81534450 ps
CPU time 1.28 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 196912 kb
Host smart-1fbf7d3a-09b4-4338-94bb-1e26cf93f623
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3583431056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3583431056
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1201011896
Short name T893
Test name
Test status
Simulation time 41239579 ps
CPU time 1.05 seconds
Started Jun 06 12:43:03 PM PDT 24
Finished Jun 06 12:43:04 PM PDT 24
Peak memory 196528 kb
Host smart-af1c9cce-204d-4375-ad7e-a8043ed38bb5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201011896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1201011896
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2803597424
Short name T848
Test name
Test status
Simulation time 50658443 ps
CPU time 1.4 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 198216 kb
Host smart-b0d357ce-c145-4bea-bdbe-71a054a42ae1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2803597424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2803597424
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1541651390
Short name T931
Test name
Test status
Simulation time 42297358 ps
CPU time 0.88 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:06 PM PDT 24
Peak memory 195704 kb
Host smart-d838f4ee-c1ae-457b-b211-756bcbd3fb35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541651390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1541651390
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3214439184
Short name T937
Test name
Test status
Simulation time 567397122 ps
CPU time 1.37 seconds
Started Jun 06 12:43:02 PM PDT 24
Finished Jun 06 12:43:04 PM PDT 24
Peak memory 196604 kb
Host smart-1050e961-0256-4bc7-8845-ca80c742bbcc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3214439184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3214439184
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3274432424
Short name T871
Test name
Test status
Simulation time 196202651 ps
CPU time 1.06 seconds
Started Jun 06 12:43:05 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 196044 kb
Host smart-0e7c0631-5b89-45f8-947a-a50bc1f232e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274432424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3274432424
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2489737337
Short name T940
Test name
Test status
Simulation time 36686170 ps
CPU time 0.91 seconds
Started Jun 06 12:43:06 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 197616 kb
Host smart-417ef2dc-2f55-4613-9ff4-6ff96c81e3ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2489737337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2489737337
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3643450426
Short name T894
Test name
Test status
Simulation time 115687732 ps
CPU time 1.31 seconds
Started Jun 06 12:43:10 PM PDT 24
Finished Jun 06 12:43:12 PM PDT 24
Peak memory 196832 kb
Host smart-8bdfa4ea-9021-4a6d-8b2e-ff29e5678787
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643450426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3643450426
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.731509100
Short name T843
Test name
Test status
Simulation time 42214996 ps
CPU time 0.88 seconds
Started Jun 06 12:43:04 PM PDT 24
Finished Jun 06 12:43:05 PM PDT 24
Peak memory 196432 kb
Host smart-a5bb35ea-982f-48ad-8eb8-736579d8e5a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=731509100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.731509100
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.45086963
Short name T889
Test name
Test status
Simulation time 35948818 ps
CPU time 0.95 seconds
Started Jun 06 12:43:06 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 195752 kb
Host smart-174c50fb-dd68-4ca7-ae61-57f68a5148b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45086963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.45086963
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4062856702
Short name T904
Test name
Test status
Simulation time 162115691 ps
CPU time 1.14 seconds
Started Jun 06 12:43:06 PM PDT 24
Finished Jun 06 12:43:08 PM PDT 24
Peak memory 196720 kb
Host smart-fc615507-102d-45e9-b428-0b2b749308a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4062856702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4062856702
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138297578
Short name T922
Test name
Test status
Simulation time 88049252 ps
CPU time 0.8 seconds
Started Jun 06 12:43:03 PM PDT 24
Finished Jun 06 12:43:05 PM PDT 24
Peak memory 195148 kb
Host smart-9e834944-b86a-4caf-b582-5973958a773d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138297578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.138297578
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3813385146
Short name T919
Test name
Test status
Simulation time 177400842 ps
CPU time 1.11 seconds
Started Jun 06 12:42:35 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 196756 kb
Host smart-b2e51b65-76d7-4fba-943f-1adf7881ce0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3813385146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3813385146
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2151002776
Short name T860
Test name
Test status
Simulation time 48821358 ps
CPU time 1.35 seconds
Started Jun 06 12:42:36 PM PDT 24
Finished Jun 06 12:42:38 PM PDT 24
Peak memory 198196 kb
Host smart-0fbe9631-dbe4-4f4a-a51d-bf8b6c1bde2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151002776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2151002776
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1916885218
Short name T870
Test name
Test status
Simulation time 103782154 ps
CPU time 1.46 seconds
Started Jun 06 12:42:45 PM PDT 24
Finished Jun 06 12:42:48 PM PDT 24
Peak memory 196804 kb
Host smart-c5620c75-fed1-46f4-97f9-5e1cdf250ff0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1916885218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1916885218
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2348443087
Short name T867
Test name
Test status
Simulation time 143619027 ps
CPU time 0.89 seconds
Started Jun 06 12:42:44 PM PDT 24
Finished Jun 06 12:42:47 PM PDT 24
Peak memory 195528 kb
Host smart-4e64ce3b-d767-42e4-8253-fb6b38bdbf52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348443087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2348443087
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1911015950
Short name T920
Test name
Test status
Simulation time 55342847 ps
CPU time 1.03 seconds
Started Jun 06 12:42:44 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 196740 kb
Host smart-69bef981-b659-45fd-8ccc-6ddcf4201513
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1911015950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1911015950
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1942951841
Short name T891
Test name
Test status
Simulation time 247186363 ps
CPU time 1.28 seconds
Started Jun 06 12:42:44 PM PDT 24
Finished Jun 06 12:42:47 PM PDT 24
Peak memory 198260 kb
Host smart-a169349d-9316-42da-b63e-fb9f3cfd0c19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942951841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1942951841
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3883833471
Short name T880
Test name
Test status
Simulation time 30975378 ps
CPU time 0.97 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:45 PM PDT 24
Peak memory 196548 kb
Host smart-82a84960-561a-4158-865d-0f3b56d9f9e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3883833471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3883833471
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.670922653
Short name T876
Test name
Test status
Simulation time 274785963 ps
CPU time 0.89 seconds
Started Jun 06 12:42:49 PM PDT 24
Finished Jun 06 12:42:51 PM PDT 24
Peak memory 196256 kb
Host smart-9a7c4bb4-29cb-424f-be6c-e637c2474abf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670922653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.670922653
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2949018331
Short name T901
Test name
Test status
Simulation time 40983592 ps
CPU time 1.09 seconds
Started Jun 06 12:42:50 PM PDT 24
Finished Jun 06 12:42:52 PM PDT 24
Peak memory 196616 kb
Host smart-0197e711-5aac-4c73-8374-030922fa8306
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2949018331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2949018331
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1156808150
Short name T908
Test name
Test status
Simulation time 35693397 ps
CPU time 1.08 seconds
Started Jun 06 12:42:43 PM PDT 24
Finished Jun 06 12:42:46 PM PDT 24
Peak memory 196724 kb
Host smart-57483aff-1cea-4623-a5b6-398f1843f789
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156808150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1156808150
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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