Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4717463	1			T23	1		T1	491		T11	766
all_pins[1]	4717463	1			T23	1		T1	491		T11	766
all_pins[2]	4717463	1			T23	1		T1	491		T11	766
all_pins[3]	4717463	1			T23	1		T1	491		T11	766
all_pins[4]	4717463	1			T23	1		T1	491		T11	766
all_pins[5]	4717463	1			T23	1		T1	491		T11	766
all_pins[6]	4717463	1			T23	1		T1	491		T11	766
all_pins[7]	4717463	1			T23	1		T1	491		T11	766
all_pins[8]	4717463	1			T23	1		T1	491		T11	766
all_pins[9]	4717463	1			T23	1		T1	491		T11	766
all_pins[10]	4717463	1			T23	1		T1	491		T11	766
all_pins[11]	4717463	1			T23	1		T1	491		T11	766
all_pins[12]	4717463	1			T23	1		T1	491		T11	766
all_pins[13]	4717463	1			T23	1		T1	491		T11	766
all_pins[14]	4717463	1			T23	1		T1	491		T11	766
all_pins[15]	4717463	1			T23	1		T1	491		T11	766
all_pins[16]	4717463	1			T23	1		T1	491		T11	766
all_pins[17]	4717463	1			T23	1		T1	491		T11	766
all_pins[18]	4717463	1			T23	1		T1	491		T11	766
all_pins[19]	4717463	1			T23	1		T1	491		T11	766
all_pins[20]	4717463	1			T23	1		T1	491		T11	766
all_pins[21]	4717463	1			T23	1		T1	491		T11	766
all_pins[22]	4717463	1			T23	1		T1	491		T11	766
all_pins[23]	4717463	1			T23	1		T1	491		T11	766
all_pins[24]	4717463	1			T23	1		T1	491		T11	766
all_pins[25]	4717463	1			T23	1		T1	491		T11	766
all_pins[26]	4717463	1			T23	1		T1	491		T11	766
all_pins[27]	4717463	1			T23	1		T1	491		T11	766
all_pins[28]	4717463	1			T23	1		T1	491		T11	766
all_pins[29]	4717463	1			T23	1		T1	491		T11	766
all_pins[30]	4717463	1			T23	1		T1	491		T11	766
all_pins[31]	4717463	1			T23	1		T1	491		T11	766

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	93739617	1			T23	32		T1	9869		T11	15205
values[0x1]	57219199	1			T1	5843		T11	9307		T12	1378
transitions[0x0=>0x1]	34277308	1			T1	3479		T11	5592		T12	832
transitions[0x1=>0x0]	34277154	1			T1	3479		T11	5592		T12	831

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2935412	1			T23	1		T1	268		T11	512
all_pins[0]	values[0x1]	1782051	1			T1	223		T11	254		T12	51
all_pins[0]	transitions[0x0=>0x1]	1103752	1			T1	170		T11	165		T12	41
all_pins[0]	transitions[0x1=>0x0]	1109593	1			T1	104		T11	245		T12	24
all_pins[1]	values[0x0]	2928804	1			T23	1		T1	287		T11	424
all_pins[1]	values[0x1]	1788659	1			T1	204		T11	342		T12	49
all_pins[1]	transitions[0x0=>0x1]	1075189	1			T1	106		T11	226		T12	22
all_pins[1]	transitions[0x1=>0x0]	1068581	1			T1	125		T11	138		T12	24
all_pins[2]	values[0x0]	2924149	1			T23	1		T1	261		T11	420
all_pins[2]	values[0x1]	1793314	1			T1	230		T11	346		T12	44
all_pins[2]	transitions[0x0=>0x1]	1073226	1			T1	126		T11	172		T12	23
all_pins[2]	transitions[0x1=>0x0]	1068571	1			T1	100		T11	168		T12	28
all_pins[3]	values[0x0]	2934161	1			T23	1		T1	317		T11	477
all_pins[3]	values[0x1]	1783302	1			T1	174		T11	289		T12	33
all_pins[3]	transitions[0x0=>0x1]	1063354	1			T1	72		T11	124		T12	19
all_pins[3]	transitions[0x1=>0x0]	1073366	1			T1	128		T11	181		T12	30
all_pins[4]	values[0x0]	2931296	1			T23	1		T1	328		T11	409
all_pins[4]	values[0x1]	1786167	1			T1	163		T11	357		T12	43
all_pins[4]	transitions[0x0=>0x1]	1070182	1			T1	106		T11	231		T12	34
all_pins[4]	transitions[0x1=>0x0]	1067317	1			T1	117		T11	163		T12	24
all_pins[5]	values[0x0]	2923122	1			T23	1		T1	286		T11	530
all_pins[5]	values[0x1]	1794341	1			T1	205		T11	236		T12	48
all_pins[5]	transitions[0x0=>0x1]	1073208	1			T1	134		T11	114		T12	22
all_pins[5]	transitions[0x1=>0x0]	1065034	1			T1	92		T11	235		T12	17
all_pins[6]	values[0x0]	2925373	1			T23	1		T1	294		T11	474
all_pins[6]	values[0x1]	1792090	1			T1	197		T11	292		T12	33
all_pins[6]	transitions[0x0=>0x1]	1068661	1			T1	125		T11	174		T12	20
all_pins[6]	transitions[0x1=>0x0]	1070912	1			T1	133		T11	118		T12	35
all_pins[7]	values[0x0]	2932934	1			T23	1		T1	316		T11	468
all_pins[7]	values[0x1]	1784529	1			T1	175		T11	298		T12	38
all_pins[7]	transitions[0x0=>0x1]	1065158	1			T1	98		T11	175		T12	26
all_pins[7]	transitions[0x1=>0x0]	1072719	1			T1	120		T11	169		T12	21
all_pins[8]	values[0x0]	2929355	1			T23	1		T1	357		T11	451
all_pins[8]	values[0x1]	1788108	1			T1	134		T11	315		T12	50
all_pins[8]	transitions[0x0=>0x1]	1070572	1			T1	87		T11	176		T12	38
all_pins[8]	transitions[0x1=>0x0]	1066993	1			T1	128		T11	159		T12	26
all_pins[9]	values[0x0]	2926505	1			T23	1		T1	340		T11	566
all_pins[9]	values[0x1]	1790958	1			T1	151		T11	200		T12	68
all_pins[9]	transitions[0x0=>0x1]	1069292	1			T1	97		T11	102		T12	42
all_pins[9]	transitions[0x1=>0x0]	1066442	1			T1	80		T11	217		T12	24
all_pins[10]	values[0x0]	2931634	1			T23	1		T1	365		T11	449
all_pins[10]	values[0x1]	1785829	1			T1	126		T11	317		T12	24
all_pins[10]	transitions[0x0=>0x1]	1068989	1			T1	89		T11	207		T12	7
all_pins[10]	transitions[0x1=>0x0]	1074118	1			T1	114		T11	90		T12	51
all_pins[11]	values[0x0]	2932499	1			T23	1		T1	355		T11	481
all_pins[11]	values[0x1]	1784964	1			T1	136		T11	285		T12	58
all_pins[11]	transitions[0x0=>0x1]	1064690	1			T1	85		T11	142		T12	43
all_pins[11]	transitions[0x1=>0x0]	1065555	1			T1	75		T11	174		T12	9
all_pins[12]	values[0x0]	2933698	1			T23	1		T1	365		T11	419
all_pins[12]	values[0x1]	1783765	1			T1	126		T11	347		T12	45
all_pins[12]	transitions[0x0=>0x1]	1069632	1			T1	79		T11	215		T12	12
all_pins[12]	transitions[0x1=>0x0]	1070831	1			T1	89		T11	153		T12	25
all_pins[13]	values[0x0]	2925768	1			T23	1		T1	354		T11	471
all_pins[13]	values[0x1]	1791695	1			T1	137		T11	295		T12	44
all_pins[13]	transitions[0x0=>0x1]	1073514	1			T1	91		T11	150		T12	19
all_pins[13]	transitions[0x1=>0x0]	1065584	1			T1	80		T11	202		T12	20
all_pins[14]	values[0x0]	2928407	1			T23	1		T1	299		T11	510
all_pins[14]	values[0x1]	1789056	1			T1	192		T11	256		T12	36
all_pins[14]	transitions[0x0=>0x1]	1068710	1			T1	131		T11	164		T12	23
all_pins[14]	transitions[0x1=>0x0]	1071349	1			T1	76		T11	203		T12	31
all_pins[15]	values[0x0]	2935331	1			T23	1		T1	283		T11	468
all_pins[15]	values[0x1]	1782132	1			T1	208		T11	298		T12	32
all_pins[15]	transitions[0x0=>0x1]	1068955	1			T1	105		T11	208		T12	15
all_pins[15]	transitions[0x1=>0x0]	1075879	1			T1	89		T11	166		T12	19
all_pins[16]	values[0x0]	2917775	1			T23	1		T1	275		T11	522
all_pins[16]	values[0x1]	1799688	1			T1	216		T11	244		T12	51
all_pins[16]	transitions[0x0=>0x1]	1083184	1			T1	127		T11	156		T12	40
all_pins[16]	transitions[0x1=>0x0]	1065628	1			T1	119		T11	210		T12	21
all_pins[17]	values[0x0]	2936423	1			T23	1		T1	309		T11	467
all_pins[17]	values[0x1]	1781040	1			T1	182		T11	299		T12	45
all_pins[17]	transitions[0x0=>0x1]	1060221	1			T1	113		T11	243		T12	30
all_pins[17]	transitions[0x1=>0x0]	1078869	1			T1	147		T11	188		T12	36
all_pins[18]	values[0x0]	2931667	1			T23	1		T1	296		T11	521
all_pins[18]	values[0x1]	1785796	1			T1	195		T11	245		T12	55
all_pins[18]	transitions[0x0=>0x1]	1072237	1			T1	142		T11	132		T12	27
all_pins[18]	transitions[0x1=>0x0]	1067481	1			T1	129		T11	186		T12	17
all_pins[19]	values[0x0]	2932492	1			T23	1		T1	300		T11	484
all_pins[19]	values[0x1]	1784971	1			T1	191		T11	282		T12	51
all_pins[19]	transitions[0x0=>0x1]	1069253	1			T1	135		T11	186		T12	13
all_pins[19]	transitions[0x1=>0x0]	1070078	1			T1	139		T11	149		T12	17
all_pins[20]	values[0x0]	2933791	1			T23	1		T1	301		T11	454
all_pins[20]	values[0x1]	1783672	1			T1	190		T11	312		T12	35
all_pins[20]	transitions[0x0=>0x1]	1068800	1			T1	112		T11	199		T12	26
all_pins[20]	transitions[0x1=>0x0]	1070099	1			T1	113		T11	169		T12	42
all_pins[21]	values[0x0]	2927798	1			T23	1		T1	282		T11	450
all_pins[21]	values[0x1]	1789665	1			T1	209		T11	316		T12	54
all_pins[21]	transitions[0x0=>0x1]	1075499	1			T1	121		T11	202		T12	50
all_pins[21]	transitions[0x1=>0x0]	1069506	1			T1	102		T11	198		T12	31
all_pins[22]	values[0x0]	2929873	1			T23	1		T1	300		T11	422
all_pins[22]	values[0x1]	1787590	1			T1	191		T11	344		T12	47
all_pins[22]	transitions[0x0=>0x1]	1067477	1			T1	104		T11	201		T12	31
all_pins[22]	transitions[0x1=>0x0]	1069552	1			T1	122		T11	173		T12	38
all_pins[23]	values[0x0]	2925337	1			T23	1		T1	304		T11	455
all_pins[23]	values[0x1]	1792126	1			T1	187		T11	311		T12	36
all_pins[23]	transitions[0x0=>0x1]	1072532	1			T1	104		T11	160		T12	14
all_pins[23]	transitions[0x1=>0x0]	1067996	1			T1	108		T11	193		T12	25
all_pins[24]	values[0x0]	2930638	1			T23	1		T1	314		T11	574
all_pins[24]	values[0x1]	1786825	1			T1	177		T11	192		T12	59
all_pins[24]	transitions[0x0=>0x1]	1067993	1			T1	98		T11	98		T12	30
all_pins[24]	transitions[0x1=>0x0]	1073294	1			T1	108		T11	217		T12	7
all_pins[25]	values[0x0]	2927403	1			T23	1		T1	253		T11	539
all_pins[25]	values[0x1]	1790060	1			T1	238		T11	227		T12	45
all_pins[25]	transitions[0x0=>0x1]	1073158	1			T1	157		T11	182		T12	17
all_pins[25]	transitions[0x1=>0x0]	1069923	1			T1	96		T11	147		T12	31
all_pins[26]	values[0x0]	2929298	1			T23	1		T1	314		T11	460
all_pins[26]	values[0x1]	1788165	1			T1	177		T11	306		T12	17
all_pins[26]	transitions[0x0=>0x1]	1069472	1			T1	92		T11	212		T12	9
all_pins[26]	transitions[0x1=>0x0]	1071367	1			T1	153		T11	133		T12	37
all_pins[27]	values[0x0]	2929479	1			T23	1		T1	278		T11	432
all_pins[27]	values[0x1]	1787984	1			T1	213		T11	334		T12	40
all_pins[27]	transitions[0x0=>0x1]	1071965	1			T1	120		T11	183		T12	33
all_pins[27]	transitions[0x1=>0x0]	1072146	1			T1	84		T11	155		T12	10
all_pins[28]	values[0x0]	2927169	1			T23	1		T1	311		T11	489
all_pins[28]	values[0x1]	1790294	1			T1	180		T11	277		T12	38
all_pins[28]	transitions[0x0=>0x1]	1070329	1			T1	84		T11	104		T12	25
all_pins[28]	transitions[0x1=>0x0]	1068019	1			T1	117		T11	161		T12	27
all_pins[29]	values[0x0]	2927475	1			T23	1		T1	332		T11	576
all_pins[29]	values[0x1]	1789988	1			T1	159		T11	190		T12	35
all_pins[29]	transitions[0x0=>0x1]	1069378	1			T1	87		T11	140		T12	27
all_pins[29]	transitions[0x1=>0x0]	1069684	1			T1	108		T11	227		T12	30
all_pins[30]	values[0x0]	2925134	1			T23	1		T1	291		T11	399
all_pins[30]	values[0x1]	1792329	1			T1	200		T11	367		T12	39
all_pins[30]	transitions[0x0=>0x1]	1069352	1			T1	111		T11	287		T12	19
all_pins[30]	transitions[0x1=>0x0]	1067011	1			T1	70		T11	110		T12	15
all_pins[31]	values[0x0]	2929417	1			T23	1		T1	334		T11	432
all_pins[31]	values[0x1]	1788046	1			T1	157		T11	334		T12	35
all_pins[31]	transitions[0x0=>0x1]	1069374	1			T1	71		T11	162		T12	35
all_pins[31]	transitions[0x1=>0x0]	1073657	1			T1	114		T11	195		T12	39