Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[1]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[2]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[3]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[4]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[5]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[6]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[7]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[8]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[9]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[10]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[11]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[12]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[13]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[14]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[15]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[16]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[17]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[18]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[19]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[20]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[21]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[22]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[23]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[24]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[25]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[26]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[27]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[28]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[29]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[30]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[31]	15458428	1			T23	501		T1	1245		T11	1927

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299458439

1

T23

10543

T1

30307

T11

30804

auto[1]

195211257

1

T23

5489

T1

9533

T11

30860

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

396589765

1

T23

11167

T1

22610

T11

61664

auto[1]

98079931

1

T23

4865

T1

17230

T13

11306

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

367682834

1

T23

11183

T1

19642

T11

61664

auto[1]

126986862

1

T23

4849

T1

20198

T13

11109

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5793444	1			T23	182		T1	343		T11	974
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4154308	1			T23	88		T1	11		T11	953
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1541275	1			T23	64		T1	257		T13	183
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2015276	1			T23	79		T1	363		T14	27
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	424487	1			T1	6		T13	174		T14	86
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1529638	1			T23	88		T1	265		T13	182
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5796131	1			T23	173		T1	372		T11	993
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4146530	1			T23	103		T1	8		T11	934
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1544526	1			T23	69		T1	205		T13	164
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2019338	1			T23	80		T1	358		T14	22
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	424045	1			T1	9		T13	192		T14	85
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1527858	1			T23	76		T1	293		T13	164
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5807574	1			T23	185		T1	322		T11	969
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4140147	1			T23	93		T1	14		T11	958
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1546882	1			T23	72		T1	271		T13	191
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2016124	1			T23	70		T1	377		T14	21
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	422569	1			T1	8		T13	158		T14	63
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1525132	1			T23	81		T1	253		T13	186
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5788846	1			T23	153		T1	323		T11	977
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4159416	1			T23	99		T1	8		T11	950
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1541208	1			T23	78		T1	286		T13	151
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2022081	1			T23	73		T1	317		T14	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	421236	1			T1	20		T13	178		T14	29
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1525641	1			T23	98		T1	291		T13	178
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5790727	1			T23	185		T1	380		T11	989
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4148095	1			T23	103		T1	3		T11	938
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1538448	1			T23	98		T1	297		T13	184
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2022006	1			T23	52		T1	276		T14	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	423370	1			T1	18		T13	195		T14	89
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1535782	1			T23	63		T1	271		T13	172
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5788799	1			T23	175		T1	363		T11	973
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4151780	1			T23	91		T1	9		T11	954
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1539544	1			T23	80		T1	201		T13	186
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2019121	1			T23	82		T1	432		T14	4
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	424221	1			T1	13		T13	150		T14	14
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1534963	1			T23	73		T1	227		T13	210
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5802287	1			T23	191		T1	400		T11	972
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4149718	1			T23	93		T1	20		T11	955
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1542111	1			T23	78		T1	137		T13	196
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2015153	1			T23	85		T1	412		T14	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	422905	1			T1	8		T13	152		T14	26
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1526254	1			T23	54		T1	268		T13	172
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5790143	1			T23	164		T1	264		T11	976
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4159548	1			T23	108		T1	20		T11	951
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1538206	1			T23	62		T1	249		T13	208
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2016955	1			T23	92		T1	417		T14	10
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	424421	1			T1	6		T13	158		T14	56
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1529155	1			T23	75		T1	289		T13	173
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5796472	1			T23	196		T1	305		T11	956
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4156269	1			T23	88		T1	8		T11	971
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1545015	1			T23	66		T1	203		T13	149
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2009838	1			T23	81		T1	412		T14	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	421485	1			T1	11		T13	188		T14	20
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1529349	1			T23	70		T1	306		T13	236
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5799676	1			T23	173		T1	312		T11	951
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4146765	1			T23	91		T1	11		T11	976
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1540508	1			T23	94		T1	343		T13	127
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2018484	1			T23	69		T1	281		T14	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	423518	1			T1	17		T13	182		T14	91
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1529477	1			T23	74		T1	281		T13	194
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5805490	1			T23	174		T1	331		T11	935
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4144986	1			T23	84		T1	14		T11	992
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1542948	1			T23	99		T1	307		T13	161
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2014420	1			T23	54		T1	313		T14	27
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	422551	1			T1	10		T13	216		T14	91
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1528033	1			T23	90		T1	270		T13	116
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5793547	1			T23	195		T1	346		T11	1007
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4156833	1			T23	96		T1	11		T11	920
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1539348	1			T23	90		T1	270		T13	188
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2017737	1			T23	46		T1	324		T14	4
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	424246	1			T1	12		T13	155		T14	32
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1526717	1			T23	74		T1	282		T13	172
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5795653	1			T23	157		T1	314		T11	960
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4149847	1			T23	104		T1	2		T11	967
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1542746	1			T23	68		T1	278		T13	166
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2017722	1			T23	92		T1	319		T14	9
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	423444	1			T1	17		T13	188		T14	29
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1529016	1			T23	80		T1	315		T13	159
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5803420	1			T23	172		T1	307		T11	960
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4151835	1			T23	100		T1	9		T11	967
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1543137	1			T23	74		T1	267		T13	204
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2014599	1			T23	84		T1	341		T14	16
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	419516	1			T1	9		T13	171		T14	31
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1525921	1			T23	71		T1	312		T13	156
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5791521	1			T23	163		T1	336		T11	967
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4154537	1			T23	99		T1	20		T11	960
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1545225	1			T23	76		T1	296		T13	174
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2015343	1			T23	75		T1	292		T14	13
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	423599	1			T1	11		T13	172		T14	60
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1528203	1			T23	88		T1	290		T13	163
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5787379	1			T23	203		T1	299		T11	939
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4161071	1			T23	100		T1	19		T11	988
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1537906	1			T23	82		T1	293		T13	166
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2020602	1			T23	66		T1	343		T14	13
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	422641	1			T1	7		T13	192		T14	41
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1528829	1			T23	50		T1	284		T13	183
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5806867	1			T23	166		T1	284		T11	946
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4148898	1			T23	95		T1	11		T11	981
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1534185	1			T23	84		T1	335		T13	182
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2020005	1			T23	80		T1	278		T14	31
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	423417	1			T1	13		T13	186		T14	87
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1525056	1			T23	76		T1	324		T13	130
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5797902	1			T23	187		T1	351		T11	949
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4156419	1			T23	91		T1	12		T11	978
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1542259	1			T23	72		T1	340		T13	204
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2019436	1			T23	63		T1	316		T14	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	424991	1			T1	14		T13	156		T14	95
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1517421	1			T23	88		T1	212		T13	160
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5803368	1			T23	164		T1	289		T11	963
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4148703	1			T23	104		T1	9		T11	964
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1532564	1			T23	58		T1	195		T13	174
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2028466	1			T23	81		T1	473		T16	235
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	423569	1			T1	14		T13	168		T14	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1521758	1			T23	94		T1	265		T13	187
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5805576	1			T23	189		T1	328		T11	971
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4151779	1			T23	97		T1	15		T11	956
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1537854	1			T23	71		T1	183		T13	172
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2017241	1			T23	94		T1	437		T14	5
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	422524	1			T1	15		T13	198		T14	59
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1523454	1			T23	50		T1	267		T13	165
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5803521	1			T23	163		T1	309		T11	973
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4151825	1			T23	97		T1	11		T11	954
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1535803	1			T23	70		T1	257		T13	172
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2025632	1			T23	69		T1	380		T14	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	423665	1			T1	16		T13	190		T14	62
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1517982	1			T23	102		T1	272		T13	149
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5788782	1			T23	181		T1	341		T11	952
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4157369	1			T23	93		T1	12		T11	975
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1540613	1			T23	87		T1	301		T13	164
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2025099	1			T23	74		T1	311		T14	25
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	422505	1			T1	9		T13	184		T14	89
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1524060	1			T23	66		T1	271		T13	172
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5788359	1			T23	138		T1	344		T11	968
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4157726	1			T23	110		T1	17		T11	959
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1538838	1			T23	77		T1	223		T13	196
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2024120	1			T23	80		T1	357		T14	32
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	424826	1			T1	13		T13	188		T14	91
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1524559	1			T23	96		T1	291		T13	140
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5802673	1			T23	186		T1	314		T11	920
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4143863	1			T23	87		T1	19		T11	1007
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1534165	1			T23	64		T1	270		T13	216
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2025883	1			T23	88		T1	372		T14	3
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	425315	1			T1	12		T13	139		T14	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1526529	1			T23	76		T1	258		T13	196
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5800235	1			T23	183		T1	293		T11	940
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4152553	1			T23	90		T1	6		T11	987
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1539303	1			T23	68		T1	240		T13	181
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2020577	1			T23	80		T1	392		T14	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	423915	1			T1	21		T13	140		T14	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1521845	1			T23	80		T1	293		T13	164
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5818790	1			T23	183		T1	354		T11	992
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4140406	1			T23	90		T1	11		T11	935
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1532416	1			T23	80		T1	290		T13	176
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2018564	1			T23	92		T1	327		T14	10
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	424951	1			T1	17		T13	178		T14	64
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1523301	1			T23	56		T1	246		T13	153
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5810515	1			T23	193		T1	367		T11	973
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4149136	1			T23	99		T1	11		T11	954
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1541448	1			T23	78		T1	325		T13	178
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2012756	1			T23	69		T1	253		T14	26
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	422548	1			T1	14		T13	158		T14	92
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1522025	1			T23	62		T1	275		T13	170
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5809441	1			T23	179		T1	391		T11	980
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4147559	1			T23	91		T1	11		T11	947
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1534114	1			T23	84		T1	256		T13	172
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2021924	1			T23	82		T1	292		T14	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	424639	1			T1	5		T13	154		T14	50
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1520751	1			T23	65		T1	290		T13	197
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5801041	1			T23	182		T1	393		T11	923
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4151831	1			T23	100		T1	12		T11	1004
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1537397	1			T23	76		T1	305		T13	168
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2023968	1			T23	63		T1	283		T14	22
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	424299	1			T1	10		T13	184		T14	50
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1519892	1			T23	80		T1	242		T13	196
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5805970	1			T23	186		T1	406		T11	952
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4146546	1			T23	94		T1	21		T11	975
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1538575	1			T23	70		T1	327		T13	172
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2020835	1			T23	68		T1	277		T14	18
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	424038	1			T1	8		T13	155		T14	105
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1522464	1			T23	83		T1	206		T13	228
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5805069	1			T23	162		T1	361		T11	944
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4146475	1			T23	100		T1	14		T11	983
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1541108	1			T23	72		T1	239		T13	235
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2017572	1			T23	102		T1	341		T14	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	424465	1			T1	14		T13	134		T14	47
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1523739	1			T23	65		T1	276		T13	166
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5797156	1			T23	166		T1	329		T11	960
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4162155	1			T23	101		T1	14		T11	967
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1531857	1			T23	94		T1	232		T13	134
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2023656	1			T23	74		T1	392		T14	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	420009	1			T1	11		T13	164		T14	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1523595	1			T23	66		T1	267		T13	223

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal