Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[1]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[2]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[3]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[4]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[5]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[6]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[7]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[8]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[9]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[10]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[11]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[12]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[13]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[14]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[15]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[16]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[17]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[18]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[19]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[20]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[21]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[22]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[23]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[24]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[25]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[26]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[27]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[28]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[29]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[30]	15458428	1			T23	501		T1	1245		T11	1927
bins_for_gpio_bits[31]	15458428	1			T23	501		T1	1245		T11	1927

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299458439

1

T23

10543

T1

30307

T11

30804

auto[1]

195211257

1

T23

5489

T1

9533

T11

30860

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299450278

1

T23

10535

T1

30295

T11

30804

auto[1]

195219418

1

T23

5497

T1

9545

T11

30860

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9076303	1			T23	303		T1	924		T11	974
bins_for_gpio_bits[0]	auto[0]	auto[1]	273463	1			T23	22		T1	38		T13	45
bins_for_gpio_bits[0]	auto[1]	auto[0]	273692	1			T23	22		T1	39		T13	44
bins_for_gpio_bits[0]	auto[1]	auto[1]	5834970	1			T23	154		T1	244		T11	953
bins_for_gpio_bits[1]	auto[0]	auto[0]	9086101	1			T23	306		T1	895		T11	993
bins_for_gpio_bits[1]	auto[0]	auto[1]	273607	1			T23	16		T1	39		T13	41
bins_for_gpio_bits[1]	auto[1]	auto[0]	273894	1			T23	16		T1	40		T13	41
bins_for_gpio_bits[1]	auto[1]	auto[1]	5824826	1			T23	163		T1	271		T11	934
bins_for_gpio_bits[2]	auto[0]	auto[0]	9097699	1			T23	311		T1	935		T11	969
bins_for_gpio_bits[2]	auto[0]	auto[1]	272575	1			T23	15		T1	35		T13	49
bins_for_gpio_bits[2]	auto[1]	auto[0]	272881	1			T23	16		T1	35		T13	48
bins_for_gpio_bits[2]	auto[1]	auto[1]	5815273	1			T23	159		T1	240		T11	958
bins_for_gpio_bits[3]	auto[0]	auto[0]	9078952	1			T23	282		T1	883		T11	977
bins_for_gpio_bits[3]	auto[0]	auto[1]	272946	1			T23	22		T1	43		T13	43
bins_for_gpio_bits[3]	auto[1]	auto[0]	273183	1			T23	22		T1	43		T13	42
bins_for_gpio_bits[3]	auto[1]	auto[1]	5833347	1			T23	175		T1	276		T11	950
bins_for_gpio_bits[4]	auto[0]	auto[0]	9076511	1			T23	318		T1	915		T11	989
bins_for_gpio_bits[4]	auto[0]	auto[1]	274420	1			T23	16		T1	37		T13	40
bins_for_gpio_bits[4]	auto[1]	auto[0]	274670	1			T23	17		T1	38		T13	40
bins_for_gpio_bits[4]	auto[1]	auto[1]	5832827	1			T23	150		T1	255		T11	938
bins_for_gpio_bits[5]	auto[0]	auto[0]	9073487	1			T23	322		T1	960		T11	973
bins_for_gpio_bits[5]	auto[0]	auto[1]	273730	1			T23	14		T1	36		T13	47
bins_for_gpio_bits[5]	auto[1]	auto[0]	273977	1			T23	15		T1	36		T13	47
bins_for_gpio_bits[5]	auto[1]	auto[1]	5837234	1			T23	150		T1	213		T11	954
bins_for_gpio_bits[6]	auto[0]	auto[0]	9085666	1			T23	338		T1	908		T11	972
bins_for_gpio_bits[6]	auto[0]	auto[1]	273622	1			T23	16		T1	40		T13	41
bins_for_gpio_bits[6]	auto[1]	auto[0]	273885	1			T23	16		T1	41		T13	41
bins_for_gpio_bits[6]	auto[1]	auto[1]	5825255	1			T23	131		T1	256		T11	955
bins_for_gpio_bits[7]	auto[0]	auto[0]	9071720	1			T23	298		T1	885		T11	976
bins_for_gpio_bits[7]	auto[0]	auto[1]	273316	1			T23	19		T1	45		T13	49
bins_for_gpio_bits[7]	auto[1]	auto[0]	273584	1			T23	20		T1	45		T13	49
bins_for_gpio_bits[7]	auto[1]	auto[1]	5839808	1			T23	164		T1	270		T11	951
bins_for_gpio_bits[8]	auto[0]	auto[0]	9078098	1			T23	326		T1	871		T11	956
bins_for_gpio_bits[8]	auto[0]	auto[1]	272947	1			T23	17		T1	48		T13	37
bins_for_gpio_bits[8]	auto[1]	auto[0]	273227	1			T23	17		T1	49		T13	36
bins_for_gpio_bits[8]	auto[1]	auto[1]	5834156	1			T23	141		T1	277		T11	971
bins_for_gpio_bits[9]	auto[0]	auto[0]	9084984	1			T23	314		T1	896		T11	951
bins_for_gpio_bits[9]	auto[0]	auto[1]	273452	1			T23	22		T1	39		T13	37
bins_for_gpio_bits[9]	auto[1]	auto[0]	273684	1			T23	22		T1	40		T13	36
bins_for_gpio_bits[9]	auto[1]	auto[1]	5826308	1			T23	143		T1	270		T11	976
bins_for_gpio_bits[10]	auto[0]	auto[0]	9088958	1			T23	303		T1	919		T11	935
bins_for_gpio_bits[10]	auto[0]	auto[1]	273687	1			T23	24		T1	32		T13	43
bins_for_gpio_bits[10]	auto[1]	auto[0]	273900	1			T23	24		T1	32		T13	42
bins_for_gpio_bits[10]	auto[1]	auto[1]	5821883	1			T23	150		T1	262		T11	992
bins_for_gpio_bits[11]	auto[0]	auto[0]	9077206	1			T23	313		T1	900		T11	1007
bins_for_gpio_bits[11]	auto[0]	auto[1]	273162	1			T23	18		T1	40		T13	48
bins_for_gpio_bits[11]	auto[1]	auto[0]	273426	1			T23	18		T1	40		T13	48
bins_for_gpio_bits[11]	auto[1]	auto[1]	5834634	1			T23	152		T1	265		T11	920
bins_for_gpio_bits[12]	auto[0]	auto[0]	9082445	1			T23	302		T1	870		T11	960
bins_for_gpio_bits[12]	auto[0]	auto[1]	273442	1			T23	15		T1	41		T13	45
bins_for_gpio_bits[12]	auto[1]	auto[0]	273676	1			T23	15		T1	41		T13	45
bins_for_gpio_bits[12]	auto[1]	auto[1]	5828865	1			T23	169		T1	293		T11	967
bins_for_gpio_bits[13]	auto[0]	auto[0]	9087231	1			T23	311		T1	875		T11	960
bins_for_gpio_bits[13]	auto[0]	auto[1]	273660	1			T23	18		T1	40		T13	44
bins_for_gpio_bits[13]	auto[1]	auto[0]	273925	1			T23	19		T1	40		T13	44
bins_for_gpio_bits[13]	auto[1]	auto[1]	5823612	1			T23	153		T1	290		T11	967
bins_for_gpio_bits[14]	auto[0]	auto[0]	9077962	1			T23	291		T1	890		T11	967
bins_for_gpio_bits[14]	auto[0]	auto[1]	273832	1			T23	23		T1	34		T13	42
bins_for_gpio_bits[14]	auto[1]	auto[0]	274127	1			T23	23		T1	34		T13	42
bins_for_gpio_bits[14]	auto[1]	auto[1]	5832507	1			T23	164		T1	287		T11	960
bins_for_gpio_bits[15]	auto[0]	auto[0]	9071914	1			T23	334		T1	887		T11	939
bins_for_gpio_bits[15]	auto[0]	auto[1]	273709	1			T23	17		T1	47		T13	46
bins_for_gpio_bits[15]	auto[1]	auto[0]	273973	1			T23	17		T1	48		T13	46
bins_for_gpio_bits[15]	auto[1]	auto[1]	5838832	1			T23	133		T1	263		T11	988
bins_for_gpio_bits[16]	auto[0]	auto[0]	9087335	1			T23	311		T1	848		T11	946
bins_for_gpio_bits[16]	auto[0]	auto[1]	273490	1			T23	19		T1	49		T13	42
bins_for_gpio_bits[16]	auto[1]	auto[0]	273722	1			T23	19		T1	49		T13	42
bins_for_gpio_bits[16]	auto[1]	auto[1]	5823881	1			T23	152		T1	299		T11	981
bins_for_gpio_bits[17]	auto[0]	auto[0]	9086524	1			T23	301		T1	968		T11	949
bins_for_gpio_bits[17]	auto[0]	auto[1]	272810	1			T23	21		T1	39		T13	50
bins_for_gpio_bits[17]	auto[1]	auto[0]	273073	1			T23	21		T1	39		T13	50
bins_for_gpio_bits[17]	auto[1]	auto[1]	5826021	1			T23	158		T1	199		T11	978
bins_for_gpio_bits[18]	auto[0]	auto[0]	9089781	1			T23	280		T1	913		T11	963
bins_for_gpio_bits[18]	auto[0]	auto[1]	274363	1			T23	23		T1	44		T13	48
bins_for_gpio_bits[18]	auto[1]	auto[0]	274617	1			T23	23		T1	44		T13	48
bins_for_gpio_bits[18]	auto[1]	auto[1]	5819667	1			T23	175		T1	244		T11	964
bins_for_gpio_bits[19]	auto[0]	auto[0]	9087323	1			T23	339		T1	909		T11	971
bins_for_gpio_bits[19]	auto[0]	auto[1]	273065	1			T23	15		T1	39		T13	40
bins_for_gpio_bits[19]	auto[1]	auto[0]	273348	1			T23	15		T1	39		T13	40
bins_for_gpio_bits[19]	auto[1]	auto[1]	5824692	1			T23	132		T1	258		T11	956
bins_for_gpio_bits[20]	auto[0]	auto[0]	9091453	1			T23	282		T1	902		T11	973
bins_for_gpio_bits[20]	auto[0]	auto[1]	273234	1			T23	20		T1	43		T13	44
bins_for_gpio_bits[20]	auto[1]	auto[0]	273503	1			T23	20		T1	44		T13	44
bins_for_gpio_bits[20]	auto[1]	auto[1]	5820238	1			T23	179		T1	256		T11	954
bins_for_gpio_bits[21]	auto[0]	auto[0]	9080245	1			T23	322		T1	914		T11	952
bins_for_gpio_bits[21]	auto[0]	auto[1]	273995	1			T23	20		T1	39		T13	45
bins_for_gpio_bits[21]	auto[1]	auto[0]	274249	1			T23	20		T1	39		T13	45
bins_for_gpio_bits[21]	auto[1]	auto[1]	5829939	1			T23	139		T1	253		T11	975
bins_for_gpio_bits[22]	auto[0]	auto[0]	9077759	1			T23	271		T1	885		T11	968
bins_for_gpio_bits[22]	auto[0]	auto[1]	273323	1			T23	24		T1	39		T13	47
bins_for_gpio_bits[22]	auto[1]	auto[0]	273558	1			T23	24		T1	39		T13	47
bins_for_gpio_bits[22]	auto[1]	auto[1]	5833788	1			T23	182		T1	282		T11	959
bins_for_gpio_bits[23]	auto[0]	auto[0]	9088332	1			T23	319		T1	917		T11	920
bins_for_gpio_bits[23]	auto[0]	auto[1]	274168	1			T23	19		T1	38		T13	49
bins_for_gpio_bits[23]	auto[1]	auto[0]	274389	1			T23	19		T1	39		T13	49
bins_for_gpio_bits[23]	auto[1]	auto[1]	5821539	1			T23	144		T1	251		T11	1007
bins_for_gpio_bits[24]	auto[0]	auto[0]	9086186	1			T23	314		T1	889		T11	940
bins_for_gpio_bits[24]	auto[0]	auto[1]	273729	1			T23	17		T1	36		T13	49
bins_for_gpio_bits[24]	auto[1]	auto[0]	273929	1			T23	17		T1	36		T13	48
bins_for_gpio_bits[24]	auto[1]	auto[1]	5824584	1			T23	153		T1	284		T11	987
bins_for_gpio_bits[25]	auto[0]	auto[0]	9096527	1			T23	336		T1	935		T11	992
bins_for_gpio_bits[25]	auto[0]	auto[1]	272972	1			T23	19		T1	36		T13	44
bins_for_gpio_bits[25]	auto[1]	auto[0]	273243	1			T23	19		T1	36		T13	44
bins_for_gpio_bits[25]	auto[1]	auto[1]	5815686	1			T23	127		T1	238		T11	935
bins_for_gpio_bits[26]	auto[0]	auto[0]	9091126	1			T23	322		T1	904		T11	973
bins_for_gpio_bits[26]	auto[0]	auto[1]	273320	1			T23	18		T1	40		T13	47
bins_for_gpio_bits[26]	auto[1]	auto[0]	273593	1			T23	18		T1	41		T13	47
bins_for_gpio_bits[26]	auto[1]	auto[1]	5820389	1			T23	143		T1	260		T11	954
bins_for_gpio_bits[27]	auto[0]	auto[0]	9092110	1			T23	328		T1	903		T11	980
bins_for_gpio_bits[27]	auto[0]	auto[1]	273109	1			T23	16		T1	36		T13	50
bins_for_gpio_bits[27]	auto[1]	auto[0]	273369	1			T23	17		T1	36		T13	50
bins_for_gpio_bits[27]	auto[1]	auto[1]	5819840	1			T23	140		T1	270		T11	947
bins_for_gpio_bits[28]	auto[0]	auto[0]	9088871	1			T23	304		T1	945		T11	923
bins_for_gpio_bits[28]	auto[0]	auto[1]	273259	1			T23	17		T1	35		T13	36
bins_for_gpio_bits[28]	auto[1]	auto[0]	273535	1			T23	17		T1	36		T13	36
bins_for_gpio_bits[28]	auto[1]	auto[1]	5822763	1			T23	163		T1	229		T11	1004
bins_for_gpio_bits[29]	auto[0]	auto[0]	9091691	1			T23	305		T1	975		T11	952
bins_for_gpio_bits[29]	auto[0]	auto[1]	273403	1			T23	18		T1	34		T13	43
bins_for_gpio_bits[29]	auto[1]	auto[0]	273689	1			T23	19		T1	35		T13	43
bins_for_gpio_bits[29]	auto[1]	auto[1]	5819645	1			T23	159		T1	201		T11	975
bins_for_gpio_bits[30]	auto[0]	auto[0]	9090059	1			T23	318		T1	906		T11	944
bins_for_gpio_bits[30]	auto[0]	auto[1]	273448	1			T23	17		T1	35		T13	46
bins_for_gpio_bits[30]	auto[1]	auto[0]	273690	1			T23	18		T1	35		T13	45
bins_for_gpio_bits[30]	auto[1]	auto[1]	5821231	1			T23	148		T1	269		T11	983
bins_for_gpio_bits[31]	auto[0]	auto[0]	9078757	1			T23	318		T1	918		T11	960
bins_for_gpio_bits[31]	auto[0]	auto[1]	273704	1			T23	16		T1	35		T13	39
bins_for_gpio_bits[31]	auto[1]	auto[0]	273912	1			T23	16		T1	35		T13	39
bins_for_gpio_bits[31]	auto[1]	auto[1]	5832055	1			T23	151		T1	257		T11	967