Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9029528 |
1 |
|
|
T23 |
349 |
|
T1 |
583 |
|
T11 |
1376 |
| auto[1] |
6669841 |
1 |
|
|
T1 |
714 |
|
T11 |
1092 |
|
T12 |
127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838200 |
1 |
|
|
T23 |
349 |
|
T1 |
1274 |
|
T11 |
2286 |
| auto[1] |
861169 |
1 |
|
|
T1 |
23 |
|
T11 |
182 |
|
T12 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8986129 |
1 |
|
|
T23 |
349 |
|
T1 |
658 |
|
T11 |
1528 |
| auto[1] |
6713240 |
1 |
|
|
T1 |
639 |
|
T11 |
940 |
|
T12 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2942090 |
1 |
|
|
T1 |
315 |
|
T11 |
371 |
|
T12 |
32 |
| auto[1] |
auto[0] |
auto[1] |
432522 |
1 |
|
|
T1 |
15 |
|
T11 |
88 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2909981 |
1 |
|
|
T1 |
301 |
|
T11 |
387 |
|
T12 |
65 |
| auto[1] |
auto[1] |
auto[1] |
428647 |
1 |
|
|
T1 |
8 |
|
T11 |
94 |
|
T12 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8992828 |
1 |
|
|
T23 |
349 |
|
T1 |
650 |
|
T11 |
1065 |
| auto[1] |
6706541 |
1 |
|
|
T1 |
647 |
|
T11 |
1403 |
|
T12 |
125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14832352 |
1 |
|
|
T23 |
349 |
|
T1 |
1267 |
|
T11 |
2211 |
| auto[1] |
867017 |
1 |
|
|
T1 |
30 |
|
T11 |
257 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8956795 |
1 |
|
|
T23 |
349 |
|
T1 |
718 |
|
T11 |
1116 |
| auto[1] |
6742574 |
1 |
|
|
T1 |
579 |
|
T11 |
1352 |
|
T12 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2944365 |
1 |
|
|
T1 |
279 |
|
T11 |
536 |
|
T12 |
33 |
| auto[1] |
auto[0] |
auto[1] |
434785 |
1 |
|
|
T1 |
10 |
|
T11 |
116 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2931192 |
1 |
|
|
T1 |
270 |
|
T11 |
559 |
|
T12 |
51 |
| auto[1] |
auto[1] |
auto[1] |
432232 |
1 |
|
|
T1 |
20 |
|
T11 |
141 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8999275 |
1 |
|
|
T23 |
349 |
|
T1 |
895 |
|
T11 |
1233 |
| auto[1] |
6700094 |
1 |
|
|
T1 |
402 |
|
T11 |
1235 |
|
T12 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14843688 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2229 |
| auto[1] |
855681 |
1 |
|
|
T1 |
25 |
|
T11 |
239 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9010139 |
1 |
|
|
T23 |
349 |
|
T1 |
657 |
|
T11 |
1149 |
| auto[1] |
6689230 |
1 |
|
|
T1 |
640 |
|
T11 |
1319 |
|
T12 |
81 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2922168 |
1 |
|
|
T1 |
439 |
|
T11 |
470 |
|
T12 |
51 |
| auto[1] |
auto[0] |
auto[1] |
429116 |
1 |
|
|
T1 |
14 |
|
T11 |
106 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2911381 |
1 |
|
|
T1 |
176 |
|
T11 |
610 |
|
T12 |
26 |
| auto[1] |
auto[1] |
auto[1] |
426565 |
1 |
|
|
T1 |
11 |
|
T11 |
133 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9018148 |
1 |
|
|
T23 |
349 |
|
T1 |
793 |
|
T11 |
1349 |
| auto[1] |
6681221 |
1 |
|
|
T1 |
504 |
|
T11 |
1119 |
|
T12 |
133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14841646 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2162 |
| auto[1] |
857723 |
1 |
|
|
T1 |
25 |
|
T11 |
306 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9006582 |
1 |
|
|
T23 |
349 |
|
T1 |
732 |
|
T11 |
957 |
| auto[1] |
6692787 |
1 |
|
|
T1 |
565 |
|
T11 |
1511 |
|
T12 |
102 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2934313 |
1 |
|
|
T1 |
346 |
|
T11 |
674 |
|
T12 |
46 |
| auto[1] |
auto[0] |
auto[1] |
431589 |
1 |
|
|
T1 |
16 |
|
T11 |
175 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2900751 |
1 |
|
|
T1 |
194 |
|
T11 |
531 |
|
T12 |
47 |
| auto[1] |
auto[1] |
auto[1] |
426134 |
1 |
|
|
T1 |
9 |
|
T11 |
131 |
|
T12 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9018000 |
1 |
|
|
T23 |
349 |
|
T1 |
882 |
|
T11 |
1173 |
| auto[1] |
6681369 |
1 |
|
|
T1 |
415 |
|
T11 |
1295 |
|
T12 |
126 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14841612 |
1 |
|
|
T23 |
349 |
|
T1 |
1281 |
|
T11 |
2167 |
| auto[1] |
857757 |
1 |
|
|
T1 |
16 |
|
T11 |
301 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9006971 |
1 |
|
|
T23 |
349 |
|
T1 |
756 |
|
T11 |
915 |
| auto[1] |
6692398 |
1 |
|
|
T1 |
541 |
|
T11 |
1553 |
|
T12 |
79 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2926408 |
1 |
|
|
T1 |
373 |
|
T11 |
631 |
|
T12 |
42 |
| auto[1] |
auto[0] |
auto[1] |
430467 |
1 |
|
|
T1 |
10 |
|
T11 |
152 |
|
T15 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2908233 |
1 |
|
|
T1 |
152 |
|
T11 |
621 |
|
T12 |
35 |
| auto[1] |
auto[1] |
auto[1] |
427290 |
1 |
|
|
T1 |
6 |
|
T11 |
149 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8991338 |
1 |
|
|
T23 |
349 |
|
T1 |
837 |
|
T11 |
1273 |
| auto[1] |
6708031 |
1 |
|
|
T1 |
460 |
|
T11 |
1195 |
|
T12 |
97 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14837539 |
1 |
|
|
T23 |
349 |
|
T1 |
1267 |
|
T11 |
2224 |
| auto[1] |
861830 |
1 |
|
|
T1 |
30 |
|
T11 |
244 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8983297 |
1 |
|
|
T23 |
349 |
|
T1 |
626 |
|
T11 |
1228 |
| auto[1] |
6716072 |
1 |
|
|
T1 |
671 |
|
T11 |
1240 |
|
T12 |
74 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2928607 |
1 |
|
|
T1 |
401 |
|
T11 |
518 |
|
T12 |
43 |
| auto[1] |
auto[0] |
auto[1] |
431117 |
1 |
|
|
T1 |
23 |
|
T11 |
131 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2925635 |
1 |
|
|
T1 |
240 |
|
T11 |
478 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[1] |
430713 |
1 |
|
|
T1 |
7 |
|
T11 |
113 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9013891 |
1 |
|
|
T23 |
349 |
|
T1 |
644 |
|
T11 |
1356 |
| auto[1] |
6685478 |
1 |
|
|
T1 |
653 |
|
T11 |
1112 |
|
T12 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14833639 |
1 |
|
|
T23 |
349 |
|
T1 |
1271 |
|
T11 |
2213 |
| auto[1] |
865730 |
1 |
|
|
T1 |
26 |
|
T11 |
255 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8969778 |
1 |
|
|
T23 |
349 |
|
T1 |
567 |
|
T11 |
1082 |
| auto[1] |
6729591 |
1 |
|
|
T1 |
730 |
|
T11 |
1386 |
|
T12 |
120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2953977 |
1 |
|
|
T1 |
332 |
|
T11 |
670 |
|
T12 |
80 |
| auto[1] |
auto[0] |
auto[1] |
437460 |
1 |
|
|
T1 |
14 |
|
T11 |
161 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2909884 |
1 |
|
|
T1 |
372 |
|
T11 |
461 |
|
T12 |
33 |
| auto[1] |
auto[1] |
auto[1] |
428270 |
1 |
|
|
T1 |
12 |
|
T11 |
94 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9025629 |
1 |
|
|
T23 |
349 |
|
T1 |
583 |
|
T11 |
1203 |
| auto[1] |
6673740 |
1 |
|
|
T1 |
714 |
|
T11 |
1265 |
|
T12 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14837354 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2267 |
| auto[1] |
862015 |
1 |
|
|
T1 |
25 |
|
T11 |
201 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8976861 |
1 |
|
|
T23 |
349 |
|
T1 |
763 |
|
T11 |
1478 |
| auto[1] |
6722508 |
1 |
|
|
T1 |
534 |
|
T11 |
990 |
|
T12 |
117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2946935 |
1 |
|
|
T1 |
226 |
|
T11 |
413 |
|
T12 |
53 |
| auto[1] |
auto[0] |
auto[1] |
435071 |
1 |
|
|
T1 |
14 |
|
T11 |
104 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2913558 |
1 |
|
|
T1 |
283 |
|
T11 |
376 |
|
T12 |
59 |
| auto[1] |
auto[1] |
auto[1] |
426944 |
1 |
|
|
T1 |
11 |
|
T11 |
97 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8979506 |
1 |
|
|
T23 |
349 |
|
T1 |
626 |
|
T11 |
1458 |
| auto[1] |
6719863 |
1 |
|
|
T1 |
671 |
|
T11 |
1010 |
|
T12 |
133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14836576 |
1 |
|
|
T23 |
349 |
|
T1 |
1271 |
|
T11 |
2171 |
| auto[1] |
862793 |
1 |
|
|
T1 |
26 |
|
T11 |
297 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8967736 |
1 |
|
|
T23 |
349 |
|
T1 |
710 |
|
T11 |
986 |
| auto[1] |
6731633 |
1 |
|
|
T1 |
587 |
|
T11 |
1482 |
|
T12 |
106 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2926377 |
1 |
|
|
T1 |
280 |
|
T11 |
691 |
|
T12 |
31 |
| auto[1] |
auto[0] |
auto[1] |
430249 |
1 |
|
|
T1 |
10 |
|
T11 |
175 |
|
T15 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2942463 |
1 |
|
|
T1 |
281 |
|
T11 |
494 |
|
T12 |
66 |
| auto[1] |
auto[1] |
auto[1] |
432544 |
1 |
|
|
T1 |
16 |
|
T11 |
122 |
|
T12 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9001481 |
1 |
|
|
T23 |
349 |
|
T1 |
699 |
|
T11 |
1273 |
| auto[1] |
6697888 |
1 |
|
|
T1 |
598 |
|
T11 |
1195 |
|
T12 |
121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838240 |
1 |
|
|
T23 |
349 |
|
T1 |
1267 |
|
T11 |
2277 |
| auto[1] |
861129 |
1 |
|
|
T1 |
30 |
|
T11 |
191 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8975311 |
1 |
|
|
T23 |
349 |
|
T1 |
589 |
|
T11 |
1557 |
| auto[1] |
6724058 |
1 |
|
|
T1 |
708 |
|
T11 |
911 |
|
T12 |
89 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2948868 |
1 |
|
|
T1 |
349 |
|
T11 |
360 |
|
T12 |
27 |
| auto[1] |
auto[0] |
auto[1] |
433271 |
1 |
|
|
T1 |
18 |
|
T11 |
99 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2914061 |
1 |
|
|
T1 |
329 |
|
T11 |
360 |
|
T12 |
57 |
| auto[1] |
auto[1] |
auto[1] |
427858 |
1 |
|
|
T1 |
12 |
|
T11 |
92 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8996269 |
1 |
|
|
T23 |
349 |
|
T1 |
648 |
|
T11 |
1391 |
| auto[1] |
6703100 |
1 |
|
|
T1 |
649 |
|
T11 |
1077 |
|
T12 |
150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14840848 |
1 |
|
|
T23 |
349 |
|
T1 |
1255 |
|
T11 |
2237 |
| auto[1] |
858521 |
1 |
|
|
T1 |
42 |
|
T11 |
231 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8998580 |
1 |
|
|
T23 |
349 |
|
T1 |
443 |
|
T11 |
1255 |
| auto[1] |
6700789 |
1 |
|
|
T1 |
854 |
|
T11 |
1213 |
|
T12 |
95 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2926147 |
1 |
|
|
T1 |
351 |
|
T11 |
618 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
431088 |
1 |
|
|
T1 |
17 |
|
T11 |
140 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2916121 |
1 |
|
|
T1 |
461 |
|
T11 |
364 |
|
T12 |
66 |
| auto[1] |
auto[1] |
auto[1] |
427433 |
1 |
|
|
T1 |
25 |
|
T11 |
91 |
|
T12 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942240 |
1 |
|
|
T23 |
349 |
|
T1 |
597 |
|
T11 |
1310 |
| auto[1] |
6757129 |
1 |
|
|
T1 |
700 |
|
T11 |
1158 |
|
T12 |
126 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838051 |
1 |
|
|
T23 |
349 |
|
T1 |
1267 |
|
T11 |
2236 |
| auto[1] |
861318 |
1 |
|
|
T1 |
30 |
|
T11 |
232 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8981334 |
1 |
|
|
T23 |
349 |
|
T1 |
568 |
|
T11 |
1324 |
| auto[1] |
6718035 |
1 |
|
|
T1 |
729 |
|
T11 |
1144 |
|
T12 |
55 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2910098 |
1 |
|
|
T1 |
304 |
|
T11 |
450 |
|
T12 |
18 |
| auto[1] |
auto[0] |
auto[1] |
427884 |
1 |
|
|
T1 |
10 |
|
T11 |
113 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2946619 |
1 |
|
|
T1 |
395 |
|
T11 |
462 |
|
T12 |
30 |
| auto[1] |
auto[1] |
auto[1] |
433434 |
1 |
|
|
T1 |
20 |
|
T11 |
119 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8971399 |
1 |
|
|
T23 |
349 |
|
T1 |
547 |
|
T11 |
1123 |
| auto[1] |
6727970 |
1 |
|
|
T1 |
750 |
|
T11 |
1345 |
|
T12 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14837748 |
1 |
|
|
T23 |
349 |
|
T1 |
1278 |
|
T11 |
2224 |
| auto[1] |
861621 |
1 |
|
|
T1 |
19 |
|
T11 |
244 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972144 |
1 |
|
|
T23 |
349 |
|
T1 |
786 |
|
T11 |
1219 |
| auto[1] |
6727225 |
1 |
|
|
T1 |
511 |
|
T11 |
1249 |
|
T12 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2928458 |
1 |
|
|
T1 |
175 |
|
T11 |
406 |
|
T12 |
54 |
| auto[1] |
auto[0] |
auto[1] |
429982 |
1 |
|
|
T1 |
5 |
|
T11 |
103 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2937146 |
1 |
|
|
T1 |
317 |
|
T11 |
599 |
|
T12 |
66 |
| auto[1] |
auto[1] |
auto[1] |
431639 |
1 |
|
|
T1 |
14 |
|
T11 |
141 |
|
T12 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9005366 |
1 |
|
|
T23 |
349 |
|
T1 |
712 |
|
T11 |
1321 |
| auto[1] |
6694003 |
1 |
|
|
T1 |
585 |
|
T11 |
1147 |
|
T12 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14841958 |
1 |
|
|
T23 |
349 |
|
T1 |
1277 |
|
T11 |
2286 |
| auto[1] |
857411 |
1 |
|
|
T1 |
20 |
|
T11 |
182 |
|
T12 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9016561 |
1 |
|
|
T23 |
349 |
|
T1 |
785 |
|
T11 |
1532 |
| auto[1] |
6682808 |
1 |
|
|
T1 |
512 |
|
T11 |
936 |
|
T12 |
136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2927652 |
1 |
|
|
T1 |
240 |
|
T11 |
365 |
|
T12 |
63 |
| auto[1] |
auto[0] |
auto[1] |
431007 |
1 |
|
|
T1 |
8 |
|
T11 |
96 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2897745 |
1 |
|
|
T1 |
252 |
|
T11 |
389 |
|
T12 |
61 |
| auto[1] |
auto[1] |
auto[1] |
426404 |
1 |
|
|
T1 |
12 |
|
T11 |
86 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940129 |
1 |
|
|
T23 |
349 |
|
T1 |
605 |
|
T11 |
1191 |
| auto[1] |
6759240 |
1 |
|
|
T1 |
692 |
|
T11 |
1277 |
|
T12 |
111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14842477 |
1 |
|
|
T23 |
349 |
|
T1 |
1280 |
|
T11 |
2248 |
| auto[1] |
856892 |
1 |
|
|
T1 |
17 |
|
T11 |
220 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9009994 |
1 |
|
|
T23 |
349 |
|
T1 |
664 |
|
T11 |
1357 |
| auto[1] |
6689375 |
1 |
|
|
T1 |
633 |
|
T11 |
1111 |
|
T12 |
102 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2901987 |
1 |
|
|
T1 |
231 |
|
T11 |
438 |
|
T12 |
46 |
| auto[1] |
auto[0] |
auto[1] |
425484 |
1 |
|
|
T1 |
7 |
|
T11 |
111 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2930496 |
1 |
|
|
T1 |
385 |
|
T11 |
453 |
|
T12 |
52 |
| auto[1] |
auto[1] |
auto[1] |
431408 |
1 |
|
|
T1 |
10 |
|
T11 |
109 |
|
T15 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9027915 |
1 |
|
|
T23 |
349 |
|
T1 |
685 |
|
T11 |
1056 |
| auto[1] |
6671454 |
1 |
|
|
T1 |
612 |
|
T11 |
1412 |
|
T12 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14840014 |
1 |
|
|
T23 |
349 |
|
T1 |
1270 |
|
T11 |
2217 |
| auto[1] |
859355 |
1 |
|
|
T1 |
27 |
|
T11 |
251 |
|
T12 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8992523 |
1 |
|
|
T23 |
349 |
|
T1 |
647 |
|
T11 |
1230 |
| auto[1] |
6706846 |
1 |
|
|
T1 |
650 |
|
T11 |
1238 |
|
T12 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2949344 |
1 |
|
|
T1 |
346 |
|
T11 |
373 |
|
T12 |
46 |
| auto[1] |
auto[0] |
auto[1] |
433695 |
1 |
|
|
T1 |
17 |
|
T11 |
89 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2898147 |
1 |
|
|
T1 |
277 |
|
T11 |
614 |
|
T12 |
51 |
| auto[1] |
auto[1] |
auto[1] |
425660 |
1 |
|
|
T1 |
10 |
|
T11 |
162 |
|
T12 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8934016 |
1 |
|
|
T23 |
349 |
|
T1 |
661 |
|
T11 |
1066 |
| auto[1] |
6765353 |
1 |
|
|
T1 |
636 |
|
T11 |
1402 |
|
T12 |
70 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14841649 |
1 |
|
|
T23 |
349 |
|
T1 |
1281 |
|
T11 |
2262 |
| auto[1] |
857720 |
1 |
|
|
T1 |
16 |
|
T11 |
206 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9012388 |
1 |
|
|
T23 |
349 |
|
T1 |
833 |
|
T11 |
1424 |
| auto[1] |
6686981 |
1 |
|
|
T1 |
464 |
|
T11 |
1044 |
|
T12 |
99 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2882538 |
1 |
|
|
T1 |
212 |
|
T11 |
362 |
|
T12 |
66 |
| auto[1] |
auto[0] |
auto[1] |
422629 |
1 |
|
|
T1 |
7 |
|
T11 |
90 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2946723 |
1 |
|
|
T1 |
236 |
|
T11 |
476 |
|
T12 |
26 |
| auto[1] |
auto[1] |
auto[1] |
435091 |
1 |
|
|
T1 |
9 |
|
T11 |
116 |
|
T15 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972962 |
1 |
|
|
T23 |
349 |
|
T1 |
708 |
|
T11 |
1705 |
| auto[1] |
6726407 |
1 |
|
|
T1 |
589 |
|
T11 |
763 |
|
T12 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14834922 |
1 |
|
|
T23 |
349 |
|
T1 |
1274 |
|
T11 |
2256 |
| auto[1] |
864447 |
1 |
|
|
T1 |
23 |
|
T11 |
212 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8960027 |
1 |
|
|
T23 |
349 |
|
T1 |
619 |
|
T11 |
1395 |
| auto[1] |
6739342 |
1 |
|
|
T1 |
678 |
|
T11 |
1073 |
|
T12 |
90 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2936386 |
1 |
|
|
T1 |
331 |
|
T11 |
657 |
|
T12 |
27 |
| auto[1] |
auto[0] |
auto[1] |
431009 |
1 |
|
|
T1 |
12 |
|
T11 |
159 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2938509 |
1 |
|
|
T1 |
324 |
|
T11 |
204 |
|
T12 |
58 |
| auto[1] |
auto[1] |
auto[1] |
433438 |
1 |
|
|
T1 |
11 |
|
T11 |
53 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8957177 |
1 |
|
|
T23 |
349 |
|
T1 |
546 |
|
T11 |
1530 |
| auto[1] |
6742192 |
1 |
|
|
T1 |
751 |
|
T11 |
938 |
|
T12 |
147 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14839621 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2230 |
| auto[1] |
859748 |
1 |
|
|
T1 |
25 |
|
T11 |
238 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8991577 |
1 |
|
|
T23 |
349 |
|
T1 |
672 |
|
T11 |
1220 |
| auto[1] |
6707792 |
1 |
|
|
T1 |
625 |
|
T11 |
1248 |
|
T12 |
101 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2913796 |
1 |
|
|
T1 |
278 |
|
T11 |
544 |
|
T12 |
30 |
| auto[1] |
auto[0] |
auto[1] |
428394 |
1 |
|
|
T1 |
13 |
|
T11 |
127 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2934248 |
1 |
|
|
T1 |
322 |
|
T11 |
466 |
|
T12 |
66 |
| auto[1] |
auto[1] |
auto[1] |
431354 |
1 |
|
|
T1 |
12 |
|
T11 |
111 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9007555 |
1 |
|
|
T23 |
349 |
|
T1 |
591 |
|
T11 |
1235 |
| auto[1] |
6691814 |
1 |
|
|
T1 |
706 |
|
T11 |
1233 |
|
T12 |
40 |