Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972051 |
1 |
|
|
T23 |
349 |
|
T1 |
659 |
|
T11 |
1503 |
| auto[1] |
6727318 |
1 |
|
|
T1 |
638 |
|
T11 |
965 |
|
T12 |
109 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14836235 |
1 |
|
|
T23 |
349 |
|
T1 |
1274 |
|
T11 |
2184 |
| auto[1] |
863134 |
1 |
|
|
T1 |
23 |
|
T11 |
284 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8970408 |
1 |
|
|
T23 |
349 |
|
T1 |
639 |
|
T11 |
1021 |
| auto[1] |
6728961 |
1 |
|
|
T1 |
658 |
|
T11 |
1447 |
|
T12 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2928595 |
1 |
|
|
T1 |
331 |
|
T11 |
751 |
|
T12 |
41 |
| auto[1] |
auto[0] |
auto[1] |
430140 |
1 |
|
|
T1 |
11 |
|
T11 |
187 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2937232 |
1 |
|
|
T1 |
304 |
|
T11 |
412 |
|
T12 |
60 |
| auto[1] |
auto[1] |
auto[1] |
432994 |
1 |
|
|
T1 |
12 |
|
T11 |
97 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |