Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8992745 |
1 |
|
|
T23 |
349 |
|
T1 |
654 |
|
T11 |
1258 |
| auto[1] |
6706624 |
1 |
|
|
T1 |
643 |
|
T11 |
1210 |
|
T12 |
89 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14834599 |
1 |
|
|
T23 |
349 |
|
T1 |
1263 |
|
T11 |
2208 |
| auto[1] |
864770 |
1 |
|
|
T1 |
34 |
|
T11 |
260 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8956641 |
1 |
|
|
T23 |
349 |
|
T1 |
487 |
|
T11 |
1093 |
| auto[1] |
6742728 |
1 |
|
|
T1 |
810 |
|
T11 |
1375 |
|
T12 |
133 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2953796 |
1 |
|
|
T1 |
346 |
|
T11 |
647 |
|
T12 |
62 |
| auto[1] |
auto[0] |
auto[1] |
434201 |
1 |
|
|
T1 |
13 |
|
T11 |
153 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2924162 |
1 |
|
|
T1 |
430 |
|
T11 |
468 |
|
T12 |
62 |
| auto[1] |
auto[1] |
auto[1] |
430569 |
1 |
|
|
T1 |
21 |
|
T11 |
107 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |