Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8965603 |
1 |
|
|
T23 |
349 |
|
T1 |
802 |
|
T11 |
1255 |
| auto[1] |
6733766 |
1 |
|
|
T1 |
495 |
|
T11 |
1213 |
|
T12 |
103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14837600 |
1 |
|
|
T23 |
349 |
|
T1 |
1254 |
|
T11 |
2212 |
| auto[1] |
861769 |
1 |
|
|
T1 |
43 |
|
T11 |
256 |
|
T12 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8983843 |
1 |
|
|
T23 |
349 |
|
T1 |
355 |
|
T11 |
1180 |
| auto[1] |
6715526 |
1 |
|
|
T1 |
942 |
|
T11 |
1288 |
|
T12 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2915596 |
1 |
|
|
T1 |
591 |
|
T11 |
522 |
|
T12 |
63 |
| auto[1] |
auto[0] |
auto[1] |
427863 |
1 |
|
|
T1 |
26 |
|
T11 |
124 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2938161 |
1 |
|
|
T1 |
308 |
|
T11 |
510 |
|
T12 |
69 |
| auto[1] |
auto[1] |
auto[1] |
433906 |
1 |
|
|
T1 |
17 |
|
T11 |
132 |
|
T12 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |