Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8964316 |
1 |
|
|
T23 |
349 |
|
T1 |
786 |
|
T11 |
1674 |
| auto[1] |
6735053 |
1 |
|
|
T1 |
511 |
|
T11 |
794 |
|
T12 |
158 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14835435 |
1 |
|
|
T23 |
349 |
|
T1 |
1277 |
|
T11 |
2217 |
| auto[1] |
863934 |
1 |
|
|
T1 |
20 |
|
T11 |
251 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8967075 |
1 |
|
|
T23 |
349 |
|
T1 |
656 |
|
T11 |
1227 |
| auto[1] |
6732294 |
1 |
|
|
T1 |
641 |
|
T11 |
1241 |
|
T12 |
61 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2917966 |
1 |
|
|
T1 |
348 |
|
T11 |
620 |
|
T12 |
13 |
| auto[1] |
auto[0] |
auto[1] |
429675 |
1 |
|
|
T1 |
12 |
|
T11 |
158 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2950394 |
1 |
|
|
T1 |
273 |
|
T11 |
370 |
|
T12 |
43 |
| auto[1] |
auto[1] |
auto[1] |
434259 |
1 |
|
|
T1 |
8 |
|
T11 |
93 |
|
T12 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |