Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9029528 |
1 |
|
|
T23 |
349 |
|
T1 |
583 |
|
T11 |
1376 |
| auto[1] |
6669841 |
1 |
|
|
T1 |
714 |
|
T11 |
1092 |
|
T12 |
127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12974903 |
1 |
|
|
T23 |
349 |
|
T1 |
1110 |
|
T11 |
1695 |
| auto[1] |
2724466 |
1 |
|
|
T1 |
187 |
|
T11 |
773 |
|
T12 |
81 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8974461 |
1 |
|
|
T23 |
349 |
|
T1 |
524 |
|
T11 |
872 |
| auto[1] |
6724908 |
1 |
|
|
T1 |
773 |
|
T11 |
1596 |
|
T12 |
123 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2016816 |
1 |
|
|
T1 |
264 |
|
T11 |
485 |
|
T12 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1370537 |
1 |
|
|
T1 |
73 |
|
T11 |
468 |
|
T12 |
36 |
| auto[1] |
auto[1] |
auto[0] |
1983626 |
1 |
|
|
T1 |
322 |
|
T11 |
338 |
|
T12 |
28 |
| auto[1] |
auto[1] |
auto[1] |
1353929 |
1 |
|
|
T1 |
114 |
|
T11 |
305 |
|
T12 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |