Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8992828 |
1 |
|
|
T23 |
349 |
|
T1 |
650 |
|
T11 |
1065 |
| auto[1] |
6706541 |
1 |
|
|
T1 |
647 |
|
T11 |
1403 |
|
T12 |
125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12977802 |
1 |
|
|
T23 |
349 |
|
T1 |
1089 |
|
T11 |
1837 |
| auto[1] |
2721567 |
1 |
|
|
T1 |
208 |
|
T11 |
631 |
|
T12 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8969917 |
1 |
|
|
T23 |
349 |
|
T1 |
495 |
|
T11 |
1203 |
| auto[1] |
6729452 |
1 |
|
|
T1 |
802 |
|
T11 |
1265 |
|
T12 |
68 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2004325 |
1 |
|
|
T1 |
274 |
|
T11 |
260 |
|
T12 |
18 |
| auto[1] |
auto[0] |
auto[1] |
1358516 |
1 |
|
|
T1 |
115 |
|
T11 |
270 |
|
T12 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2003560 |
1 |
|
|
T1 |
320 |
|
T11 |
374 |
|
T12 |
24 |
| auto[1] |
auto[1] |
auto[1] |
1363051 |
1 |
|
|
T1 |
93 |
|
T11 |
361 |
|
T12 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |