Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8999275 |
1 |
|
|
T23 |
349 |
|
T1 |
895 |
|
T11 |
1233 |
| auto[1] |
6700094 |
1 |
|
|
T1 |
402 |
|
T11 |
1235 |
|
T12 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13001438 |
1 |
|
|
T23 |
349 |
|
T1 |
1164 |
|
T11 |
1840 |
| auto[1] |
2697931 |
1 |
|
|
T1 |
133 |
|
T11 |
628 |
|
T12 |
51 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9025605 |
1 |
|
|
T23 |
349 |
|
T1 |
662 |
|
T11 |
1214 |
| auto[1] |
6673764 |
1 |
|
|
T1 |
635 |
|
T11 |
1254 |
|
T12 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2000718 |
1 |
|
|
T1 |
393 |
|
T11 |
280 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1358178 |
1 |
|
|
T1 |
63 |
|
T11 |
289 |
|
T12 |
34 |
| auto[1] |
auto[1] |
auto[0] |
1975115 |
1 |
|
|
T1 |
109 |
|
T11 |
346 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
1339753 |
1 |
|
|
T1 |
70 |
|
T11 |
339 |
|
T12 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |