Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9018148 |
1 |
|
|
T23 |
349 |
|
T1 |
793 |
|
T11 |
1349 |
| auto[1] |
6681221 |
1 |
|
|
T1 |
504 |
|
T11 |
1119 |
|
T12 |
133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12977525 |
1 |
|
|
T23 |
349 |
|
T1 |
1139 |
|
T11 |
1730 |
| auto[1] |
2721844 |
1 |
|
|
T1 |
158 |
|
T11 |
738 |
|
T12 |
54 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8977747 |
1 |
|
|
T23 |
349 |
|
T1 |
718 |
|
T11 |
926 |
| auto[1] |
6721622 |
1 |
|
|
T1 |
579 |
|
T11 |
1542 |
|
T12 |
119 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2012466 |
1 |
|
|
T1 |
238 |
|
T11 |
404 |
|
T12 |
31 |
| auto[1] |
auto[0] |
auto[1] |
1367015 |
1 |
|
|
T1 |
132 |
|
T11 |
406 |
|
T12 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1987312 |
1 |
|
|
T1 |
183 |
|
T11 |
400 |
|
T12 |
34 |
| auto[1] |
auto[1] |
auto[1] |
1354829 |
1 |
|
|
T1 |
26 |
|
T11 |
332 |
|
T12 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |