Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9018000 |
1 |
|
|
T23 |
349 |
|
T1 |
882 |
|
T11 |
1173 |
| auto[1] |
6681369 |
1 |
|
|
T1 |
415 |
|
T11 |
1295 |
|
T12 |
126 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12970286 |
1 |
|
|
T23 |
349 |
|
T1 |
1111 |
|
T11 |
2039 |
| auto[1] |
2729083 |
1 |
|
|
T1 |
186 |
|
T11 |
429 |
|
T12 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8959729 |
1 |
|
|
T23 |
349 |
|
T1 |
734 |
|
T11 |
1574 |
| auto[1] |
6739640 |
1 |
|
|
T1 |
563 |
|
T11 |
894 |
|
T12 |
92 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020721 |
1 |
|
|
T1 |
268 |
|
T11 |
231 |
|
T12 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1371755 |
1 |
|
|
T1 |
150 |
|
T11 |
211 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1989836 |
1 |
|
|
T1 |
109 |
|
T11 |
234 |
|
T12 |
32 |
| auto[1] |
auto[1] |
auto[1] |
1357328 |
1 |
|
|
T1 |
36 |
|
T11 |
218 |
|
T12 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |