Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838132 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2258 |
| auto[1] |
861237 |
1 |
|
|
T1 |
25 |
|
T11 |
210 |
|
T12 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8982536 |
1 |
|
|
T23 |
349 |
|
T1 |
657 |
|
T11 |
1337 |
| auto[1] |
6716833 |
1 |
|
|
T1 |
640 |
|
T11 |
1131 |
|
T12 |
97 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2942167 |
1 |
|
|
T1 |
310 |
|
T11 |
397 |
|
T12 |
66 |
| auto[1] |
auto[0] |
auto[1] |
432629 |
1 |
|
|
T1 |
13 |
|
T11 |
89 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2913429 |
1 |
|
|
T1 |
305 |
|
T11 |
524 |
|
T12 |
28 |
| auto[1] |
auto[1] |
auto[1] |
428608 |
1 |
|
|
T1 |
12 |
|
T11 |
121 |
|
T15 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |