Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8991338 |
1 |
|
|
T23 |
349 |
|
T1 |
837 |
|
T11 |
1273 |
| auto[1] |
6708031 |
1 |
|
|
T1 |
460 |
|
T11 |
1195 |
|
T12 |
97 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12975179 |
1 |
|
|
T23 |
349 |
|
T1 |
1090 |
|
T11 |
1883 |
| auto[1] |
2724190 |
1 |
|
|
T1 |
207 |
|
T11 |
585 |
|
T12 |
73 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8973706 |
1 |
|
|
T23 |
349 |
|
T1 |
644 |
|
T11 |
1273 |
| auto[1] |
6725663 |
1 |
|
|
T1 |
653 |
|
T11 |
1195 |
|
T12 |
128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2004956 |
1 |
|
|
T1 |
262 |
|
T11 |
349 |
|
T12 |
32 |
| auto[1] |
auto[0] |
auto[1] |
1359985 |
1 |
|
|
T1 |
140 |
|
T11 |
322 |
|
T12 |
35 |
| auto[1] |
auto[1] |
auto[0] |
1996517 |
1 |
|
|
T1 |
184 |
|
T11 |
261 |
|
T12 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1364205 |
1 |
|
|
T1 |
67 |
|
T11 |
263 |
|
T12 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |