Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9013891 |
1 |
|
|
T23 |
349 |
|
T1 |
644 |
|
T11 |
1356 |
| auto[1] |
6685478 |
1 |
|
|
T1 |
653 |
|
T11 |
1112 |
|
T12 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12989256 |
1 |
|
|
T23 |
349 |
|
T1 |
1111 |
|
T11 |
1882 |
| auto[1] |
2710113 |
1 |
|
|
T1 |
186 |
|
T11 |
586 |
|
T12 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8991277 |
1 |
|
|
T23 |
349 |
|
T1 |
640 |
|
T11 |
1273 |
| auto[1] |
6708092 |
1 |
|
|
T1 |
657 |
|
T11 |
1195 |
|
T12 |
140 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1995689 |
1 |
|
|
T1 |
242 |
|
T11 |
366 |
|
T12 |
54 |
| auto[1] |
auto[0] |
auto[1] |
1353016 |
1 |
|
|
T1 |
91 |
|
T11 |
316 |
|
T12 |
34 |
| auto[1] |
auto[1] |
auto[0] |
2002290 |
1 |
|
|
T1 |
229 |
|
T11 |
243 |
|
T12 |
42 |
| auto[1] |
auto[1] |
auto[1] |
1357097 |
1 |
|
|
T1 |
95 |
|
T11 |
270 |
|
T12 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |