Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9025629 |
1 |
|
|
T23 |
349 |
|
T1 |
583 |
|
T11 |
1203 |
| auto[1] |
6673740 |
1 |
|
|
T1 |
714 |
|
T11 |
1265 |
|
T12 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12985196 |
1 |
|
|
T23 |
349 |
|
T1 |
1195 |
|
T11 |
1828 |
| auto[1] |
2714173 |
1 |
|
|
T1 |
102 |
|
T11 |
640 |
|
T12 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9000707 |
1 |
|
|
T23 |
349 |
|
T1 |
761 |
|
T11 |
1265 |
| auto[1] |
6698662 |
1 |
|
|
T1 |
536 |
|
T11 |
1203 |
|
T12 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2006650 |
1 |
|
|
T1 |
198 |
|
T11 |
267 |
|
T12 |
38 |
| auto[1] |
auto[0] |
auto[1] |
1371199 |
1 |
|
|
T1 |
50 |
|
T11 |
303 |
|
T12 |
23 |
| auto[1] |
auto[1] |
auto[0] |
1977839 |
1 |
|
|
T1 |
236 |
|
T11 |
296 |
|
T12 |
22 |
| auto[1] |
auto[1] |
auto[1] |
1342974 |
1 |
|
|
T1 |
52 |
|
T11 |
337 |
|
T12 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |