Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8979506 |
1 |
|
|
T23 |
349 |
|
T1 |
626 |
|
T11 |
1458 |
| auto[1] |
6719863 |
1 |
|
|
T1 |
671 |
|
T11 |
1010 |
|
T12 |
133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12979136 |
1 |
|
|
T23 |
349 |
|
T1 |
1096 |
|
T11 |
1713 |
| auto[1] |
2720233 |
1 |
|
|
T1 |
201 |
|
T11 |
755 |
|
T12 |
73 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8975171 |
1 |
|
|
T23 |
349 |
|
T1 |
491 |
|
T11 |
1002 |
| auto[1] |
6724198 |
1 |
|
|
T1 |
806 |
|
T11 |
1466 |
|
T12 |
108 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2011341 |
1 |
|
|
T1 |
370 |
|
T11 |
433 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1359423 |
1 |
|
|
T1 |
78 |
|
T11 |
430 |
|
T12 |
29 |
| auto[1] |
auto[1] |
auto[0] |
1992624 |
1 |
|
|
T1 |
235 |
|
T11 |
278 |
|
T12 |
29 |
| auto[1] |
auto[1] |
auto[1] |
1360810 |
1 |
|
|
T1 |
123 |
|
T11 |
325 |
|
T12 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |