Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9001481 |
1 |
|
|
T23 |
349 |
|
T1 |
699 |
|
T11 |
1273 |
| auto[1] |
6697888 |
1 |
|
|
T1 |
598 |
|
T11 |
1195 |
|
T12 |
121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12995666 |
1 |
|
|
T23 |
349 |
|
T1 |
1191 |
|
T11 |
1972 |
| auto[1] |
2703703 |
1 |
|
|
T1 |
106 |
|
T11 |
496 |
|
T12 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9019348 |
1 |
|
|
T23 |
349 |
|
T1 |
721 |
|
T11 |
1443 |
| auto[1] |
6680021 |
1 |
|
|
T1 |
576 |
|
T11 |
1025 |
|
T12 |
97 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2007994 |
1 |
|
|
T1 |
286 |
|
T11 |
257 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1360703 |
1 |
|
|
T1 |
59 |
|
T11 |
230 |
|
T12 |
40 |
| auto[1] |
auto[1] |
auto[0] |
1968324 |
1 |
|
|
T1 |
184 |
|
T11 |
272 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1343000 |
1 |
|
|
T1 |
47 |
|
T11 |
266 |
|
T12 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |