Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8996269 |
1 |
|
|
T23 |
349 |
|
T1 |
648 |
|
T11 |
1391 |
| auto[1] |
6703100 |
1 |
|
|
T1 |
649 |
|
T11 |
1077 |
|
T12 |
150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12981290 |
1 |
|
|
T23 |
349 |
|
T1 |
1148 |
|
T11 |
1923 |
| auto[1] |
2718079 |
1 |
|
|
T1 |
149 |
|
T11 |
545 |
|
T12 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8970353 |
1 |
|
|
T23 |
349 |
|
T1 |
634 |
|
T11 |
1364 |
| auto[1] |
6729016 |
1 |
|
|
T1 |
663 |
|
T11 |
1104 |
|
T12 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020578 |
1 |
|
|
T1 |
202 |
|
T11 |
321 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1368794 |
1 |
|
|
T1 |
65 |
|
T11 |
334 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1990359 |
1 |
|
|
T1 |
312 |
|
T11 |
238 |
|
T12 |
41 |
| auto[1] |
auto[1] |
auto[1] |
1349285 |
1 |
|
|
T1 |
84 |
|
T11 |
211 |
|
T12 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |