Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942240 |
1 |
|
|
T23 |
349 |
|
T1 |
597 |
|
T11 |
1310 |
| auto[1] |
6757129 |
1 |
|
|
T1 |
700 |
|
T11 |
1158 |
|
T12 |
126 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12988000 |
1 |
|
|
T23 |
349 |
|
T1 |
1163 |
|
T11 |
1621 |
| auto[1] |
2711369 |
1 |
|
|
T1 |
134 |
|
T11 |
847 |
|
T12 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9005738 |
1 |
|
|
T23 |
349 |
|
T1 |
707 |
|
T11 |
681 |
| auto[1] |
6693631 |
1 |
|
|
T1 |
590 |
|
T11 |
1787 |
|
T12 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1963131 |
1 |
|
|
T1 |
229 |
|
T11 |
510 |
|
T12 |
23 |
| auto[1] |
auto[0] |
auto[1] |
1347028 |
1 |
|
|
T1 |
71 |
|
T11 |
482 |
|
T12 |
30 |
| auto[1] |
auto[1] |
auto[0] |
2019131 |
1 |
|
|
T1 |
227 |
|
T11 |
430 |
|
T12 |
46 |
| auto[1] |
auto[1] |
auto[1] |
1364341 |
1 |
|
|
T1 |
63 |
|
T11 |
365 |
|
T12 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |