Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8971399 |
1 |
|
|
T23 |
349 |
|
T1 |
547 |
|
T11 |
1123 |
| auto[1] |
6727970 |
1 |
|
|
T1 |
750 |
|
T11 |
1345 |
|
T12 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12993102 |
1 |
|
|
T23 |
349 |
|
T1 |
1138 |
|
T11 |
1847 |
| auto[1] |
2706267 |
1 |
|
|
T1 |
159 |
|
T11 |
621 |
|
T12 |
53 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9017080 |
1 |
|
|
T23 |
349 |
|
T1 |
596 |
|
T11 |
1199 |
| auto[1] |
6682289 |
1 |
|
|
T1 |
701 |
|
T11 |
1269 |
|
T12 |
104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1989058 |
1 |
|
|
T1 |
221 |
|
T11 |
309 |
|
T12 |
36 |
| auto[1] |
auto[0] |
auto[1] |
1352736 |
1 |
|
|
T1 |
65 |
|
T11 |
330 |
|
T12 |
31 |
| auto[1] |
auto[1] |
auto[0] |
1986964 |
1 |
|
|
T1 |
321 |
|
T11 |
339 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
1353531 |
1 |
|
|
T1 |
94 |
|
T11 |
291 |
|
T12 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |