Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9005366 |
1 |
|
|
T23 |
349 |
|
T1 |
712 |
|
T11 |
1321 |
| auto[1] |
6694003 |
1 |
|
|
T1 |
585 |
|
T11 |
1147 |
|
T12 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12983740 |
1 |
|
|
T23 |
349 |
|
T1 |
1156 |
|
T11 |
1729 |
| auto[1] |
2715629 |
1 |
|
|
T1 |
141 |
|
T11 |
739 |
|
T12 |
59 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8998734 |
1 |
|
|
T23 |
349 |
|
T1 |
680 |
|
T11 |
1040 |
| auto[1] |
6700635 |
1 |
|
|
T1 |
617 |
|
T11 |
1428 |
|
T12 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2000787 |
1 |
|
|
T1 |
230 |
|
T11 |
391 |
|
T12 |
27 |
| auto[1] |
auto[0] |
auto[1] |
1367497 |
1 |
|
|
T1 |
68 |
|
T11 |
442 |
|
T12 |
36 |
| auto[1] |
auto[1] |
auto[0] |
1984219 |
1 |
|
|
T1 |
246 |
|
T11 |
298 |
|
T12 |
14 |
| auto[1] |
auto[1] |
auto[1] |
1348132 |
1 |
|
|
T1 |
73 |
|
T11 |
297 |
|
T12 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |