Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940129 |
1 |
|
|
T23 |
349 |
|
T1 |
605 |
|
T11 |
1191 |
| auto[1] |
6759240 |
1 |
|
|
T1 |
692 |
|
T11 |
1277 |
|
T12 |
111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12984744 |
1 |
|
|
T23 |
349 |
|
T1 |
1158 |
|
T11 |
1826 |
| auto[1] |
2714625 |
1 |
|
|
T1 |
139 |
|
T11 |
642 |
|
T12 |
58 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8999437 |
1 |
|
|
T23 |
349 |
|
T1 |
586 |
|
T11 |
1251 |
| auto[1] |
6699932 |
1 |
|
|
T1 |
711 |
|
T11 |
1217 |
|
T12 |
128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1979079 |
1 |
|
|
T1 |
231 |
|
T11 |
239 |
|
T12 |
39 |
| auto[1] |
auto[0] |
auto[1] |
1351478 |
1 |
|
|
T1 |
62 |
|
T11 |
270 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2006228 |
1 |
|
|
T1 |
341 |
|
T11 |
336 |
|
T12 |
31 |
| auto[1] |
auto[1] |
auto[1] |
1363147 |
1 |
|
|
T1 |
77 |
|
T11 |
372 |
|
T12 |
31 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |