Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8968062 |
1 |
|
|
T23 |
349 |
|
T1 |
625 |
|
T11 |
1167 |
| auto[1] |
6731307 |
1 |
|
|
T1 |
672 |
|
T11 |
1301 |
|
T12 |
90 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838067 |
1 |
|
|
T23 |
349 |
|
T1 |
1271 |
|
T11 |
2220 |
| auto[1] |
861302 |
1 |
|
|
T1 |
26 |
|
T11 |
248 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8987611 |
1 |
|
|
T23 |
349 |
|
T1 |
676 |
|
T11 |
1125 |
| auto[1] |
6711758 |
1 |
|
|
T1 |
621 |
|
T11 |
1343 |
|
T12 |
73 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2924143 |
1 |
|
|
T1 |
292 |
|
T11 |
563 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
429766 |
1 |
|
|
T1 |
12 |
|
T11 |
121 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2926313 |
1 |
|
|
T1 |
303 |
|
T11 |
532 |
|
T12 |
28 |
| auto[1] |
auto[1] |
auto[1] |
431536 |
1 |
|
|
T1 |
14 |
|
T11 |
127 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |