Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9027915 |
1 |
|
|
T23 |
349 |
|
T1 |
685 |
|
T11 |
1056 |
| auto[1] |
6671454 |
1 |
|
|
T1 |
612 |
|
T11 |
1412 |
|
T12 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12977203 |
1 |
|
|
T23 |
349 |
|
T1 |
1175 |
|
T11 |
1886 |
| auto[1] |
2722166 |
1 |
|
|
T1 |
122 |
|
T11 |
582 |
|
T12 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8966218 |
1 |
|
|
T23 |
349 |
|
T1 |
716 |
|
T11 |
1265 |
| auto[1] |
6733151 |
1 |
|
|
T1 |
581 |
|
T11 |
1203 |
|
T12 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2005572 |
1 |
|
|
T1 |
215 |
|
T11 |
245 |
|
T12 |
37 |
| auto[1] |
auto[0] |
auto[1] |
1365013 |
1 |
|
|
T1 |
65 |
|
T11 |
288 |
|
T12 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2005413 |
1 |
|
|
T1 |
244 |
|
T11 |
376 |
|
T12 |
30 |
| auto[1] |
auto[1] |
auto[1] |
1357153 |
1 |
|
|
T1 |
57 |
|
T11 |
294 |
|
T12 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |