Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8934016 |
1 |
|
|
T23 |
349 |
|
T1 |
661 |
|
T11 |
1066 |
| auto[1] |
6765353 |
1 |
|
|
T1 |
636 |
|
T11 |
1402 |
|
T12 |
70 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12997756 |
1 |
|
|
T23 |
349 |
|
T1 |
1094 |
|
T11 |
1989 |
| auto[1] |
2701613 |
1 |
|
|
T1 |
203 |
|
T11 |
479 |
|
T12 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9011055 |
1 |
|
|
T23 |
349 |
|
T1 |
499 |
|
T11 |
1451 |
| auto[1] |
6688314 |
1 |
|
|
T1 |
798 |
|
T11 |
1017 |
|
T12 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1981521 |
1 |
|
|
T1 |
309 |
|
T11 |
211 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1345559 |
1 |
|
|
T1 |
122 |
|
T11 |
227 |
|
T12 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2005180 |
1 |
|
|
T1 |
286 |
|
T11 |
327 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[1] |
1356054 |
1 |
|
|
T1 |
81 |
|
T11 |
252 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |