Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972962 |
1 |
|
|
T23 |
349 |
|
T1 |
708 |
|
T11 |
1705 |
| auto[1] |
6726407 |
1 |
|
|
T1 |
589 |
|
T11 |
763 |
|
T12 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12975376 |
1 |
|
|
T23 |
349 |
|
T1 |
1159 |
|
T11 |
1760 |
| auto[1] |
2723993 |
1 |
|
|
T1 |
138 |
|
T11 |
708 |
|
T12 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8973474 |
1 |
|
|
T23 |
349 |
|
T1 |
708 |
|
T11 |
1184 |
| auto[1] |
6725895 |
1 |
|
|
T1 |
589 |
|
T11 |
1284 |
|
T12 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1983379 |
1 |
|
|
T1 |
222 |
|
T11 |
413 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1355529 |
1 |
|
|
T1 |
61 |
|
T11 |
447 |
|
T12 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2018523 |
1 |
|
|
T1 |
229 |
|
T11 |
163 |
|
T12 |
40 |
| auto[1] |
auto[1] |
auto[1] |
1368464 |
1 |
|
|
T1 |
77 |
|
T11 |
261 |
|
T12 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |