Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8987717 |
1 |
|
|
T23 |
349 |
|
T1 |
585 |
|
T11 |
1411 |
| auto[1] |
6711652 |
1 |
|
|
T1 |
712 |
|
T11 |
1057 |
|
T12 |
91 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838216 |
1 |
|
|
T23 |
349 |
|
T1 |
1273 |
|
T11 |
2258 |
| auto[1] |
861153 |
1 |
|
|
T1 |
24 |
|
T11 |
210 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8989338 |
1 |
|
|
T23 |
349 |
|
T1 |
606 |
|
T11 |
1357 |
| auto[1] |
6710031 |
1 |
|
|
T1 |
691 |
|
T11 |
1111 |
|
T12 |
140 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2921464 |
1 |
|
|
T1 |
285 |
|
T11 |
548 |
|
T12 |
64 |
| auto[1] |
auto[0] |
auto[1] |
429999 |
1 |
|
|
T1 |
11 |
|
T11 |
131 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2927414 |
1 |
|
|
T1 |
382 |
|
T11 |
353 |
|
T12 |
67 |
| auto[1] |
auto[1] |
auto[1] |
431154 |
1 |
|
|
T1 |
13 |
|
T11 |
79 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |