Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8964688 |
1 |
|
|
T23 |
349 |
|
T1 |
703 |
|
T11 |
1611 |
| auto[1] |
6734681 |
1 |
|
|
T1 |
594 |
|
T11 |
857 |
|
T12 |
115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14835375 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2226 |
| auto[1] |
863994 |
1 |
|
|
T1 |
25 |
|
T11 |
242 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8966335 |
1 |
|
|
T23 |
349 |
|
T1 |
630 |
|
T11 |
1242 |
| auto[1] |
6733034 |
1 |
|
|
T1 |
667 |
|
T11 |
1226 |
|
T12 |
124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2918329 |
1 |
|
|
T1 |
355 |
|
T11 |
656 |
|
T12 |
54 |
| auto[1] |
auto[0] |
auto[1] |
428450 |
1 |
|
|
T1 |
14 |
|
T11 |
171 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2950711 |
1 |
|
|
T1 |
287 |
|
T11 |
328 |
|
T12 |
61 |
| auto[1] |
auto[1] |
auto[1] |
435544 |
1 |
|
|
T1 |
11 |
|
T11 |
71 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |