Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9011577 |
1 |
|
|
T23 |
349 |
|
T1 |
662 |
|
T11 |
1281 |
| auto[1] |
6687792 |
1 |
|
|
T1 |
635 |
|
T11 |
1187 |
|
T12 |
89 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838261 |
1 |
|
|
T23 |
349 |
|
T1 |
1260 |
|
T11 |
2255 |
| auto[1] |
861108 |
1 |
|
|
T1 |
37 |
|
T11 |
213 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8985011 |
1 |
|
|
T23 |
349 |
|
T1 |
473 |
|
T11 |
1385 |
| auto[1] |
6714358 |
1 |
|
|
T1 |
824 |
|
T11 |
1083 |
|
T12 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2933158 |
1 |
|
|
T1 |
392 |
|
T11 |
394 |
|
T12 |
57 |
| auto[1] |
auto[0] |
auto[1] |
431019 |
1 |
|
|
T1 |
13 |
|
T11 |
99 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2920092 |
1 |
|
|
T1 |
395 |
|
T11 |
476 |
|
T12 |
35 |
| auto[1] |
auto[1] |
auto[1] |
430089 |
1 |
|
|
T1 |
24 |
|
T11 |
114 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |