Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8975430 |
1 |
|
|
T23 |
349 |
|
T1 |
647 |
|
T11 |
1070 |
| auto[1] |
6723939 |
1 |
|
|
T1 |
650 |
|
T11 |
1398 |
|
T12 |
81 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14838275 |
1 |
|
|
T23 |
349 |
|
T1 |
1261 |
|
T11 |
2163 |
| auto[1] |
861094 |
1 |
|
|
T1 |
36 |
|
T11 |
305 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8980398 |
1 |
|
|
T23 |
349 |
|
T1 |
502 |
|
T11 |
848 |
| auto[1] |
6718971 |
1 |
|
|
T1 |
795 |
|
T11 |
1620 |
|
T12 |
173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2921347 |
1 |
|
|
T1 |
356 |
|
T11 |
588 |
|
T12 |
94 |
| auto[1] |
auto[0] |
auto[1] |
429042 |
1 |
|
|
T1 |
18 |
|
T11 |
137 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2936530 |
1 |
|
|
T1 |
403 |
|
T11 |
727 |
|
T12 |
70 |
| auto[1] |
auto[1] |
auto[1] |
432052 |
1 |
|
|
T1 |
18 |
|
T11 |
168 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |