Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8986928 |
1 |
|
|
T23 |
349 |
|
T1 |
796 |
|
T11 |
1204 |
| auto[1] |
6712441 |
1 |
|
|
T1 |
501 |
|
T11 |
1264 |
|
T12 |
64 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14836543 |
1 |
|
|
T23 |
349 |
|
T1 |
1270 |
|
T11 |
2168 |
| auto[1] |
862826 |
1 |
|
|
T1 |
27 |
|
T11 |
300 |
|
T12 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8970318 |
1 |
|
|
T23 |
349 |
|
T1 |
582 |
|
T11 |
1028 |
| auto[1] |
6729051 |
1 |
|
|
T1 |
715 |
|
T11 |
1440 |
|
T12 |
123 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2946845 |
1 |
|
|
T1 |
388 |
|
T11 |
482 |
|
T12 |
81 |
| auto[1] |
auto[0] |
auto[1] |
433546 |
1 |
|
|
T1 |
15 |
|
T11 |
132 |
|
T12 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2919380 |
1 |
|
|
T1 |
300 |
|
T11 |
658 |
|
T12 |
32 |
| auto[1] |
auto[1] |
auto[1] |
429280 |
1 |
|
|
T1 |
12 |
|
T11 |
168 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |