Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8980707 |
1 |
|
|
T23 |
349 |
|
T1 |
696 |
|
T11 |
1077 |
| auto[1] |
6718662 |
1 |
|
|
T1 |
601 |
|
T11 |
1391 |
|
T12 |
108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14836372 |
1 |
|
|
T23 |
349 |
|
T1 |
1272 |
|
T11 |
2209 |
| auto[1] |
862997 |
1 |
|
|
T1 |
25 |
|
T11 |
259 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8981369 |
1 |
|
|
T23 |
349 |
|
T1 |
551 |
|
T11 |
1150 |
| auto[1] |
6718000 |
1 |
|
|
T1 |
746 |
|
T11 |
1318 |
|
T12 |
112 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2931976 |
1 |
|
|
T1 |
351 |
|
T11 |
402 |
|
T12 |
50 |
| auto[1] |
auto[0] |
auto[1] |
432827 |
1 |
|
|
T1 |
17 |
|
T11 |
106 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2923027 |
1 |
|
|
T1 |
370 |
|
T11 |
657 |
|
T12 |
53 |
| auto[1] |
auto[1] |
auto[1] |
430170 |
1 |
|
|
T1 |
8 |
|
T11 |
153 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |