Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 948
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T767 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2296507681 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:31 PM PDT 24 135261451 ps
T768 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1419383925 Jun 07 07:32:39 PM PDT 24 Jun 07 07:32:45 PM PDT 24 235302218 ps
T769 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2610784134 Jun 07 07:32:48 PM PDT 24 Jun 07 07:32:52 PM PDT 24 44416814 ps
T770 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1106196196 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:12 PM PDT 24 54416742 ps
T771 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2302765989 Jun 07 07:32:37 PM PDT 24 Jun 07 07:32:43 PM PDT 24 20406645 ps
T38 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2908066102 Jun 07 07:32:31 PM PDT 24 Jun 07 07:32:37 PM PDT 24 137077372 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2936860200 Jun 07 07:32:31 PM PDT 24 Jun 07 07:32:37 PM PDT 24 82517714 ps
T773 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2225491901 Jun 07 07:33:06 PM PDT 24 Jun 07 07:33:10 PM PDT 24 160479021 ps
T774 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1355117420 Jun 07 07:33:04 PM PDT 24 Jun 07 07:33:08 PM PDT 24 97450899 ps
T775 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1803831263 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:29 PM PDT 24 45328691 ps
T776 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.595998179 Jun 07 07:32:23 PM PDT 24 Jun 07 07:32:32 PM PDT 24 184317231 ps
T777 /workspace/coverage/cover_reg_top/25.gpio_intr_test.273309465 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:06 PM PDT 24 42561354 ps
T778 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3537192686 Jun 07 07:32:51 PM PDT 24 Jun 07 07:32:53 PM PDT 24 58889706 ps
T779 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.773052613 Jun 07 07:32:54 PM PDT 24 Jun 07 07:32:57 PM PDT 24 563933933 ps
T780 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1566332119 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:06 PM PDT 24 43503284 ps
T90 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2760981705 Jun 07 07:32:23 PM PDT 24 Jun 07 07:32:30 PM PDT 24 60519302 ps
T39 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1163211123 Jun 07 07:32:34 PM PDT 24 Jun 07 07:32:41 PM PDT 24 431910294 ps
T781 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1292937855 Jun 07 07:32:34 PM PDT 24 Jun 07 07:32:41 PM PDT 24 121215128 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3331507376 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:29 PM PDT 24 20775032 ps
T42 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.8368118 Jun 07 07:32:21 PM PDT 24 Jun 07 07:32:28 PM PDT 24 422743583 ps
T783 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.863060554 Jun 07 07:32:32 PM PDT 24 Jun 07 07:32:38 PM PDT 24 478993762 ps
T784 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1680637415 Jun 07 07:32:35 PM PDT 24 Jun 07 07:32:42 PM PDT 24 29767412 ps
T785 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3407058195 Jun 07 07:32:32 PM PDT 24 Jun 07 07:32:38 PM PDT 24 234320201 ps
T786 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3187895044 Jun 07 07:32:37 PM PDT 24 Jun 07 07:32:43 PM PDT 24 44718819 ps
T787 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2773298296 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:05 PM PDT 24 45561986 ps
T788 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.513243068 Jun 07 07:32:38 PM PDT 24 Jun 07 07:32:45 PM PDT 24 17851539 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3140282923 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:31 PM PDT 24 1051791404 ps
T789 /workspace/coverage/cover_reg_top/22.gpio_intr_test.646972213 Jun 07 07:33:05 PM PDT 24 Jun 07 07:33:09 PM PDT 24 42424828 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.171974867 Jun 07 07:32:41 PM PDT 24 Jun 07 07:32:47 PM PDT 24 106923000 ps
T791 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1750066703 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:05 PM PDT 24 23000228 ps
T91 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3836679637 Jun 07 07:32:31 PM PDT 24 Jun 07 07:32:37 PM PDT 24 11205897 ps
T792 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2349580446 Jun 07 07:32:54 PM PDT 24 Jun 07 07:32:58 PM PDT 24 173274675 ps
T43 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2565147752 Jun 07 07:32:26 PM PDT 24 Jun 07 07:32:34 PM PDT 24 184922434 ps
T793 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2882104874 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:29 PM PDT 24 25145884 ps
T794 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2837776 Jun 07 07:32:37 PM PDT 24 Jun 07 07:32:43 PM PDT 24 241846731 ps
T795 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1061643056 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:06 PM PDT 24 37654680 ps
T92 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2597065423 Jun 07 07:32:24 PM PDT 24 Jun 07 07:32:31 PM PDT 24 38176673 ps
T93 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2185206112 Jun 07 07:32:38 PM PDT 24 Jun 07 07:32:44 PM PDT 24 14939185 ps
T99 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.196039195 Jun 07 07:32:33 PM PDT 24 Jun 07 07:32:38 PM PDT 24 14278130 ps
T796 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1113636013 Jun 07 07:32:34 PM PDT 24 Jun 07 07:32:40 PM PDT 24 15404891 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.250364769 Jun 07 07:32:36 PM PDT 24 Jun 07 07:32:42 PM PDT 24 81527987 ps
T798 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3347859580 Jun 07 07:33:08 PM PDT 24 Jun 07 07:33:13 PM PDT 24 48622499 ps
T799 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2819891948 Jun 07 07:32:41 PM PDT 24 Jun 07 07:32:46 PM PDT 24 75862597 ps
T800 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2965927252 Jun 07 07:32:38 PM PDT 24 Jun 07 07:32:46 PM PDT 24 38814922 ps
T801 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4048535459 Jun 07 07:32:45 PM PDT 24 Jun 07 07:32:48 PM PDT 24 69690718 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_intr_test.290823237 Jun 07 07:32:41 PM PDT 24 Jun 07 07:32:46 PM PDT 24 23764953 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4020920426 Jun 07 07:32:30 PM PDT 24 Jun 07 07:32:38 PM PDT 24 1433092557 ps
T803 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4190023562 Jun 07 07:32:46 PM PDT 24 Jun 07 07:32:49 PM PDT 24 31326340 ps
T804 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.91590593 Jun 07 07:32:35 PM PDT 24 Jun 07 07:32:42 PM PDT 24 37148778 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3549244805 Jun 07 07:32:36 PM PDT 24 Jun 07 07:32:42 PM PDT 24 19566296 ps
T45 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2707281907 Jun 07 07:32:40 PM PDT 24 Jun 07 07:32:46 PM PDT 24 85452405 ps
T806 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3420317053 Jun 07 07:33:04 PM PDT 24 Jun 07 07:33:07 PM PDT 24 18699811 ps
T807 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.620843039 Jun 07 07:32:53 PM PDT 24 Jun 07 07:32:55 PM PDT 24 43260648 ps
T808 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1860340611 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:06 PM PDT 24 170764017 ps
T809 /workspace/coverage/cover_reg_top/12.gpio_intr_test.385814580 Jun 07 07:32:39 PM PDT 24 Jun 07 07:32:45 PM PDT 24 16563883 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2115908622 Jun 07 07:32:50 PM PDT 24 Jun 07 07:32:52 PM PDT 24 39671202 ps
T98 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.964974368 Jun 07 07:32:45 PM PDT 24 Jun 07 07:32:48 PM PDT 24 41331479 ps
T811 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.885543294 Jun 07 07:32:24 PM PDT 24 Jun 07 07:32:32 PM PDT 24 188881353 ps
T812 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.76625002 Jun 07 07:32:40 PM PDT 24 Jun 07 07:32:47 PM PDT 24 194003214 ps
T813 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3155460257 Jun 07 07:32:38 PM PDT 24 Jun 07 07:32:44 PM PDT 24 28212562 ps
T814 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.713924141 Jun 07 07:32:38 PM PDT 24 Jun 07 07:32:44 PM PDT 24 14928778 ps
T815 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1953313022 Jun 07 07:32:32 PM PDT 24 Jun 07 07:32:37 PM PDT 24 22763154 ps
T816 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3262333574 Jun 07 07:32:21 PM PDT 24 Jun 07 07:32:28 PM PDT 24 19454905 ps
T96 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.304349995 Jun 07 07:32:16 PM PDT 24 Jun 07 07:32:22 PM PDT 24 16921977 ps
T817 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1992739806 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:06 PM PDT 24 17046860 ps
T818 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3186038830 Jun 07 07:32:42 PM PDT 24 Jun 07 07:32:48 PM PDT 24 329598009 ps
T819 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1757256307 Jun 07 07:33:05 PM PDT 24 Jun 07 07:33:09 PM PDT 24 49632610 ps
T97 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3666916287 Jun 07 07:32:21 PM PDT 24 Jun 07 07:32:29 PM PDT 24 34677043 ps
T820 /workspace/coverage/cover_reg_top/42.gpio_intr_test.888562156 Jun 07 07:33:13 PM PDT 24 Jun 07 07:33:19 PM PDT 24 21558354 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2030939551 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:28 PM PDT 24 15464283 ps
T822 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1304336118 Jun 07 07:32:33 PM PDT 24 Jun 07 07:32:38 PM PDT 24 28776296 ps
T100 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1806170762 Jun 07 07:32:51 PM PDT 24 Jun 07 07:32:53 PM PDT 24 15595391 ps
T823 /workspace/coverage/cover_reg_top/30.gpio_intr_test.45481595 Jun 07 07:33:05 PM PDT 24 Jun 07 07:33:09 PM PDT 24 90627127 ps
T824 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2976383675 Jun 07 07:33:06 PM PDT 24 Jun 07 07:33:12 PM PDT 24 67590453 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.722369691 Jun 07 07:32:55 PM PDT 24 Jun 07 07:32:58 PM PDT 24 293244560 ps
T826 /workspace/coverage/cover_reg_top/28.gpio_intr_test.247492497 Jun 07 07:33:05 PM PDT 24 Jun 07 07:33:09 PM PDT 24 40514063 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4148564468 Jun 07 07:32:30 PM PDT 24 Jun 07 07:32:36 PM PDT 24 16610044 ps
T828 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2113850271 Jun 07 07:32:54 PM PDT 24 Jun 07 07:32:56 PM PDT 24 36873476 ps
T829 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3139983013 Jun 07 07:32:32 PM PDT 24 Jun 07 07:32:37 PM PDT 24 20395349 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4145669754 Jun 07 07:32:20 PM PDT 24 Jun 07 07:32:26 PM PDT 24 66788619 ps
T831 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2626177625 Jun 07 07:33:06 PM PDT 24 Jun 07 07:33:11 PM PDT 24 21779021 ps
T832 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3092891740 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:05 PM PDT 24 13614022 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1453838383 Jun 07 07:32:16 PM PDT 24 Jun 07 07:32:21 PM PDT 24 25211329 ps
T834 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2966746381 Jun 07 07:32:39 PM PDT 24 Jun 07 07:32:45 PM PDT 24 187471857 ps
T835 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1416820724 Jun 07 07:32:41 PM PDT 24 Jun 07 07:32:46 PM PDT 24 49517980 ps
T836 /workspace/coverage/cover_reg_top/41.gpio_intr_test.883756040 Jun 07 07:33:05 PM PDT 24 Jun 07 07:33:09 PM PDT 24 14061433 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1361552492 Jun 07 07:32:33 PM PDT 24 Jun 07 07:32:40 PM PDT 24 175400798 ps
T838 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.995349412 Jun 07 07:32:53 PM PDT 24 Jun 07 07:32:55 PM PDT 24 343110465 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.145850170 Jun 07 07:32:55 PM PDT 24 Jun 07 07:32:57 PM PDT 24 24196730 ps
T840 /workspace/coverage/cover_reg_top/17.gpio_intr_test.317979276 Jun 07 07:32:53 PM PDT 24 Jun 07 07:32:54 PM PDT 24 13676021 ps
T841 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1680323098 Jun 07 07:32:49 PM PDT 24 Jun 07 07:32:51 PM PDT 24 44410006 ps
T842 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1477620847 Jun 07 07:32:33 PM PDT 24 Jun 07 07:32:40 PM PDT 24 432472026 ps
T843 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2062420517 Jun 07 07:32:40 PM PDT 24 Jun 07 07:32:47 PM PDT 24 51738757 ps
T844 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1511073338 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:29 PM PDT 24 96648957 ps
T845 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1569800967 Jun 07 07:33:03 PM PDT 24 Jun 07 07:33:05 PM PDT 24 17933083 ps
T846 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3947195583 Jun 07 07:32:51 PM PDT 24 Jun 07 07:32:53 PM PDT 24 40342030 ps
T847 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.727940675 Jun 07 07:32:40 PM PDT 24 Jun 07 07:32:46 PM PDT 24 103067939 ps
T848 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1140354661 Jun 07 07:32:38 PM PDT 24 Jun 07 07:32:44 PM PDT 24 56416948 ps
T849 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.260553762 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:42 PM PDT 24 88160709 ps
T850 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3431721143 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:41 PM PDT 24 76251001 ps
T851 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1295586618 Jun 07 08:03:55 PM PDT 24 Jun 07 08:03:57 PM PDT 24 39801327 ps
T852 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353668838 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 82237530 ps
T853 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1806894512 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 66592664 ps
T854 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2050683652 Jun 07 08:04:35 PM PDT 24 Jun 07 08:04:37 PM PDT 24 198140143 ps
T855 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.948703537 Jun 07 08:04:24 PM PDT 24 Jun 07 08:04:27 PM PDT 24 29071290 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2503963681 Jun 07 08:04:26 PM PDT 24 Jun 07 08:04:29 PM PDT 24 392635227 ps
T857 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2590211785 Jun 07 08:04:40 PM PDT 24 Jun 07 08:04:44 PM PDT 24 263341586 ps
T858 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4243619504 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:11 PM PDT 24 174607182 ps
T859 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2845952879 Jun 07 08:04:36 PM PDT 24 Jun 07 08:04:39 PM PDT 24 120899949 ps
T860 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4106574250 Jun 07 08:04:32 PM PDT 24 Jun 07 08:04:34 PM PDT 24 180388881 ps
T861 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.230033935 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 347612553 ps
T862 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.449785273 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:11 PM PDT 24 569950991 ps
T863 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.990497223 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 556808910 ps
T864 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3139982251 Jun 07 08:04:11 PM PDT 24 Jun 07 08:04:15 PM PDT 24 131566664 ps
T865 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3254426477 Jun 07 08:04:35 PM PDT 24 Jun 07 08:04:38 PM PDT 24 481405737 ps
T866 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.346827369 Jun 07 08:04:31 PM PDT 24 Jun 07 08:04:33 PM PDT 24 218331615 ps
T867 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908756898 Jun 07 08:04:37 PM PDT 24 Jun 07 08:04:39 PM PDT 24 95909863 ps
T868 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3023400153 Jun 07 08:04:23 PM PDT 24 Jun 07 08:04:26 PM PDT 24 78508347 ps
T869 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3171414545 Jun 07 08:04:32 PM PDT 24 Jun 07 08:04:34 PM PDT 24 39700603 ps
T870 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1190398631 Jun 07 08:04:31 PM PDT 24 Jun 07 08:04:33 PM PDT 24 357431394 ps
T871 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1541160855 Jun 07 08:04:25 PM PDT 24 Jun 07 08:04:27 PM PDT 24 36248832 ps
T872 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4223813002 Jun 07 08:04:37 PM PDT 24 Jun 07 08:04:41 PM PDT 24 121672112 ps
T873 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.41782152 Jun 07 08:04:33 PM PDT 24 Jun 07 08:04:35 PM PDT 24 97542230 ps
T874 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2218394515 Jun 07 08:04:29 PM PDT 24 Jun 07 08:04:32 PM PDT 24 45281933 ps
T875 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1239996696 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 180905478 ps
T876 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4294890828 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 44324842 ps
T877 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3855753845 Jun 07 08:04:29 PM PDT 24 Jun 07 08:04:32 PM PDT 24 73580956 ps
T878 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2931775996 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:42 PM PDT 24 327044768 ps
T879 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.989249993 Jun 07 08:04:33 PM PDT 24 Jun 07 08:04:36 PM PDT 24 225351076 ps
T880 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1185802833 Jun 07 08:04:11 PM PDT 24 Jun 07 08:04:13 PM PDT 24 19163410 ps
T881 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4261630538 Jun 07 08:04:32 PM PDT 24 Jun 07 08:04:34 PM PDT 24 154444373 ps
T882 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4222346505 Jun 07 08:03:52 PM PDT 24 Jun 07 08:03:55 PM PDT 24 967005252 ps
T883 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.618164 Jun 07 08:04:33 PM PDT 24 Jun 07 08:04:35 PM PDT 24 438375602 ps
T884 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1305436972 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 73762179 ps
T885 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3491376350 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:41 PM PDT 24 56515356 ps
T886 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1170168571 Jun 07 08:04:23 PM PDT 24 Jun 07 08:04:26 PM PDT 24 379247878 ps
T887 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1994660985 Jun 07 08:04:37 PM PDT 24 Jun 07 08:04:40 PM PDT 24 74955834 ps
T888 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4149484384 Jun 07 08:04:30 PM PDT 24 Jun 07 08:04:33 PM PDT 24 77040515 ps
T889 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2882655399 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 937035020 ps
T890 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2155655686 Jun 07 08:04:32 PM PDT 24 Jun 07 08:04:34 PM PDT 24 55452795 ps
T891 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.378435379 Jun 07 08:04:29 PM PDT 24 Jun 07 08:04:31 PM PDT 24 35056938 ps
T892 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2541337225 Jun 07 08:04:30 PM PDT 24 Jun 07 08:04:33 PM PDT 24 105482944 ps
T893 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1681718819 Jun 07 08:04:08 PM PDT 24 Jun 07 08:04:09 PM PDT 24 30617494 ps
T894 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3859463381 Jun 07 08:04:40 PM PDT 24 Jun 07 08:04:46 PM PDT 24 43413476 ps
T895 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1577528910 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:11 PM PDT 24 79279180 ps
T896 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3183706369 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:42 PM PDT 24 180151594 ps
T897 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1517487387 Jun 07 08:04:25 PM PDT 24 Jun 07 08:04:28 PM PDT 24 37026562 ps
T898 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2855022986 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 174129521 ps
T899 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138905743 Jun 07 08:04:12 PM PDT 24 Jun 07 08:04:14 PM PDT 24 32403106 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710777063 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 50854048 ps
T901 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525499376 Jun 07 08:04:39 PM PDT 24 Jun 07 08:04:43 PM PDT 24 508733227 ps
T902 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2013291620 Jun 07 08:04:40 PM PDT 24 Jun 07 08:04:45 PM PDT 24 75382316 ps
T903 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4058956323 Jun 07 08:04:29 PM PDT 24 Jun 07 08:04:31 PM PDT 24 19936398 ps
T904 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1549779114 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:14 PM PDT 24 49999295 ps
T905 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3635608478 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 172519794 ps
T906 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.352231152 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 42457903 ps
T907 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1796662183 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 63547164 ps
T908 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1096836704 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:14 PM PDT 24 219381609 ps
T909 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2110710498 Jun 07 08:04:27 PM PDT 24 Jun 07 08:04:30 PM PDT 24 288647072 ps
T910 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.888838073 Jun 07 08:04:24 PM PDT 24 Jun 07 08:04:27 PM PDT 24 38173599 ps
T911 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.698770644 Jun 07 08:04:24 PM PDT 24 Jun 07 08:04:27 PM PDT 24 205968538 ps
T912 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.493322909 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 380270803 ps
T913 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1615472733 Jun 07 08:04:41 PM PDT 24 Jun 07 08:04:46 PM PDT 24 400824843 ps
T914 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193235235 Jun 07 08:04:12 PM PDT 24 Jun 07 08:04:15 PM PDT 24 45150388 ps
T915 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1111346747 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 110698442 ps
T916 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.408008571 Jun 07 08:04:24 PM PDT 24 Jun 07 08:04:27 PM PDT 24 34870724 ps
T917 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1347511571 Jun 07 08:04:31 PM PDT 24 Jun 07 08:04:33 PM PDT 24 27229189 ps
T918 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1607908029 Jun 07 08:04:40 PM PDT 24 Jun 07 08:04:44 PM PDT 24 37970137 ps
T919 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.447120589 Jun 07 08:04:39 PM PDT 24 Jun 07 08:04:43 PM PDT 24 363117463 ps
T920 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1765479618 Jun 07 08:04:39 PM PDT 24 Jun 07 08:04:43 PM PDT 24 52243673 ps
T921 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4000722384 Jun 07 08:04:30 PM PDT 24 Jun 07 08:04:32 PM PDT 24 54075220 ps
T922 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482618870 Jun 07 08:04:08 PM PDT 24 Jun 07 08:04:10 PM PDT 24 150364707 ps
T923 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1751407298 Jun 07 08:04:35 PM PDT 24 Jun 07 08:04:37 PM PDT 24 114206898 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.733416323 Jun 07 08:04:34 PM PDT 24 Jun 07 08:04:37 PM PDT 24 27349087 ps
T925 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3288578580 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:11 PM PDT 24 109572088 ps
T926 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525780809 Jun 07 08:04:35 PM PDT 24 Jun 07 08:04:37 PM PDT 24 43933645 ps
T927 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.712565199 Jun 07 08:04:08 PM PDT 24 Jun 07 08:04:10 PM PDT 24 70764382 ps
T928 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3441386983 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:42 PM PDT 24 308495353 ps
T929 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2979052087 Jun 07 08:04:40 PM PDT 24 Jun 07 08:04:45 PM PDT 24 443973748 ps
T930 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1735394719 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:13 PM PDT 24 127746750 ps
T931 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.908813147 Jun 07 08:04:40 PM PDT 24 Jun 07 08:04:46 PM PDT 24 71349542 ps
T932 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3839130936 Jun 07 08:04:23 PM PDT 24 Jun 07 08:04:26 PM PDT 24 95365718 ps
T933 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2717947152 Jun 07 08:04:28 PM PDT 24 Jun 07 08:04:31 PM PDT 24 139412003 ps
T934 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2201360293 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:12 PM PDT 24 162890225 ps
T935 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861542593 Jun 07 08:04:27 PM PDT 24 Jun 07 08:04:29 PM PDT 24 212644134 ps
T936 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1116576496 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 151394743 ps
T937 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1331574937 Jun 07 08:04:11 PM PDT 24 Jun 07 08:04:14 PM PDT 24 208400339 ps
T938 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594702848 Jun 07 08:04:39 PM PDT 24 Jun 07 08:04:43 PM PDT 24 186279352 ps
T939 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4002783946 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:11 PM PDT 24 35145132 ps
T940 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1902640153 Jun 07 08:04:11 PM PDT 24 Jun 07 08:04:14 PM PDT 24 176653923 ps
T941 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3161112383 Jun 07 08:04:37 PM PDT 24 Jun 07 08:04:41 PM PDT 24 168606523 ps
T942 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.543642644 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:42 PM PDT 24 376429176 ps
T943 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2263666121 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:41 PM PDT 24 60753496 ps
T944 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3509419362 Jun 07 08:04:38 PM PDT 24 Jun 07 08:04:41 PM PDT 24 23579910 ps
T945 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.691471046 Jun 07 08:04:09 PM PDT 24 Jun 07 08:04:11 PM PDT 24 96898522 ps
T946 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4046049021 Jun 07 08:04:37 PM PDT 24 Jun 07 08:04:41 PM PDT 24 113898054 ps
T947 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3390945734 Jun 07 08:04:10 PM PDT 24 Jun 07 08:04:13 PM PDT 24 215855581 ps
T948 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3885114399 Jun 07 08:04:29 PM PDT 24 Jun 07 08:04:32 PM PDT 24 109783954 ps

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3574986556
Short name T1
Test name
Test status
Simulation time 319926268 ps
CPU time 4.33 seconds
Started Jun 07 07:38:07 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 198012 kb
Host smart-4219f724-1b0b-41c2-a9f6-a90c9208ee7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574986556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3574986556
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2198088675
Short name T67
Test name
Test status
Simulation time 34316560 ps
CPU time 1.58 seconds
Started Jun 07 07:38:27 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 197980 kb
Host smart-066409f9-a8d0-4233-805c-87f64ff3bcf7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198088675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2198088675
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3651101725
Short name T26
Test name
Test status
Simulation time 68540598342 ps
CPU time 1936.91 seconds
Started Jun 07 07:36:22 PM PDT 24
Finished Jun 07 08:08:41 PM PDT 24
Peak memory 198260 kb
Host smart-ef8f7123-5536-4b34-b0b7-2aa2fcb76023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3651101725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3651101725
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1952296538
Short name T32
Test name
Test status
Simulation time 39770973 ps
CPU time 0.83 seconds
Started Jun 07 07:35:42 PM PDT 24
Finished Jun 07 07:35:45 PM PDT 24
Peak memory 213804 kb
Host smart-d7c70ed4-8fa5-4186-8eda-aabb162d83ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952296538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1952296538
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.828437819
Short name T82
Test name
Test status
Simulation time 34152266 ps
CPU time 0.59 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:39 PM PDT 24
Peak memory 194444 kb
Host smart-85485947-0cf4-4120-95ad-830df5810fca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828437819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.828437819
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2599435185
Short name T31
Test name
Test status
Simulation time 445330953 ps
CPU time 1.56 seconds
Started Jun 07 07:32:48 PM PDT 24
Finished Jun 07 07:32:51 PM PDT 24
Peak memory 198016 kb
Host smart-e9e3e488-4d84-46b9-ad99-0ac8c6ccdf48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599435185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2599435185
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1954799357
Short name T170
Test name
Test status
Simulation time 43522362 ps
CPU time 0.57 seconds
Started Jun 07 07:35:25 PM PDT 24
Finished Jun 07 07:35:27 PM PDT 24
Peak memory 194636 kb
Host smart-ce250555-8d7c-4a60-bd87-9e0695b14fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954799357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1954799357
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2943888104
Short name T102
Test name
Test status
Simulation time 21679924 ps
CPU time 0.71 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 194872 kb
Host smart-10641c14-9870-4c85-ae69-783a67da4742
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943888104 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2943888104
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1477620847
Short name T842
Test name
Test status
Simulation time 432472026 ps
CPU time 1.51 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 198008 kb
Host smart-f97cb50e-bf64-4695-bd48-89ecc37215e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477620847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1477620847
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.304349995
Short name T96
Test name
Test status
Simulation time 16921977 ps
CPU time 0.84 seconds
Started Jun 07 07:32:16 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 196452 kb
Host smart-43d00b93-c102-4022-a20c-2cc95f5921c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304349995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.304349995
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.394569383
Short name T742
Test name
Test status
Simulation time 35562196 ps
CPU time 1.39 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 197908 kb
Host smart-66685b6c-27c9-4630-94e6-aae041ed4656
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394569383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.394569383
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4266283583
Short name T111
Test name
Test status
Simulation time 36121627 ps
CPU time 0.68 seconds
Started Jun 07 07:32:16 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 194820 kb
Host smart-8e892737-e1ee-4e6a-a3c1-718b0203dbfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266283583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4266283583
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.203052913
Short name T735
Test name
Test status
Simulation time 19319892 ps
CPU time 0.75 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 196844 kb
Host smart-74330950-3dd6-4f93-8886-aa230f78d223
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203052913 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.203052913
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1453838383
Short name T833
Test name
Test status
Simulation time 25211329 ps
CPU time 0.63 seconds
Started Jun 07 07:32:16 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 194904 kb
Host smart-98a3d87f-6145-481f-be3e-b0a3985e50e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453838383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1453838383
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3262333574
Short name T816
Test name
Test status
Simulation time 19454905 ps
CPU time 0.6 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 193648 kb
Host smart-53e15307-72c7-485c-bc51-bb1756e12401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262333574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3262333574
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2296507681
Short name T767
Test name
Test status
Simulation time 135261451 ps
CPU time 2.99 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:31 PM PDT 24
Peak memory 197996 kb
Host smart-3c60fcba-4e95-4037-b93a-134db7c44108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296507681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2296507681
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.262234208
Short name T40
Test name
Test status
Simulation time 310288818 ps
CPU time 1.11 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 197968 kb
Host smart-fa8b1369-8c16-48df-88cb-3678acb6de68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262234208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.262234208
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4015139874
Short name T79
Test name
Test status
Simulation time 84018209 ps
CPU time 0.77 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 196708 kb
Host smart-84727918-4628-4082-987f-02bbb03034d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015139874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4015139874
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3140282923
Short name T94
Test name
Test status
Simulation time 1051791404 ps
CPU time 2.39 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:31 PM PDT 24
Peak memory 196916 kb
Host smart-a48eb297-8290-4f82-b5df-45e7c927c2cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140282923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3140282923
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2030939551
Short name T821
Test name
Test status
Simulation time 15464283 ps
CPU time 0.6 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 194676 kb
Host smart-ee25ca2e-6a17-44c2-ba40-b96282eecc91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030939551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2030939551
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4145669754
Short name T830
Test name
Test status
Simulation time 66788619 ps
CPU time 0.8 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 197952 kb
Host smart-3f53a7df-5b24-4450-b872-a576a8f2d195
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145669754 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4145669754
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1508294938
Short name T81
Test name
Test status
Simulation time 22449566 ps
CPU time 0.56 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 194456 kb
Host smart-4c113eb5-027f-447d-a4c4-0bde76bcd4f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508294938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1508294938
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2936860200
Short name T772
Test name
Test status
Simulation time 82517714 ps
CPU time 0.59 seconds
Started Jun 07 07:32:31 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 193636 kb
Host smart-291518ef-eff6-4496-8fe9-59d298caf0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936860200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2936860200
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2882104874
Short name T793
Test name
Test status
Simulation time 25145884 ps
CPU time 0.67 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 195464 kb
Host smart-d7397990-b9cf-4987-a92d-86419b54e504
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882104874 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2882104874
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1341735914
Short name T728
Test name
Test status
Simulation time 91909852 ps
CPU time 1.81 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 197976 kb
Host smart-10224aa2-681e-456c-96f1-58b860c6addf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341735914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1341735914
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.8368118
Short name T42
Test name
Test status
Simulation time 422743583 ps
CPU time 1.34 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 197768 kb
Host smart-6c31358e-6bb8-4861-9104-657cc45f4f82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8368118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_tl_intg_err.8368118
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2837776
Short name T794
Test name
Test status
Simulation time 241846731 ps
CPU time 0.86 seconds
Started Jun 07 07:32:37 PM PDT 24
Finished Jun 07 07:32:43 PM PDT 24
Peak memory 197916 kb
Host smart-921887f9-30d8-4453-962c-eacc2aff661b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837776 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2837776
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.91590593
Short name T804
Test name
Test status
Simulation time 37148778 ps
CPU time 0.6 seconds
Started Jun 07 07:32:35 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 193924 kb
Host smart-12b31c99-6551-442d-8986-d94ce0a00f1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91590593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_
csr_rw.91590593
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3511669131
Short name T747
Test name
Test status
Simulation time 23994507 ps
CPU time 0.62 seconds
Started Jun 07 07:32:39 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 193676 kb
Host smart-acc68afb-1efe-4cce-86c9-251fbcecbc2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511669131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3511669131
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3209778701
Short name T85
Test name
Test status
Simulation time 125704572 ps
CPU time 0.77 seconds
Started Jun 07 07:32:37 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 196308 kb
Host smart-03499113-a26f-4ff4-b9a9-04e8128d07c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209778701 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3209778701
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2062420517
Short name T843
Test name
Test status
Simulation time 51738757 ps
CPU time 2.56 seconds
Started Jun 07 07:32:40 PM PDT 24
Finished Jun 07 07:32:47 PM PDT 24
Peak memory 198008 kb
Host smart-a09c5d6f-7818-4668-8c31-1ed7aaac72a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062420517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2062420517
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1419383925
Short name T768
Test name
Test status
Simulation time 235302218 ps
CPU time 0.94 seconds
Started Jun 07 07:32:39 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 197128 kb
Host smart-71fabc11-a050-4287-86f6-58f2b2555b59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419383925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1419383925
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2819891948
Short name T799
Test name
Test status
Simulation time 75862597 ps
CPU time 1.08 seconds
Started Jun 07 07:32:41 PM PDT 24
Finished Jun 07 07:32:46 PM PDT 24
Peak memory 197964 kb
Host smart-d7b6e551-80ea-4681-91ba-1991d1f84bdf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819891948 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2819891948
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3187895044
Short name T786
Test name
Test status
Simulation time 44718819 ps
CPU time 0.6 seconds
Started Jun 07 07:32:37 PM PDT 24
Finished Jun 07 07:32:43 PM PDT 24
Peak memory 195284 kb
Host smart-0e080bac-f934-41b0-b590-537237be9eff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187895044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3187895044
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1061266158
Short name T725
Test name
Test status
Simulation time 65397696 ps
CPU time 0.56 seconds
Started Jun 07 07:32:39 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 193640 kb
Host smart-dcbf2d98-9531-4a08-be20-3fc75c41c2c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061266158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1061266158
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1416820724
Short name T835
Test name
Test status
Simulation time 49517980 ps
CPU time 0.68 seconds
Started Jun 07 07:32:41 PM PDT 24
Finished Jun 07 07:32:46 PM PDT 24
Peak memory 195704 kb
Host smart-6016d4ab-cfd1-466a-a08a-6df0e0028466
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416820724 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1416820724
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.76625002
Short name T812
Test name
Test status
Simulation time 194003214 ps
CPU time 1.98 seconds
Started Jun 07 07:32:40 PM PDT 24
Finished Jun 07 07:32:47 PM PDT 24
Peak memory 197996 kb
Host smart-09a7cc45-864d-4b7d-9142-3b92c71650d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76625002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.76625002
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3215802421
Short name T753
Test name
Test status
Simulation time 61589995 ps
CPU time 0.85 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 197860 kb
Host smart-53e73327-5e69-43ef-a353-446116821bd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215802421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3215802421
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3155460257
Short name T813
Test name
Test status
Simulation time 28212562 ps
CPU time 1.23 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 198152 kb
Host smart-c6d2540e-16dd-452b-b7a4-9bb8d28141fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155460257 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3155460257
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4190023562
Short name T803
Test name
Test status
Simulation time 31326340 ps
CPU time 0.61 seconds
Started Jun 07 07:32:46 PM PDT 24
Finished Jun 07 07:32:49 PM PDT 24
Peak memory 195328 kb
Host smart-b1581b8c-d02c-4a41-83d3-d4ca0aa8f037
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190023562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4190023562
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.385814580
Short name T809
Test name
Test status
Simulation time 16563883 ps
CPU time 0.58 seconds
Started Jun 07 07:32:39 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 193460 kb
Host smart-815d749b-c705-41e5-957b-833b1310456c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385814580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.385814580
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2526960171
Short name T106
Test name
Test status
Simulation time 33948731 ps
CPU time 0.83 seconds
Started Jun 07 07:32:44 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 196384 kb
Host smart-0c61d731-52c5-4d98-975a-3699f1a3b993
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526960171 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2526960171
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2984527243
Short name T743
Test name
Test status
Simulation time 797945265 ps
CPU time 2.61 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:50 PM PDT 24
Peak memory 197984 kb
Host smart-420282c3-ca6a-4694-96d5-cbb631439c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984527243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2984527243
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2707281907
Short name T45
Test name
Test status
Simulation time 85452405 ps
CPU time 0.88 seconds
Started Jun 07 07:32:40 PM PDT 24
Finished Jun 07 07:32:46 PM PDT 24
Peak memory 196904 kb
Host smart-53a7dae1-c0e0-4e40-a8ec-4f68b2204ce5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707281907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2707281907
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4048535459
Short name T801
Test name
Test status
Simulation time 69690718 ps
CPU time 0.65 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 196976 kb
Host smart-2fc709a5-5bcf-487d-bd5a-4057938dab63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048535459 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4048535459
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.964974368
Short name T98
Test name
Test status
Simulation time 41331479 ps
CPU time 0.58 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 194440 kb
Host smart-e863a823-4f34-4eb8-8aea-49cdd386f608
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964974368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.964974368
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3869494221
Short name T750
Test name
Test status
Simulation time 11434760 ps
CPU time 0.59 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 193652 kb
Host smart-84b57a2e-4455-4d12-af3b-477dcd75dadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869494221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3869494221
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1962353899
Short name T765
Test name
Test status
Simulation time 107413873 ps
CPU time 0.6 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 194296 kb
Host smart-43306c2c-8979-411b-b2af-faf8379e25ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962353899 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1962353899
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.727940675
Short name T847
Test name
Test status
Simulation time 103067939 ps
CPU time 1.29 seconds
Started Jun 07 07:32:40 PM PDT 24
Finished Jun 07 07:32:46 PM PDT 24
Peak memory 198020 kb
Host smart-c217e400-79cb-4398-aa7f-23c6e57ee16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727940675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.727940675
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.385099182
Short name T749
Test name
Test status
Simulation time 90549775 ps
CPU time 1.2 seconds
Started Jun 07 07:32:41 PM PDT 24
Finished Jun 07 07:32:47 PM PDT 24
Peak memory 198032 kb
Host smart-21214a4c-5b0e-4276-ab91-92b74ffe63d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385099182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.385099182
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.171974867
Short name T790
Test name
Test status
Simulation time 106923000 ps
CPU time 1.43 seconds
Started Jun 07 07:32:41 PM PDT 24
Finished Jun 07 07:32:47 PM PDT 24
Peak memory 198100 kb
Host smart-2bda5d76-1071-4245-9461-158649ff3719
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171974867 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.171974867
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2609199516
Short name T110
Test name
Test status
Simulation time 37992974 ps
CPU time 0.61 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 194704 kb
Host smart-f9210bbf-8fe0-4773-9755-6b3303efda85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609199516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2609199516
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.290823237
Short name T802
Test name
Test status
Simulation time 23764953 ps
CPU time 0.6 seconds
Started Jun 07 07:32:41 PM PDT 24
Finished Jun 07 07:32:46 PM PDT 24
Peak memory 193692 kb
Host smart-e786f6ef-102d-4458-9008-1da7c83beca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290823237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.290823237
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2966746381
Short name T834
Test name
Test status
Simulation time 187471857 ps
CPU time 0.7 seconds
Started Jun 07 07:32:39 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 195228 kb
Host smart-7fd96044-cbe5-46fd-9ad2-f886ad0e79d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966746381 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2966746381
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2965927252
Short name T800
Test name
Test status
Simulation time 38814922 ps
CPU time 2.05 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:46 PM PDT 24
Peak memory 197980 kb
Host smart-45bc9f75-9142-42c1-a2df-a2de8f37b78a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965927252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2965927252
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3639341518
Short name T29
Test name
Test status
Simulation time 216560969 ps
CPU time 1.45 seconds
Started Jun 07 07:32:41 PM PDT 24
Finished Jun 07 07:32:47 PM PDT 24
Peak memory 198000 kb
Host smart-aade781d-cb1b-4bec-8ce3-ef46f30195bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639341518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3639341518
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.513243068
Short name T788
Test name
Test status
Simulation time 17851539 ps
CPU time 1.03 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 197972 kb
Host smart-45c538ee-4971-4b35-8f91-b56eca64f4ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513243068 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.513243068
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.48170537
Short name T759
Test name
Test status
Simulation time 14575162 ps
CPU time 0.58 seconds
Started Jun 07 07:32:47 PM PDT 24
Finished Jun 07 07:32:49 PM PDT 24
Peak memory 193296 kb
Host smart-7e4b9adf-41d5-440a-9169-eb67c5099e10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48170537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_
csr_rw.48170537
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2496992186
Short name T746
Test name
Test status
Simulation time 51999456 ps
CPU time 0.62 seconds
Started Jun 07 07:32:51 PM PDT 24
Finished Jun 07 07:32:53 PM PDT 24
Peak memory 193704 kb
Host smart-827890aa-3fde-439c-9dd7-398b1d25b3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496992186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2496992186
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.915638643
Short name T104
Test name
Test status
Simulation time 17371637 ps
CPU time 0.72 seconds
Started Jun 07 07:32:44 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 196164 kb
Host smart-680a8f49-61c3-4480-a243-ddabebdb7d1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915638643 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.915638643
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3186038830
Short name T818
Test name
Test status
Simulation time 329598009 ps
CPU time 1.81 seconds
Started Jun 07 07:32:42 PM PDT 24
Finished Jun 07 07:32:48 PM PDT 24
Peak memory 198024 kb
Host smart-07560979-9a6d-496d-b11d-66cf0cf56144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186038830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3186038830
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2495245615
Short name T41
Test name
Test status
Simulation time 1103280630 ps
CPU time 1.19 seconds
Started Jun 07 07:32:45 PM PDT 24
Finished Jun 07 07:32:49 PM PDT 24
Peak memory 197988 kb
Host smart-752c92d3-3860-4d8c-9fd9-b65b1fb99394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495245615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2495245615
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3537192686
Short name T778
Test name
Test status
Simulation time 58889706 ps
CPU time 0.84 seconds
Started Jun 07 07:32:51 PM PDT 24
Finished Jun 07 07:32:53 PM PDT 24
Peak memory 198028 kb
Host smart-b6e7a88f-d91f-4f15-a650-7b73490299d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537192686 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3537192686
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1680323098
Short name T841
Test name
Test status
Simulation time 44410006 ps
CPU time 0.63 seconds
Started Jun 07 07:32:49 PM PDT 24
Finished Jun 07 07:32:51 PM PDT 24
Peak memory 195060 kb
Host smart-16a5c3ab-8f16-496e-b16f-578c1c077c95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680323098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1680323098
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3947195583
Short name T846
Test name
Test status
Simulation time 40342030 ps
CPU time 0.6 seconds
Started Jun 07 07:32:51 PM PDT 24
Finished Jun 07 07:32:53 PM PDT 24
Peak memory 193636 kb
Host smart-84aa2f51-59c0-4a39-a21b-b6c4f672713d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947195583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3947195583
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.145850170
Short name T839
Test name
Test status
Simulation time 24196730 ps
CPU time 0.64 seconds
Started Jun 07 07:32:55 PM PDT 24
Finished Jun 07 07:32:57 PM PDT 24
Peak memory 195832 kb
Host smart-accb5aa2-f342-47f7-aaaf-c112670f686e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145850170 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.145850170
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2610784134
Short name T769
Test name
Test status
Simulation time 44416814 ps
CPU time 2.16 seconds
Started Jun 07 07:32:48 PM PDT 24
Finished Jun 07 07:32:52 PM PDT 24
Peak memory 198040 kb
Host smart-8ffa83bc-11b7-4afc-8152-415a6a92bf6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610784134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2610784134
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.340394458
Short name T739
Test name
Test status
Simulation time 99547865 ps
CPU time 0.73 seconds
Started Jun 07 07:32:52 PM PDT 24
Finished Jun 07 07:32:54 PM PDT 24
Peak memory 197968 kb
Host smart-6a3368e4-acc4-4b23-aa21-1b9049860588
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340394458 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.340394458
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.559316042
Short name T87
Test name
Test status
Simulation time 13300718 ps
CPU time 0.61 seconds
Started Jun 07 07:32:48 PM PDT 24
Finished Jun 07 07:32:50 PM PDT 24
Peak memory 194880 kb
Host smart-f4ba6f11-1a2e-46b2-b7ca-e54887a71ce3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559316042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.559316042
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.317979276
Short name T840
Test name
Test status
Simulation time 13676021 ps
CPU time 0.59 seconds
Started Jun 07 07:32:53 PM PDT 24
Finished Jun 07 07:32:54 PM PDT 24
Peak memory 194292 kb
Host smart-63edc155-2ccc-4e65-9bc4-aafdc32f1926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317979276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.317979276
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.620843039
Short name T807
Test name
Test status
Simulation time 43260648 ps
CPU time 0.89 seconds
Started Jun 07 07:32:53 PM PDT 24
Finished Jun 07 07:32:55 PM PDT 24
Peak memory 196384 kb
Host smart-dd27963a-0807-4057-b373-2b3aa0193439
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620843039 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.620843039
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2349580446
Short name T792
Test name
Test status
Simulation time 173274675 ps
CPU time 2.77 seconds
Started Jun 07 07:32:54 PM PDT 24
Finished Jun 07 07:32:58 PM PDT 24
Peak memory 197988 kb
Host smart-7be4af6f-ce31-45c1-a409-cfbe393deb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349580446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2349580446
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.722369691
Short name T825
Test name
Test status
Simulation time 293244560 ps
CPU time 1.43 seconds
Started Jun 07 07:32:55 PM PDT 24
Finished Jun 07 07:32:58 PM PDT 24
Peak memory 198028 kb
Host smart-1cb141a6-54a7-4d3f-9504-b3c249d604cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722369691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.722369691
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4225045081
Short name T757
Test name
Test status
Simulation time 213210578 ps
CPU time 1.06 seconds
Started Jun 07 07:32:48 PM PDT 24
Finished Jun 07 07:32:51 PM PDT 24
Peak memory 198004 kb
Host smart-be72383f-1440-46ee-a677-f5909d11ad87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225045081 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.4225045081
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1806170762
Short name T100
Test name
Test status
Simulation time 15595391 ps
CPU time 0.65 seconds
Started Jun 07 07:32:51 PM PDT 24
Finished Jun 07 07:32:53 PM PDT 24
Peak memory 194532 kb
Host smart-20b8bc95-5c76-4ba0-bde7-a188c74566b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806170762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1806170762
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2115908622
Short name T810
Test name
Test status
Simulation time 39671202 ps
CPU time 0.61 seconds
Started Jun 07 07:32:50 PM PDT 24
Finished Jun 07 07:32:52 PM PDT 24
Peak memory 193676 kb
Host smart-3012c740-f62a-4ba4-b34b-c0f2d1c21a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115908622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2115908622
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3338490837
Short name T105
Test name
Test status
Simulation time 20746868 ps
CPU time 0.68 seconds
Started Jun 07 07:32:51 PM PDT 24
Finished Jun 07 07:32:53 PM PDT 24
Peak memory 194896 kb
Host smart-8e18c048-73f2-464c-beb2-fe22f1bebc6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338490837 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3338490837
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.773052613
Short name T779
Test name
Test status
Simulation time 563933933 ps
CPU time 2.04 seconds
Started Jun 07 07:32:54 PM PDT 24
Finished Jun 07 07:32:57 PM PDT 24
Peak memory 197976 kb
Host smart-861809a0-5052-4503-996a-fb54a3eebe23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773052613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.773052613
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.995349412
Short name T838
Test name
Test status
Simulation time 343110465 ps
CPU time 1.06 seconds
Started Jun 07 07:32:53 PM PDT 24
Finished Jun 07 07:32:55 PM PDT 24
Peak memory 197992 kb
Host smart-08d020f7-6669-41b4-9314-194f2dd90827
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995349412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.995349412
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2225491901
Short name T773
Test name
Test status
Simulation time 160479021 ps
CPU time 1.04 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:10 PM PDT 24
Peak memory 197976 kb
Host smart-56aa711a-1ab7-44bb-9572-92d9eec1143a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225491901 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2225491901
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2113850271
Short name T828
Test name
Test status
Simulation time 36873476 ps
CPU time 0.55 seconds
Started Jun 07 07:32:54 PM PDT 24
Finished Jun 07 07:32:56 PM PDT 24
Peak memory 193340 kb
Host smart-aeba53c0-3eeb-44fa-9daf-e7c53e6b1cdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113850271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2113850271
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1750066703
Short name T791
Test name
Test status
Simulation time 23000228 ps
CPU time 0.62 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:05 PM PDT 24
Peak memory 193656 kb
Host smart-5adc8d4c-4b84-4f8a-9be4-55639e180eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750066703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1750066703
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2773298296
Short name T787
Test name
Test status
Simulation time 45561986 ps
CPU time 0.74 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:05 PM PDT 24
Peak memory 195868 kb
Host smart-36790175-d2e5-4a01-a3d3-10b67119e4b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773298296 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2773298296
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1355117420
Short name T774
Test name
Test status
Simulation time 97450899 ps
CPU time 1.42 seconds
Started Jun 07 07:33:04 PM PDT 24
Finished Jun 07 07:33:08 PM PDT 24
Peak memory 197960 kb
Host smart-398fd2ea-5037-4ad2-ac33-37b4fcb9eb67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355117420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1355117420
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2976383675
Short name T824
Test name
Test status
Simulation time 67590453 ps
CPU time 1.14 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:12 PM PDT 24
Peak memory 198024 kb
Host smart-c17ca7f0-14af-43b0-b29d-8e1cd291c7e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976383675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2976383675
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2760981705
Short name T90
Test name
Test status
Simulation time 60519302 ps
CPU time 0.71 seconds
Started Jun 07 07:32:23 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 195700 kb
Host smart-05606a1c-1adf-44b8-8dd3-90c945c60e08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760981705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2760981705
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2349808751
Short name T80
Test name
Test status
Simulation time 3595417765 ps
CPU time 3.35 seconds
Started Jun 07 07:32:23 PM PDT 24
Finished Jun 07 07:32:32 PM PDT 24
Peak memory 197936 kb
Host smart-50ae2e5d-c0e0-44c6-8d7f-da27c40c7fb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349808751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2349808751
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.250364769
Short name T797
Test name
Test status
Simulation time 81527987 ps
CPU time 0.6 seconds
Started Jun 07 07:32:36 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 194512 kb
Host smart-7c7e1a10-a62a-4530-9f07-ae9880569fa3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250364769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.250364769
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1511073338
Short name T844
Test name
Test status
Simulation time 96648957 ps
CPU time 0.83 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 198008 kb
Host smart-3a115511-63d7-488b-9c41-4e1adb47cba8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511073338 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1511073338
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.704153852
Short name T89
Test name
Test status
Simulation time 47512025 ps
CPU time 0.62 seconds
Started Jun 07 07:32:23 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 194772 kb
Host smart-818d17f4-e696-4d7e-b92a-bcc884362324
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704153852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.704153852
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3549244805
Short name T805
Test name
Test status
Simulation time 19566296 ps
CPU time 0.58 seconds
Started Jun 07 07:32:36 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 194296 kb
Host smart-121e0869-fe3c-415b-9ec6-14ae08071b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549244805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3549244805
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4171780142
Short name T84
Test name
Test status
Simulation time 22472276 ps
CPU time 0.67 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 195036 kb
Host smart-68f9b924-2af3-49da-a552-414e423f3284
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171780142 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4171780142
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1913763424
Short name T727
Test name
Test status
Simulation time 520483467 ps
CPU time 1.57 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 197980 kb
Host smart-dd2d6971-dc7f-484b-a052-93b21d6a7fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913763424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1913763424
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2616418914
Short name T30
Test name
Test status
Simulation time 45732840 ps
CPU time 0.86 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 197220 kb
Host smart-a00b018a-b9cb-4c7f-806b-779df0d44d80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616418914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2616418914
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3430149261
Short name T744
Test name
Test status
Simulation time 16418311 ps
CPU time 0.62 seconds
Started Jun 07 07:33:08 PM PDT 24
Finished Jun 07 07:33:14 PM PDT 24
Peak memory 194344 kb
Host smart-55759d14-d93f-488a-aef6-c0111bc352c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430149261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3430149261
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1456642105
Short name T738
Test name
Test status
Simulation time 159033402 ps
CPU time 0.6 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 193656 kb
Host smart-04b025b2-fdfd-4c42-9083-955a52575a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456642105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1456642105
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.646972213
Short name T789
Test name
Test status
Simulation time 42424828 ps
CPU time 0.56 seconds
Started Jun 07 07:33:05 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 193608 kb
Host smart-7080f510-8e12-4296-94e3-32ee93c7ae49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646972213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.646972213
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.68197637
Short name T734
Test name
Test status
Simulation time 48977988 ps
CPU time 0.66 seconds
Started Jun 07 07:33:04 PM PDT 24
Finished Jun 07 07:33:07 PM PDT 24
Peak memory 193736 kb
Host smart-bc00d600-6fac-4706-945c-53e855f5afa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68197637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.68197637
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1569800967
Short name T845
Test name
Test status
Simulation time 17933083 ps
CPU time 0.6 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:05 PM PDT 24
Peak memory 193732 kb
Host smart-369a89bf-23ae-4c64-bf1f-920f13c6d1ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569800967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1569800967
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.273309465
Short name T777
Test name
Test status
Simulation time 42561354 ps
CPU time 0.58 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:06 PM PDT 24
Peak memory 194264 kb
Host smart-3882d69b-04b0-48ec-9fb8-d43ada49f267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273309465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.273309465
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2366534590
Short name T729
Test name
Test status
Simulation time 19486571 ps
CPU time 0.66 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:05 PM PDT 24
Peak memory 193708 kb
Host smart-8372efed-5799-4f63-b2e5-a74703ff5df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366534590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2366534590
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1061643056
Short name T795
Test name
Test status
Simulation time 37654680 ps
CPU time 0.66 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:06 PM PDT 24
Peak memory 193688 kb
Host smart-5bc62c49-0edc-4669-8c1c-96a12dd76e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061643056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1061643056
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.247492497
Short name T826
Test name
Test status
Simulation time 40514063 ps
CPU time 0.57 seconds
Started Jun 07 07:33:05 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 193608 kb
Host smart-462b5bdf-ebca-4540-9567-af7ceabac846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247492497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.247492497
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2456548845
Short name T741
Test name
Test status
Simulation time 16197568 ps
CPU time 0.62 seconds
Started Jun 07 07:33:04 PM PDT 24
Finished Jun 07 07:33:08 PM PDT 24
Peak memory 193652 kb
Host smart-872241da-0a93-4413-a461-7403dbdb1df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456548845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2456548845
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.713924141
Short name T814
Test name
Test status
Simulation time 14928778 ps
CPU time 0.67 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 195412 kb
Host smart-89ec38b3-2f05-4325-930f-2c67e3606da6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713924141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.713924141
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3666916287
Short name T97
Test name
Test status
Simulation time 34677043 ps
CPU time 1.43 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 197948 kb
Host smart-f97ec4b9-b5c2-4cc6-bfde-efc3cf8a7260
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666916287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3666916287
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2185206112
Short name T93
Test name
Test status
Simulation time 14939185 ps
CPU time 0.62 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 194708 kb
Host smart-d3d09f0e-9d46-431c-898d-fa2dca59d817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185206112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2185206112
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.885543294
Short name T811
Test name
Test status
Simulation time 188881353 ps
CPU time 1.09 seconds
Started Jun 07 07:32:24 PM PDT 24
Finished Jun 07 07:32:32 PM PDT 24
Peak memory 197972 kb
Host smart-510c854c-122e-40c4-8ba6-c63be0367beb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885543294 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.885543294
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1803831263
Short name T775
Test name
Test status
Simulation time 45328691 ps
CPU time 0.61 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 194976 kb
Host smart-1a60b33b-63b7-45c2-ba43-dc32ad7b8b5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803831263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1803831263
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1140354661
Short name T848
Test name
Test status
Simulation time 56416948 ps
CPU time 0.64 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 193652 kb
Host smart-959fd02d-22fe-458a-84c8-4ac4789d33ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140354661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1140354661
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3973910737
Short name T103
Test name
Test status
Simulation time 14024238 ps
CPU time 0.61 seconds
Started Jun 07 07:32:38 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 194952 kb
Host smart-f8297690-aa81-4421-9ea7-dc76d5c9f607
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973910737 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3973910737
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.595998179
Short name T776
Test name
Test status
Simulation time 184317231 ps
CPU time 1.89 seconds
Started Jun 07 07:32:23 PM PDT 24
Finished Jun 07 07:32:32 PM PDT 24
Peak memory 197976 kb
Host smart-d6acd626-4235-405c-9b8f-fdb32e74e5af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595998179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.595998179
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2565147752
Short name T43
Test name
Test status
Simulation time 184922434 ps
CPU time 1.34 seconds
Started Jun 07 07:32:26 PM PDT 24
Finished Jun 07 07:32:34 PM PDT 24
Peak memory 197892 kb
Host smart-acaab741-c0db-4706-9432-4143eeed2b87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565147752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2565147752
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.45481595
Short name T823
Test name
Test status
Simulation time 90627127 ps
CPU time 0.59 seconds
Started Jun 07 07:33:05 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 193740 kb
Host smart-005c6c1c-8f52-4822-ab94-531c6127b2f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45481595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.45481595
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2626177625
Short name T831
Test name
Test status
Simulation time 21779021 ps
CPU time 0.58 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:11 PM PDT 24
Peak memory 194320 kb
Host smart-4dcfc825-16de-42ad-b6d2-0a64ce2dd71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626177625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2626177625
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.180390536
Short name T761
Test name
Test status
Simulation time 47153792 ps
CPU time 0.63 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:11 PM PDT 24
Peak memory 193604 kb
Host smart-72d62a99-70d1-49d0-979a-19935f08e252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180390536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.180390536
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3092891740
Short name T832
Test name
Test status
Simulation time 13614022 ps
CPU time 0.67 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:05 PM PDT 24
Peak memory 194300 kb
Host smart-cb34991c-02c5-4a34-9eab-8a98463778c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092891740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3092891740
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1223225310
Short name T737
Test name
Test status
Simulation time 22508167 ps
CPU time 0.59 seconds
Started Jun 07 07:33:05 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 194320 kb
Host smart-fa6d731a-a884-4e11-ac59-21c0f7c182ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223225310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1223225310
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3462383597
Short name T730
Test name
Test status
Simulation time 22830704 ps
CPU time 0.61 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:10 PM PDT 24
Peak memory 193688 kb
Host smart-db531406-c37c-4eb9-b155-937aec32fd0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462383597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3462383597
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3061502700
Short name T754
Test name
Test status
Simulation time 12436453 ps
CPU time 0.56 seconds
Started Jun 07 07:33:04 PM PDT 24
Finished Jun 07 07:33:08 PM PDT 24
Peak memory 193572 kb
Host smart-afcab2a1-eb44-45b2-a415-a08b1126bcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061502700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3061502700
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3347859580
Short name T798
Test name
Test status
Simulation time 48622499 ps
CPU time 0.65 seconds
Started Jun 07 07:33:08 PM PDT 24
Finished Jun 07 07:33:13 PM PDT 24
Peak memory 193644 kb
Host smart-859d8f26-c612-468b-83fe-dd3b5d85dee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347859580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3347859580
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1106196196
Short name T770
Test name
Test status
Simulation time 54416742 ps
CPU time 0.61 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:12 PM PDT 24
Peak memory 193660 kb
Host smart-d0711bec-da19-43ea-bebf-ba5451f4605b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106196196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1106196196
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.657248730
Short name T740
Test name
Test status
Simulation time 130747278 ps
CPU time 0.6 seconds
Started Jun 07 07:33:04 PM PDT 24
Finished Jun 07 07:33:08 PM PDT 24
Peak memory 193664 kb
Host smart-ea4c9ec5-d684-4a58-b0e1-ee5868912fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657248730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.657248730
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1012649224
Short name T732
Test name
Test status
Simulation time 53777635 ps
CPU time 0.62 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 194384 kb
Host smart-9228f324-5104-414f-b509-d60e06fd510c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012649224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1012649224
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4020920426
Short name T95
Test name
Test status
Simulation time 1433092557 ps
CPU time 3.24 seconds
Started Jun 07 07:32:30 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 196700 kb
Host smart-e5b813df-7f45-4787-bc61-57d669edfc1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020920426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4020920426
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1901079376
Short name T755
Test name
Test status
Simulation time 41579840 ps
CPU time 0.61 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 194672 kb
Host smart-7b888661-7924-45a6-9b22-99769246a3fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901079376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1901079376
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3331507376
Short name T782
Test name
Test status
Simulation time 20775032 ps
CPU time 0.77 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 198000 kb
Host smart-dd02ebde-7680-4d3d-bcbe-e2ca2ae3d3d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331507376 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3331507376
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2597065423
Short name T92
Test name
Test status
Simulation time 38176673 ps
CPU time 0.59 seconds
Started Jun 07 07:32:24 PM PDT 24
Finished Jun 07 07:32:31 PM PDT 24
Peak memory 194724 kb
Host smart-7caaf54e-64bc-4d0f-947b-ec0bb0a19507
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597065423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2597065423
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1727605724
Short name T766
Test name
Test status
Simulation time 12225145 ps
CPU time 0.62 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 194376 kb
Host smart-d8c0c121-37bd-4dbb-b7ba-a3abd4cb95ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727605724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1727605724
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.240192777
Short name T763
Test name
Test status
Simulation time 15872864 ps
CPU time 0.72 seconds
Started Jun 07 07:32:36 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 195896 kb
Host smart-375a1b76-af88-4f8a-bca4-d3075dbcc36c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240192777 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.240192777
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1798200090
Short name T760
Test name
Test status
Simulation time 53336179 ps
CPU time 1.36 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 197992 kb
Host smart-89f046ac-f28e-4a1b-83a2-4d21921e20d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798200090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1798200090
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2908066102
Short name T38
Test name
Test status
Simulation time 137077372 ps
CPU time 1.22 seconds
Started Jun 07 07:32:31 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 198032 kb
Host smart-ae8b28c2-d47e-417d-99fd-e8b0f2d51943
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908066102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2908066102
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1566332119
Short name T780
Test name
Test status
Simulation time 43503284 ps
CPU time 0.58 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:06 PM PDT 24
Peak memory 193636 kb
Host smart-a6fa5e7e-e13b-4e92-9ece-311d27e966e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566332119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1566332119
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.883756040
Short name T836
Test name
Test status
Simulation time 14061433 ps
CPU time 0.57 seconds
Started Jun 07 07:33:05 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 193624 kb
Host smart-013b7729-7b77-426d-9afe-331755278fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883756040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.883756040
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.888562156
Short name T820
Test name
Test status
Simulation time 21558354 ps
CPU time 0.59 seconds
Started Jun 07 07:33:13 PM PDT 24
Finished Jun 07 07:33:19 PM PDT 24
Peak memory 193656 kb
Host smart-d13534bb-a82f-44ba-841a-a94c0833fb93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888562156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.888562156
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2676642682
Short name T758
Test name
Test status
Simulation time 13855851 ps
CPU time 0.59 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:11 PM PDT 24
Peak memory 194268 kb
Host smart-858c9297-1646-4b1c-b15e-e1f148c86930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676642682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2676642682
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1925395307
Short name T751
Test name
Test status
Simulation time 24356248 ps
CPU time 0.59 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:11 PM PDT 24
Peak memory 193636 kb
Host smart-b95c832e-cb05-4b32-ab38-4b1aec7a659e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925395307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1925395307
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1860340611
Short name T808
Test name
Test status
Simulation time 170764017 ps
CPU time 0.68 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:06 PM PDT 24
Peak memory 193712 kb
Host smart-e20fea47-976b-4e45-a756-6b381dfa50e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860340611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1860340611
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1757256307
Short name T819
Test name
Test status
Simulation time 49632610 ps
CPU time 0.58 seconds
Started Jun 07 07:33:05 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 193612 kb
Host smart-9c647ba5-3c8f-4033-ae18-5d8b6afd2483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757256307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1757256307
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1992739806
Short name T817
Test name
Test status
Simulation time 17046860 ps
CPU time 0.63 seconds
Started Jun 07 07:33:03 PM PDT 24
Finished Jun 07 07:33:06 PM PDT 24
Peak memory 193772 kb
Host smart-0630b7be-4d5d-4ffb-8d71-c9dab0eb16a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992739806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1992739806
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3420317053
Short name T806
Test name
Test status
Simulation time 18699811 ps
CPU time 0.62 seconds
Started Jun 07 07:33:04 PM PDT 24
Finished Jun 07 07:33:07 PM PDT 24
Peak memory 193752 kb
Host smart-028fbead-4dd7-445f-9836-64fc37190f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420317053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3420317053
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2885335665
Short name T762
Test name
Test status
Simulation time 16002227 ps
CPU time 0.65 seconds
Started Jun 07 07:33:09 PM PDT 24
Finished Jun 07 07:33:15 PM PDT 24
Peak memory 193700 kb
Host smart-38c56aa6-4d92-439b-b46f-6783a5dc9c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885335665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2885335665
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1304336118
Short name T822
Test name
Test status
Simulation time 28776296 ps
CPU time 0.85 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 198004 kb
Host smart-36f9c78e-c8f4-4287-ad05-617322d6e082
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304336118 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1304336118
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.384523335
Short name T88
Test name
Test status
Simulation time 29849334 ps
CPU time 0.63 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 195072 kb
Host smart-56b5f610-53c0-47fc-b6ab-aa24d3f6eeaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384523335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.384523335
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4027749297
Short name T756
Test name
Test status
Simulation time 26946322 ps
CPU time 0.57 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:39 PM PDT 24
Peak memory 193632 kb
Host smart-fc17708c-473f-47f9-8c36-29b477dff08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027749297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4027749297
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1953313022
Short name T815
Test name
Test status
Simulation time 22763154 ps
CPU time 0.67 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 194580 kb
Host smart-53f5dee3-160c-4e56-a1f7-cabccf1fd4b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953313022 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1953313022
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1015222041
Short name T736
Test name
Test status
Simulation time 35734864 ps
CPU time 1.63 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 197900 kb
Host smart-b314f54c-944f-4713-9dd7-0e204c5ab7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015222041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1015222041
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3745233728
Short name T764
Test name
Test status
Simulation time 79925336 ps
CPU time 1.18 seconds
Started Jun 07 07:32:31 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 197856 kb
Host smart-2d9a9792-eec9-483e-adf5-45cd9c2fe2fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745233728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3745233728
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3407058195
Short name T785
Test name
Test status
Simulation time 234320201 ps
CPU time 0.74 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 197964 kb
Host smart-be4e3d97-2974-4e13-9c17-deaf724bc0be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407058195 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3407058195
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.196039195
Short name T99
Test name
Test status
Simulation time 14278130 ps
CPU time 0.58 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 194528 kb
Host smart-5241abf3-3017-40e6-8bf0-92988856deca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196039195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.196039195
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3351089782
Short name T731
Test name
Test status
Simulation time 23122412 ps
CPU time 0.58 seconds
Started Jun 07 07:32:31 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 193588 kb
Host smart-5a91cb6c-9da2-4039-b162-a8b1780877a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351089782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3351089782
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1361552492
Short name T837
Test name
Test status
Simulation time 175400798 ps
CPU time 0.98 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 197360 kb
Host smart-4f1926b4-0207-42e9-a592-f20c13fe5470
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361552492 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1361552492
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3121797703
Short name T752
Test name
Test status
Simulation time 105181457 ps
CPU time 1.99 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 197928 kb
Host smart-8db4db81-4c69-41d0-be3b-8fe0fb58f9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121797703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3121797703
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3139983013
Short name T829
Test name
Test status
Simulation time 20395349 ps
CPU time 0.67 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 197140 kb
Host smart-ee63c69a-860b-4949-9f58-fadba3ac48dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139983013 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3139983013
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3836679637
Short name T91
Test name
Test status
Simulation time 11205897 ps
CPU time 0.6 seconds
Started Jun 07 07:32:31 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 194636 kb
Host smart-ac8e7e5e-2a3b-4540-be97-c4bef9054e58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836679637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3836679637
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1113636013
Short name T796
Test name
Test status
Simulation time 15404891 ps
CPU time 0.64 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 194288 kb
Host smart-f45ced62-642c-4241-88c7-ca1aa0e986b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113636013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1113636013
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.588111697
Short name T83
Test name
Test status
Simulation time 30718999 ps
CPU time 0.65 seconds
Started Jun 07 07:32:35 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 195368 kb
Host smart-48965361-be4b-43be-a34f-d96a02656bd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588111697 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.588111697
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3615382614
Short name T726
Test name
Test status
Simulation time 296610720 ps
CPU time 1.41 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 197948 kb
Host smart-0de87848-98e2-4d76-aaf0-5718ae0bc756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615382614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3615382614
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.863060554
Short name T783
Test name
Test status
Simulation time 478993762 ps
CPU time 1.12 seconds
Started Jun 07 07:32:32 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 197620 kb
Host smart-8b49692c-1d21-4fca-8fda-17111d6462ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863060554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.863060554
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2695833471
Short name T733
Test name
Test status
Simulation time 55517107 ps
CPU time 0.8 seconds
Started Jun 07 07:32:33 PM PDT 24
Finished Jun 07 07:32:39 PM PDT 24
Peak memory 197568 kb
Host smart-e1e5c031-5ccd-4caf-a554-6398641cb269
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695833471 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2695833471
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2302765989
Short name T771
Test name
Test status
Simulation time 20406645 ps
CPU time 0.58 seconds
Started Jun 07 07:32:37 PM PDT 24
Finished Jun 07 07:32:43 PM PDT 24
Peak memory 194296 kb
Host smart-a905e44f-4eec-44c6-a3ed-912e812e5c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302765989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2302765989
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1762388348
Short name T101
Test name
Test status
Simulation time 71286971 ps
CPU time 0.65 seconds
Started Jun 07 07:32:35 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 194756 kb
Host smart-e641f065-6c1c-4ce1-b00c-bbc533988c02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762388348 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1762388348
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1292937855
Short name T781
Test name
Test status
Simulation time 121215128 ps
CPU time 1.5 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 197936 kb
Host smart-1bf1c797-b819-489e-9270-b9d8c705781f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292937855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1292937855
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.855835571
Short name T44
Test name
Test status
Simulation time 831528281 ps
CPU time 1.18 seconds
Started Jun 07 07:32:35 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 197964 kb
Host smart-4827fa51-e4e2-4d61-a0da-a81d22f0666f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855835571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.855835571
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.191830968
Short name T748
Test name
Test status
Simulation time 131414251 ps
CPU time 0.88 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 198048 kb
Host smart-9b4c523d-b86c-4dd8-8a7f-2061f10ac408
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191830968 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.191830968
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1680637415
Short name T784
Test name
Test status
Simulation time 29767412 ps
CPU time 0.62 seconds
Started Jun 07 07:32:35 PM PDT 24
Finished Jun 07 07:32:42 PM PDT 24
Peak memory 194868 kb
Host smart-805e3f7e-4a11-4ea2-b2a7-40062e1b76f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680637415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1680637415
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4148564468
Short name T827
Test name
Test status
Simulation time 16610044 ps
CPU time 0.6 seconds
Started Jun 07 07:32:30 PM PDT 24
Finished Jun 07 07:32:36 PM PDT 24
Peak memory 193732 kb
Host smart-c57aaa34-9752-46a4-a1d5-9605af8862f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148564468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4148564468
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3531965266
Short name T86
Test name
Test status
Simulation time 75706378 ps
CPU time 0.65 seconds
Started Jun 07 07:32:37 PM PDT 24
Finished Jun 07 07:32:43 PM PDT 24
Peak memory 194480 kb
Host smart-0275b656-cee3-4717-b20c-c57e3b2ad6db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531965266 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3531965266
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2383519950
Short name T745
Test name
Test status
Simulation time 26942349 ps
CPU time 1.24 seconds
Started Jun 07 07:32:36 PM PDT 24
Finished Jun 07 07:32:43 PM PDT 24
Peak memory 198012 kb
Host smart-dc32292f-202f-43d1-aa8b-e70cd4079f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383519950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2383519950
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1163211123
Short name T39
Test name
Test status
Simulation time 431910294 ps
CPU time 1.4 seconds
Started Jun 07 07:32:34 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 197924 kb
Host smart-0c0f3031-6ac9-4efe-a45e-d0368be9f142
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163211123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1163211123
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2285915854
Short name T334
Test name
Test status
Simulation time 30603949 ps
CPU time 0.93 seconds
Started Jun 07 07:35:15 PM PDT 24
Finished Jun 07 07:35:18 PM PDT 24
Peak memory 195856 kb
Host smart-ee4f6dd9-3ad1-43ee-86fc-e8533e2d3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285915854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2285915854
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3313881876
Short name T240
Test name
Test status
Simulation time 1644891837 ps
CPU time 28.15 seconds
Started Jun 07 07:35:17 PM PDT 24
Finished Jun 07 07:35:46 PM PDT 24
Peak memory 197184 kb
Host smart-d560a519-4dbb-4629-99c5-59da7aaa3947
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313881876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3313881876
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2413373123
Short name T403
Test name
Test status
Simulation time 149119464 ps
CPU time 0.83 seconds
Started Jun 07 07:35:21 PM PDT 24
Finished Jun 07 07:35:23 PM PDT 24
Peak memory 196188 kb
Host smart-0eaf321b-da7d-4182-9366-d870abd38a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413373123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2413373123
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.204065122
Short name T116
Test name
Test status
Simulation time 81819326 ps
CPU time 1.31 seconds
Started Jun 07 07:35:21 PM PDT 24
Finished Jun 07 07:35:23 PM PDT 24
Peak memory 195864 kb
Host smart-27e1a36d-08e3-457a-bc8f-52bbd8421ad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204065122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.204065122
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.584223087
Short name T419
Test name
Test status
Simulation time 34429858 ps
CPU time 1.54 seconds
Started Jun 07 07:35:19 PM PDT 24
Finished Jun 07 07:35:21 PM PDT 24
Peak memory 196972 kb
Host smart-f0c932f1-7b68-4673-9f8d-3d715310222c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584223087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.584223087
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2992669369
Short name T547
Test name
Test status
Simulation time 258732011 ps
CPU time 1.69 seconds
Started Jun 07 07:35:16 PM PDT 24
Finished Jun 07 07:35:19 PM PDT 24
Peak memory 196036 kb
Host smart-5449a9de-a3da-4e5a-bd9d-fa287d7af361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992669369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2992669369
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.658640326
Short name T339
Test name
Test status
Simulation time 428994995 ps
CPU time 1.36 seconds
Started Jun 07 07:35:10 PM PDT 24
Finished Jun 07 07:35:14 PM PDT 24
Peak memory 198128 kb
Host smart-be16b328-d68f-4998-8cc9-e660fdaf3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658640326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.658640326
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2975046300
Short name T253
Test name
Test status
Simulation time 186834957 ps
CPU time 1.07 seconds
Started Jun 07 07:35:14 PM PDT 24
Finished Jun 07 07:35:16 PM PDT 24
Peak memory 195948 kb
Host smart-ba9153cc-c0bc-4bb6-bd5d-ae6c367a0be6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975046300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2975046300
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3595659509
Short name T538
Test name
Test status
Simulation time 4594139182 ps
CPU time 3.93 seconds
Started Jun 07 07:35:17 PM PDT 24
Finished Jun 07 07:35:23 PM PDT 24
Peak memory 198120 kb
Host smart-308bec72-6b41-4516-9f88-410976d2d763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595659509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3595659509
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3197544851
Short name T33
Test name
Test status
Simulation time 436905682 ps
CPU time 0.97 seconds
Started Jun 07 07:35:24 PM PDT 24
Finished Jun 07 07:35:27 PM PDT 24
Peak memory 215068 kb
Host smart-49dd6159-0e7b-4eac-b6ee-7d770bc249ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197544851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3197544851
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2182346988
Short name T139
Test name
Test status
Simulation time 75569819 ps
CPU time 1.43 seconds
Started Jun 07 07:35:09 PM PDT 24
Finished Jun 07 07:35:12 PM PDT 24
Peak memory 195708 kb
Host smart-10946737-5ece-4434-b98d-c735e2f34a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182346988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2182346988
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.646463571
Short name T619
Test name
Test status
Simulation time 551644633 ps
CPU time 0.82 seconds
Started Jun 07 07:35:08 PM PDT 24
Finished Jun 07 07:35:10 PM PDT 24
Peak memory 195940 kb
Host smart-d67b3371-609f-42e2-bcce-ab08ec1d6617
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646463571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.646463571
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1043361232
Short name T494
Test name
Test status
Simulation time 6636622135 ps
CPU time 172.15 seconds
Started Jun 07 07:35:19 PM PDT 24
Finished Jun 07 07:38:13 PM PDT 24
Peak memory 198236 kb
Host smart-7faa03bc-11e6-4746-a093-0264dc465097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043361232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1043361232
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.275659215
Short name T53
Test name
Test status
Simulation time 20378784846 ps
CPU time 627.69 seconds
Started Jun 07 07:35:25 PM PDT 24
Finished Jun 07 07:45:55 PM PDT 24
Peak memory 198256 kb
Host smart-7c899865-b651-4af2-b684-fef7bd7c0b30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=275659215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.275659215
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4139747352
Short name T394
Test name
Test status
Simulation time 44228875 ps
CPU time 0.57 seconds
Started Jun 07 07:35:39 PM PDT 24
Finished Jun 07 07:35:41 PM PDT 24
Peak memory 193988 kb
Host smart-41a3bbcb-6216-459d-aace-93fdc867222a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139747352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4139747352
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.50343403
Short name T492
Test name
Test status
Simulation time 63496933 ps
CPU time 0.87 seconds
Started Jun 07 07:35:25 PM PDT 24
Finished Jun 07 07:35:27 PM PDT 24
Peak memory 196460 kb
Host smart-441c37d0-5e0b-4f64-b36b-91a7011e0ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50343403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.50343403
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.379121999
Short name T230
Test name
Test status
Simulation time 1119357448 ps
CPU time 15.61 seconds
Started Jun 07 07:35:26 PM PDT 24
Finished Jun 07 07:35:44 PM PDT 24
Peak memory 198064 kb
Host smart-8a897e7f-7b02-4e47-971d-ffb9a8419d18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379121999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.379121999
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1052370465
Short name T425
Test name
Test status
Simulation time 121728506 ps
CPU time 0.96 seconds
Started Jun 07 07:35:22 PM PDT 24
Finished Jun 07 07:35:24 PM PDT 24
Peak memory 197932 kb
Host smart-73d4d6c8-3eaa-412a-b6a0-deeb629fabfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052370465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1052370465
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1994758597
Short name T557
Test name
Test status
Simulation time 518461700 ps
CPU time 1.46 seconds
Started Jun 07 07:35:24 PM PDT 24
Finished Jun 07 07:35:28 PM PDT 24
Peak memory 198100 kb
Host smart-502f8383-a6d8-4bfd-b3f1-238f6ff9ebe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994758597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1994758597
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3563278777
Short name T479
Test name
Test status
Simulation time 95773060 ps
CPU time 3.77 seconds
Started Jun 07 07:35:24 PM PDT 24
Finished Jun 07 07:35:29 PM PDT 24
Peak memory 198080 kb
Host smart-fe8341ee-d0d0-4b5c-a9aa-5bd0349408ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563278777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3563278777
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.440071086
Short name T201
Test name
Test status
Simulation time 650252681 ps
CPU time 3.31 seconds
Started Jun 07 07:35:22 PM PDT 24
Finished Jun 07 07:35:27 PM PDT 24
Peak memory 197232 kb
Host smart-11ab186f-8cea-4c77-a306-3220fe8b2a36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440071086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.440071086
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2298885865
Short name T420
Test name
Test status
Simulation time 28275307 ps
CPU time 1.1 seconds
Started Jun 07 07:35:24 PM PDT 24
Finished Jun 07 07:35:27 PM PDT 24
Peak memory 195880 kb
Host smart-5dd0d348-0497-4ecf-98a2-264d3a8182e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298885865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2298885865
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2642053084
Short name T239
Test name
Test status
Simulation time 117570215 ps
CPU time 1.38 seconds
Started Jun 07 07:35:24 PM PDT 24
Finished Jun 07 07:35:28 PM PDT 24
Peak memory 196972 kb
Host smart-d959d8c7-cdbf-45cd-abf0-26f3f53d63fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642053084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2642053084
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1108725782
Short name T501
Test name
Test status
Simulation time 2540497266 ps
CPU time 4.79 seconds
Started Jun 07 07:35:26 PM PDT 24
Finished Jun 07 07:35:32 PM PDT 24
Peak memory 198168 kb
Host smart-b02e9c9c-3d71-47cb-b531-2bc4f3aa3400
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108725782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1108725782
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3137426061
Short name T48
Test name
Test status
Simulation time 62728027 ps
CPU time 0.88 seconds
Started Jun 07 07:35:31 PM PDT 24
Finished Jun 07 07:35:33 PM PDT 24
Peak memory 213824 kb
Host smart-b98a4c54-8d13-42d6-b0ff-a72599a6093f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137426061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3137426061
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2461743660
Short name T627
Test name
Test status
Simulation time 54483699 ps
CPU time 1.14 seconds
Started Jun 07 07:35:25 PM PDT 24
Finished Jun 07 07:35:28 PM PDT 24
Peak memory 195880 kb
Host smart-eb0895a5-fe28-4e41-a543-cb63786eda14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461743660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2461743660
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2786098648
Short name T528
Test name
Test status
Simulation time 170204366 ps
CPU time 1.21 seconds
Started Jun 07 07:35:24 PM PDT 24
Finished Jun 07 07:35:27 PM PDT 24
Peak memory 195656 kb
Host smart-4bd2fd3d-a4e2-4201-94e4-e495ad94b500
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786098648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2786098648
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3749009331
Short name T676
Test name
Test status
Simulation time 21855582446 ps
CPU time 162.65 seconds
Started Jun 07 07:35:26 PM PDT 24
Finished Jun 07 07:38:10 PM PDT 24
Peak memory 198192 kb
Host smart-803117e0-dc6d-4f1f-9464-efa01f286438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749009331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3749009331
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1999249209
Short name T625
Test name
Test status
Simulation time 130961329364 ps
CPU time 186.65 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:38:42 PM PDT 24
Peak memory 206524 kb
Host smart-967e71eb-d472-4332-9f0f-e4e1f85a155d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1999249209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1999249209
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.902769799
Short name T715
Test name
Test status
Simulation time 36607648 ps
CPU time 0.57 seconds
Started Jun 07 07:36:29 PM PDT 24
Finished Jun 07 07:36:32 PM PDT 24
Peak memory 194160 kb
Host smart-1801ce52-290e-460a-a544-5f56a529c555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902769799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.902769799
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.4275500063
Short name T145
Test name
Test status
Simulation time 23931980 ps
CPU time 0.8 seconds
Started Jun 07 07:36:31 PM PDT 24
Finished Jun 07 07:36:33 PM PDT 24
Peak memory 195332 kb
Host smart-5ce95fe7-5cf6-4425-a489-ac20bd1f39e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275500063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.4275500063
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1697995731
Short name T644
Test name
Test status
Simulation time 517911801 ps
CPU time 4.87 seconds
Started Jun 07 07:36:30 PM PDT 24
Finished Jun 07 07:36:36 PM PDT 24
Peak memory 196008 kb
Host smart-67a52d14-d95a-4b3a-a531-b49255f61832
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697995731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1697995731
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2546262653
Short name T46
Test name
Test status
Simulation time 79197047 ps
CPU time 0.77 seconds
Started Jun 07 07:36:29 PM PDT 24
Finished Jun 07 07:36:32 PM PDT 24
Peak memory 196576 kb
Host smart-597e2f87-7a61-4933-a9a2-649d963f4965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546262653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2546262653
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2659455417
Short name T319
Test name
Test status
Simulation time 42949346 ps
CPU time 0.81 seconds
Started Jun 07 07:36:28 PM PDT 24
Finished Jun 07 07:36:30 PM PDT 24
Peak memory 195696 kb
Host smart-f2deb207-3e33-49a3-8a75-0779585f50d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659455417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2659455417
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1435629910
Short name T333
Test name
Test status
Simulation time 776265133 ps
CPU time 2.2 seconds
Started Jun 07 07:36:27 PM PDT 24
Finished Jun 07 07:36:30 PM PDT 24
Peak memory 198148 kb
Host smart-1c0c5aaa-6ad6-4436-804d-5d039992ae37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435629910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1435629910
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.10699771
Short name T604
Test name
Test status
Simulation time 71744258 ps
CPU time 2.16 seconds
Started Jun 07 07:36:30 PM PDT 24
Finished Jun 07 07:36:34 PM PDT 24
Peak memory 197032 kb
Host smart-5ce39df8-15d5-41f4-aa61-b1b20e33eb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.10699771
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4013754589
Short name T698
Test name
Test status
Simulation time 88541898 ps
CPU time 0.73 seconds
Started Jun 07 07:36:28 PM PDT 24
Finished Jun 07 07:36:30 PM PDT 24
Peak memory 195528 kb
Host smart-13d763a0-7a1e-4546-a12a-2fd3e0cb41e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013754589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4013754589
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.693271703
Short name T203
Test name
Test status
Simulation time 51883724 ps
CPU time 0.7 seconds
Started Jun 07 07:36:27 PM PDT 24
Finished Jun 07 07:36:28 PM PDT 24
Peak memory 194352 kb
Host smart-a7b8b744-87b4-4930-a007-b6297591b2b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693271703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.693271703
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1723913801
Short name T260
Test name
Test status
Simulation time 145151734 ps
CPU time 1.99 seconds
Started Jun 07 07:36:29 PM PDT 24
Finished Jun 07 07:36:32 PM PDT 24
Peak memory 198084 kb
Host smart-76879bc0-6189-40f2-ba32-367cdefc8c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723913801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1723913801
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.835224075
Short name T666
Test name
Test status
Simulation time 151182988 ps
CPU time 0.82 seconds
Started Jun 07 07:36:26 PM PDT 24
Finished Jun 07 07:36:28 PM PDT 24
Peak memory 195460 kb
Host smart-d49788cd-3764-4e63-85d6-730e6b97b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835224075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.835224075
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.723748492
Short name T503
Test name
Test status
Simulation time 793974661 ps
CPU time 1.36 seconds
Started Jun 07 07:36:27 PM PDT 24
Finished Jun 07 07:36:30 PM PDT 24
Peak memory 197972 kb
Host smart-12ac6818-00b4-4b80-9458-c629e2129a7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723748492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.723748492
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.535816485
Short name T480
Test name
Test status
Simulation time 6008355643 ps
CPU time 40.07 seconds
Started Jun 07 07:36:30 PM PDT 24
Finished Jun 07 07:37:12 PM PDT 24
Peak memory 198232 kb
Host smart-7246326c-bd75-40ea-b926-37f7a3cb0d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535816485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.535816485
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.729622213
Short name T524
Test name
Test status
Simulation time 95731545 ps
CPU time 0.57 seconds
Started Jun 07 07:36:38 PM PDT 24
Finished Jun 07 07:36:40 PM PDT 24
Peak memory 193948 kb
Host smart-f678835d-0e47-4091-bea4-5a5cab85e4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729622213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.729622213
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3845711056
Short name T350
Test name
Test status
Simulation time 143517387 ps
CPU time 0.88 seconds
Started Jun 07 07:36:33 PM PDT 24
Finished Jun 07 07:36:35 PM PDT 24
Peak memory 196656 kb
Host smart-2fc73b95-637c-4161-ac39-9d5103d250c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845711056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3845711056
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2053618205
Short name T310
Test name
Test status
Simulation time 7487442567 ps
CPU time 25.43 seconds
Started Jun 07 07:36:32 PM PDT 24
Finished Jun 07 07:36:58 PM PDT 24
Peak memory 196724 kb
Host smart-398c8d2d-f373-45db-94f3-b35d6138a235
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053618205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2053618205
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1936960364
Short name T197
Test name
Test status
Simulation time 41718271 ps
CPU time 0.82 seconds
Started Jun 07 07:36:33 PM PDT 24
Finished Jun 07 07:36:35 PM PDT 24
Peak memory 195952 kb
Host smart-6c876fb6-dc62-447a-bb28-fe39028ae81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936960364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1936960364
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1118608293
Short name T326
Test name
Test status
Simulation time 612702158 ps
CPU time 1.2 seconds
Started Jun 07 07:36:34 PM PDT 24
Finished Jun 07 07:36:37 PM PDT 24
Peak memory 195964 kb
Host smart-70e9226d-7daf-4d63-8271-91d2fa07c229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118608293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1118608293
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.597808402
Short name T305
Test name
Test status
Simulation time 76699940 ps
CPU time 2.83 seconds
Started Jun 07 07:36:34 PM PDT 24
Finished Jun 07 07:36:38 PM PDT 24
Peak memory 198056 kb
Host smart-8dafd12d-c2f4-4a78-808e-0e621f2702a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597808402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.597808402
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.37247157
Short name T261
Test name
Test status
Simulation time 40818301 ps
CPU time 1.42 seconds
Started Jun 07 07:36:37 PM PDT 24
Finished Jun 07 07:36:40 PM PDT 24
Peak memory 196800 kb
Host smart-3bbfa704-2dd6-4b5f-bbb2-a8922ad21abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.37247157
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3733708817
Short name T507
Test name
Test status
Simulation time 68038970 ps
CPU time 0.9 seconds
Started Jun 07 07:36:37 PM PDT 24
Finished Jun 07 07:36:39 PM PDT 24
Peak memory 196668 kb
Host smart-0f70cc24-f470-4435-b5d1-094147b0f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733708817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3733708817
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1915541076
Short name T349
Test name
Test status
Simulation time 36843365 ps
CPU time 1.26 seconds
Started Jun 07 07:36:34 PM PDT 24
Finished Jun 07 07:36:37 PM PDT 24
Peak memory 196592 kb
Host smart-d07a984d-8598-4d82-b80c-8fc3325ab956
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915541076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1915541076
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3728238984
Short name T504
Test name
Test status
Simulation time 299497333 ps
CPU time 3.78 seconds
Started Jun 07 07:36:35 PM PDT 24
Finished Jun 07 07:36:40 PM PDT 24
Peak memory 197912 kb
Host smart-a9547121-841c-4c8f-8c72-b966a8e457a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728238984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3728238984
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1512336338
Short name T573
Test name
Test status
Simulation time 98186043 ps
CPU time 1.02 seconds
Started Jun 07 07:36:34 PM PDT 24
Finished Jun 07 07:36:36 PM PDT 24
Peak memory 195488 kb
Host smart-43524ee2-6b25-414c-8e59-4c87875f4805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512336338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1512336338
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.368536828
Short name T259
Test name
Test status
Simulation time 363589763 ps
CPU time 1.55 seconds
Started Jun 07 07:36:36 PM PDT 24
Finished Jun 07 07:36:39 PM PDT 24
Peak memory 198028 kb
Host smart-575b90db-c61a-42a7-b531-7f6cac3f0054
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368536828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.368536828
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2839812323
Short name T716
Test name
Test status
Simulation time 28639802702 ps
CPU time 44.94 seconds
Started Jun 07 07:36:39 PM PDT 24
Finished Jun 07 07:37:25 PM PDT 24
Peak memory 198268 kb
Host smart-1e1ef0ae-0575-4394-bcb0-5ce0b7a31ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839812323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2839812323
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2381777414
Short name T446
Test name
Test status
Simulation time 118243808424 ps
CPU time 544.6 seconds
Started Jun 07 07:36:37 PM PDT 24
Finished Jun 07 07:45:43 PM PDT 24
Peak memory 198268 kb
Host smart-1176d6f3-5456-48d7-ad76-39a202a43358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2381777414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2381777414
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2893494690
Short name T429
Test name
Test status
Simulation time 20782477 ps
CPU time 0.6 seconds
Started Jun 07 07:36:50 PM PDT 24
Finished Jun 07 07:36:52 PM PDT 24
Peak memory 193932 kb
Host smart-2fa86842-ecff-4c7d-b81b-a5728563427d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893494690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2893494690
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3123538015
Short name T219
Test name
Test status
Simulation time 26985057 ps
CPU time 0.78 seconds
Started Jun 07 07:36:44 PM PDT 24
Finished Jun 07 07:36:46 PM PDT 24
Peak memory 196124 kb
Host smart-c1abf817-38fc-4c36-a710-a4b2eb0a9c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123538015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3123538015
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1181519379
Short name T526
Test name
Test status
Simulation time 2241147959 ps
CPU time 8.3 seconds
Started Jun 07 07:36:43 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 197052 kb
Host smart-59d9a833-c31a-4db5-973d-3e4ac9c5efe1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181519379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1181519379
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.629387687
Short name T138
Test name
Test status
Simulation time 65053671 ps
CPU time 1.1 seconds
Started Jun 07 07:36:42 PM PDT 24
Finished Jun 07 07:36:44 PM PDT 24
Peak memory 196644 kb
Host smart-71a53988-72fb-4b72-bb13-53aada13a483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629387687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.629387687
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1220241878
Short name T508
Test name
Test status
Simulation time 129671710 ps
CPU time 0.94 seconds
Started Jun 07 07:36:44 PM PDT 24
Finished Jun 07 07:36:46 PM PDT 24
Peak memory 196436 kb
Host smart-1b6943a9-fcf8-49af-ba51-a2e29ade927a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220241878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1220241878
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3595845941
Short name T119
Test name
Test status
Simulation time 286537771 ps
CPU time 2.96 seconds
Started Jun 07 07:36:42 PM PDT 24
Finished Jun 07 07:36:45 PM PDT 24
Peak memory 198076 kb
Host smart-337df447-3399-40cb-b264-48efcb50ebbb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595845941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3595845941
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3498924834
Short name T212
Test name
Test status
Simulation time 45386333 ps
CPU time 1.07 seconds
Started Jun 07 07:36:44 PM PDT 24
Finished Jun 07 07:36:46 PM PDT 24
Peak memory 196212 kb
Host smart-d83fa959-b333-45c3-8a77-75b64a2ef1a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498924834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3498924834
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1619376843
Short name T274
Test name
Test status
Simulation time 18345923 ps
CPU time 0.76 seconds
Started Jun 07 07:36:42 PM PDT 24
Finished Jun 07 07:36:44 PM PDT 24
Peak memory 196140 kb
Host smart-901727b7-05bd-4e45-a035-3821f96532ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619376843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1619376843
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1325642769
Short name T598
Test name
Test status
Simulation time 33878826 ps
CPU time 0.86 seconds
Started Jun 07 07:36:44 PM PDT 24
Finished Jun 07 07:36:46 PM PDT 24
Peak memory 196736 kb
Host smart-80690a33-7197-4222-ac10-2d686f0abb46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325642769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1325642769
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.906832003
Short name T707
Test name
Test status
Simulation time 302247580 ps
CPU time 4.14 seconds
Started Jun 07 07:36:43 PM PDT 24
Finished Jun 07 07:36:48 PM PDT 24
Peak memory 197992 kb
Host smart-fed662b5-a248-4391-b9c9-b90bb858ac77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906832003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.906832003
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3946878974
Short name T490
Test name
Test status
Simulation time 207925351 ps
CPU time 1.14 seconds
Started Jun 07 07:36:33 PM PDT 24
Finished Jun 07 07:36:35 PM PDT 24
Peak memory 195576 kb
Host smart-9c1d69ec-f377-4792-aa78-19ff285065dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946878974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3946878974
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3831942190
Short name T198
Test name
Test status
Simulation time 74589650 ps
CPU time 1.23 seconds
Started Jun 07 07:36:42 PM PDT 24
Finished Jun 07 07:36:45 PM PDT 24
Peak memory 195640 kb
Host smart-831741ca-2df3-4087-befe-f3af37fd54c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831942190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3831942190
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.905864941
Short name T509
Test name
Test status
Simulation time 59694654301 ps
CPU time 105.18 seconds
Started Jun 07 07:36:43 PM PDT 24
Finished Jun 07 07:38:29 PM PDT 24
Peak memory 198236 kb
Host smart-520a2dda-67c0-46bf-bb72-b2719958e50b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905864941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.905864941
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1286975475
Short name T589
Test name
Test status
Simulation time 27636189 ps
CPU time 0.58 seconds
Started Jun 07 07:36:51 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 194164 kb
Host smart-cf699b77-c052-47c3-af2a-0ff2b39133c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286975475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1286975475
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4092144368
Short name T444
Test name
Test status
Simulation time 22559585 ps
CPU time 0.7 seconds
Started Jun 07 07:36:53 PM PDT 24
Finished Jun 07 07:36:55 PM PDT 24
Peak memory 194960 kb
Host smart-c7e414ff-c205-4c31-a2ff-e85631525815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092144368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4092144368
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2602435525
Short name T25
Test name
Test status
Simulation time 4110648725 ps
CPU time 10.84 seconds
Started Jun 07 07:36:50 PM PDT 24
Finished Jun 07 07:37:01 PM PDT 24
Peak memory 196860 kb
Host smart-56483551-c6e8-4394-9ae4-a1a845925440
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602435525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2602435525
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.751553565
Short name T331
Test name
Test status
Simulation time 44063108 ps
CPU time 0.77 seconds
Started Jun 07 07:36:50 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 195828 kb
Host smart-e349b876-b81d-4c7e-90d0-3a6fe8639640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751553565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.751553565
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4079802977
Short name T209
Test name
Test status
Simulation time 63881870 ps
CPU time 1.05 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:00 PM PDT 24
Peak memory 196548 kb
Host smart-9cc6f459-5921-46d2-8797-653cf697680c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079802977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4079802977
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3234147600
Short name T68
Test name
Test status
Simulation time 313573260 ps
CPU time 3.02 seconds
Started Jun 07 07:36:52 PM PDT 24
Finished Jun 07 07:36:57 PM PDT 24
Peak memory 198108 kb
Host smart-caf3c498-4fac-49db-a1c4-e2d2f55e4427
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234147600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3234147600
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1310341193
Short name T719
Test name
Test status
Simulation time 176790792 ps
CPU time 2.84 seconds
Started Jun 07 07:36:54 PM PDT 24
Finished Jun 07 07:36:58 PM PDT 24
Peak memory 198112 kb
Host smart-02a4d0d0-8ffd-4cba-bf49-69b4b9c05c95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310341193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1310341193
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3838772813
Short name T477
Test name
Test status
Simulation time 146332758 ps
CPU time 1.31 seconds
Started Jun 07 07:36:53 PM PDT 24
Finished Jun 07 07:36:56 PM PDT 24
Peak memory 197012 kb
Host smart-bc64fe52-4420-460a-bb4c-975be5f9c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838772813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3838772813
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1138852076
Short name T693
Test name
Test status
Simulation time 346236275 ps
CPU time 1.31 seconds
Started Jun 07 07:36:51 PM PDT 24
Finished Jun 07 07:36:54 PM PDT 24
Peak memory 197196 kb
Host smart-aa8e1d0a-7f63-478f-8326-4bcb77065818
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138852076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1138852076
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2019900245
Short name T336
Test name
Test status
Simulation time 114829754 ps
CPU time 2.94 seconds
Started Jun 07 07:36:50 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 198052 kb
Host smart-d6a829ef-b804-476a-bb14-09de33a72131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019900245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2019900245
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3527231743
Short name T235
Test name
Test status
Simulation time 317827427 ps
CPU time 1.4 seconds
Started Jun 07 07:36:50 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 196000 kb
Host smart-de19095e-d31c-490c-a9db-6daa32787b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527231743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3527231743
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3290568164
Short name T701
Test name
Test status
Simulation time 31664825 ps
CPU time 0.84 seconds
Started Jun 07 07:36:50 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 196028 kb
Host smart-33ec06ee-01d5-4bf1-9f73-c76c7567b87b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290568164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3290568164
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1100090264
Short name T121
Test name
Test status
Simulation time 17277736617 ps
CPU time 123.63 seconds
Started Jun 07 07:36:53 PM PDT 24
Finished Jun 07 07:38:58 PM PDT 24
Peak memory 198120 kb
Host smart-ae1b76bd-b6d5-437b-9a7e-5f57b67a8756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100090264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1100090264
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.933408405
Short name T28
Test name
Test status
Simulation time 172654472395 ps
CPU time 1123.02 seconds
Started Jun 07 07:36:56 PM PDT 24
Finished Jun 07 07:55:41 PM PDT 24
Peak memory 198292 kb
Host smart-2bbe4adb-35cd-458e-9914-08325d4e3abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=933408405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.933408405
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3552515032
Short name T401
Test name
Test status
Simulation time 35211555 ps
CPU time 0.57 seconds
Started Jun 07 07:36:55 PM PDT 24
Finished Jun 07 07:36:57 PM PDT 24
Peak memory 194876 kb
Host smart-d2c28371-8b2b-476f-aa08-575d2742b72d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552515032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3552515032
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1833556073
Short name T123
Test name
Test status
Simulation time 48367246 ps
CPU time 0.85 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:01 PM PDT 24
Peak memory 196552 kb
Host smart-22391d5f-5742-42bd-a06b-7c37c8e8868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833556073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1833556073
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3019119040
Short name T697
Test name
Test status
Simulation time 666316370 ps
CPU time 13.76 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:14 PM PDT 24
Peak memory 197032 kb
Host smart-79c0b381-46fb-44b8-885a-0f7a2bbd64ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019119040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3019119040
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3378158444
Short name T413
Test name
Test status
Simulation time 118199129 ps
CPU time 0.74 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:00 PM PDT 24
Peak memory 194856 kb
Host smart-76ce17bc-5b48-4ac4-96e7-f3df30fffeab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378158444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3378158444
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3059118836
Short name T243
Test name
Test status
Simulation time 67761018 ps
CPU time 0.69 seconds
Started Jun 07 07:36:57 PM PDT 24
Finished Jun 07 07:36:59 PM PDT 24
Peak memory 194396 kb
Host smart-f5e6d98c-fc2b-4490-9bae-b5f8cb8ba474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059118836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3059118836
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3225523724
Short name T646
Test name
Test status
Simulation time 281320707 ps
CPU time 2.77 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:02 PM PDT 24
Peak memory 198144 kb
Host smart-6322d0b4-4f10-462b-988c-a9ab480e7349
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225523724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3225523724
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2619676767
Short name T131
Test name
Test status
Simulation time 103938252 ps
CPU time 2.06 seconds
Started Jun 07 07:36:57 PM PDT 24
Finished Jun 07 07:37:01 PM PDT 24
Peak memory 196200 kb
Host smart-34e065b4-02af-403d-9999-d5fc5bc01e13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619676767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2619676767
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3142836126
Short name T681
Test name
Test status
Simulation time 16873305 ps
CPU time 0.73 seconds
Started Jun 07 07:36:51 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 196220 kb
Host smart-8dbffb38-3f8c-4302-b049-ab2f9aaee9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142836126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3142836126
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2748615416
Short name T667
Test name
Test status
Simulation time 79901334 ps
CPU time 0.66 seconds
Started Jun 07 07:36:49 PM PDT 24
Finished Jun 07 07:36:50 PM PDT 24
Peak memory 195108 kb
Host smart-ba29ae38-9995-4e07-8b0c-4d7ab4c45ef0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748615416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2748615416
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1769914629
Short name T306
Test name
Test status
Simulation time 395931194 ps
CPU time 5.59 seconds
Started Jun 07 07:37:00 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 198008 kb
Host smart-7a412720-f119-433d-b337-9809d8e2afe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769914629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1769914629
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2613340012
Short name T637
Test name
Test status
Simulation time 24845829 ps
CPU time 0.76 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:00 PM PDT 24
Peak memory 195896 kb
Host smart-249d9fad-cece-4950-80da-612c8c0929de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613340012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2613340012
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2815022798
Short name T300
Test name
Test status
Simulation time 46180059 ps
CPU time 1.24 seconds
Started Jun 07 07:36:54 PM PDT 24
Finished Jun 07 07:36:56 PM PDT 24
Peak memory 195692 kb
Host smart-4d5200fa-0bad-4451-b00c-a919aad09560
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815022798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2815022798
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2193782803
Short name T691
Test name
Test status
Simulation time 12630487832 ps
CPU time 47.59 seconds
Started Jun 07 07:36:59 PM PDT 24
Finished Jun 07 07:37:48 PM PDT 24
Peak memory 198312 kb
Host smart-b6bd2a1e-ac40-48ef-98d9-3d3dfb047a08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193782803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2193782803
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3667343905
Short name T234
Test name
Test status
Simulation time 21631206 ps
CPU time 0.56 seconds
Started Jun 07 07:37:06 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 194160 kb
Host smart-178d2398-1171-40be-a3f2-42b339347d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667343905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3667343905
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3654333138
Short name T651
Test name
Test status
Simulation time 28221790 ps
CPU time 0.82 seconds
Started Jun 07 07:37:00 PM PDT 24
Finished Jun 07 07:37:02 PM PDT 24
Peak memory 197384 kb
Host smart-742097a2-72f5-4106-9258-ce8988b3d6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654333138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3654333138
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1936272979
Short name T391
Test name
Test status
Simulation time 639567056 ps
CPU time 21.74 seconds
Started Jun 07 07:37:06 PM PDT 24
Finished Jun 07 07:37:29 PM PDT 24
Peak memory 196908 kb
Host smart-28dc51df-97f2-4885-b302-0390b3da0463
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936272979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1936272979
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1258547439
Short name T474
Test name
Test status
Simulation time 33155537 ps
CPU time 0.62 seconds
Started Jun 07 07:37:04 PM PDT 24
Finished Jun 07 07:37:06 PM PDT 24
Peak memory 194456 kb
Host smart-cf4424eb-ef14-47cb-8cc4-461e8c517e0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258547439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1258547439
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2067118191
Short name T588
Test name
Test status
Simulation time 37714961 ps
CPU time 0.87 seconds
Started Jun 07 07:36:57 PM PDT 24
Finished Jun 07 07:36:59 PM PDT 24
Peak memory 196532 kb
Host smart-5c14341c-62da-4a25-bbb7-3e5aca1c7e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067118191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2067118191
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3521399470
Short name T483
Test name
Test status
Simulation time 289823554 ps
CPU time 1.11 seconds
Started Jun 07 07:37:05 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 197968 kb
Host smart-eba51bb2-5b94-4bf5-b521-4ac2740e17e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521399470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3521399470
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.624252506
Short name T568
Test name
Test status
Simulation time 268140415 ps
CPU time 1.59 seconds
Started Jun 07 07:36:57 PM PDT 24
Finished Jun 07 07:37:00 PM PDT 24
Peak memory 195852 kb
Host smart-1ae67da3-0192-4102-8e04-21319a4b5e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624252506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
624252506
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2582133265
Short name T422
Test name
Test status
Simulation time 22337736 ps
CPU time 0.86 seconds
Started Jun 07 07:37:00 PM PDT 24
Finished Jun 07 07:37:02 PM PDT 24
Peak memory 196744 kb
Host smart-21a36a23-dc23-4c4f-bea4-ef1dadd37dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582133265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2582133265
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4085166840
Short name T208
Test name
Test status
Simulation time 51857781 ps
CPU time 1.16 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:01 PM PDT 24
Peak memory 195928 kb
Host smart-f58b96ef-42f3-47e3-8a3d-7300ad6044f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085166840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4085166840
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1774237619
Short name T128
Test name
Test status
Simulation time 86272119 ps
CPU time 2.1 seconds
Started Jun 07 07:37:05 PM PDT 24
Finished Jun 07 07:37:08 PM PDT 24
Peak memory 198072 kb
Host smart-b08ed8c2-8a49-4f92-84a4-b36487894e9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774237619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1774237619
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3964873867
Short name T143
Test name
Test status
Simulation time 56583209 ps
CPU time 0.75 seconds
Started Jun 07 07:36:56 PM PDT 24
Finished Jun 07 07:36:58 PM PDT 24
Peak memory 196028 kb
Host smart-ed7c7dff-1c45-4925-b94c-32df539e6bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964873867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3964873867
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3798780468
Short name T708
Test name
Test status
Simulation time 68717016 ps
CPU time 1.22 seconds
Started Jun 07 07:36:58 PM PDT 24
Finished Jun 07 07:37:01 PM PDT 24
Peak memory 195788 kb
Host smart-3c2d0555-a7bd-4a2c-be75-f7db3f445ab0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798780468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3798780468
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1553911999
Short name T76
Test name
Test status
Simulation time 16651854161 ps
CPU time 100.9 seconds
Started Jun 07 07:37:05 PM PDT 24
Finished Jun 07 07:38:47 PM PDT 24
Peak memory 198152 kb
Host smart-0758bade-ef49-473d-afa3-9f1e0df09ede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553911999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1553911999
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.4102450294
Short name T266
Test name
Test status
Simulation time 35502303 ps
CPU time 0.57 seconds
Started Jun 07 07:37:13 PM PDT 24
Finished Jun 07 07:37:14 PM PDT 24
Peak memory 194676 kb
Host smart-ee54c9ca-f9f0-45ef-bc50-6d8b1e18f877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102450294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.4102450294
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4037885234
Short name T122
Test name
Test status
Simulation time 20249964 ps
CPU time 0.69 seconds
Started Jun 07 07:37:05 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 194252 kb
Host smart-5c393b23-d7d4-44cf-a08a-9943977f7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037885234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4037885234
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4221113069
Short name T303
Test name
Test status
Simulation time 272015276 ps
CPU time 9.72 seconds
Started Jun 07 07:37:13 PM PDT 24
Finished Jun 07 07:37:24 PM PDT 24
Peak memory 197152 kb
Host smart-9e16c166-3039-4b03-af0b-17e9b671ba8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221113069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4221113069
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4268994867
Short name T186
Test name
Test status
Simulation time 95357744 ps
CPU time 0.82 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 195960 kb
Host smart-383f7185-2855-40e3-8827-eab34ff6308e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268994867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4268994867
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1521443296
Short name T15
Test name
Test status
Simulation time 320331616 ps
CPU time 1.15 seconds
Started Jun 07 07:37:05 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 196184 kb
Host smart-a8d59ea4-8f94-4041-be58-38af62a82d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521443296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1521443296
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3221110125
Short name T723
Test name
Test status
Simulation time 186912761 ps
CPU time 2.12 seconds
Started Jun 07 07:37:13 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 198132 kb
Host smart-d105ddf8-0b31-4f39-a11b-4101a17a8a6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221110125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3221110125
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1646894437
Short name T567
Test name
Test status
Simulation time 74239162 ps
CPU time 1.57 seconds
Started Jun 07 07:37:04 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 196112 kb
Host smart-0ce915e0-90b2-4d22-8909-11b549447ae8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646894437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1646894437
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3385381134
Short name T497
Test name
Test status
Simulation time 33205562 ps
CPU time 1.1 seconds
Started Jun 07 07:37:04 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 196116 kb
Host smart-6e2d69f9-762f-457b-abc1-c9107445c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385381134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3385381134
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1943465412
Short name T258
Test name
Test status
Simulation time 55128040 ps
CPU time 0.69 seconds
Started Jun 07 07:37:08 PM PDT 24
Finished Jun 07 07:37:10 PM PDT 24
Peak memory 195564 kb
Host smart-5fa331ee-2c48-43f0-8263-980c01e9d434
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943465412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1943465412
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2129071119
Short name T54
Test name
Test status
Simulation time 52726441 ps
CPU time 2.28 seconds
Started Jun 07 07:37:15 PM PDT 24
Finished Jun 07 07:37:19 PM PDT 24
Peak memory 198016 kb
Host smart-a142d915-27f8-42c9-b820-3c1778736daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129071119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2129071119
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3218913921
Short name T182
Test name
Test status
Simulation time 123061447 ps
CPU time 1.25 seconds
Started Jun 07 07:37:07 PM PDT 24
Finished Jun 07 07:37:09 PM PDT 24
Peak memory 195732 kb
Host smart-b7ec35e9-848d-40a1-89d2-d72a56e1a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218913921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3218913921
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.983580772
Short name T551
Test name
Test status
Simulation time 134203399 ps
CPU time 1.17 seconds
Started Jun 07 07:37:05 PM PDT 24
Finished Jun 07 07:37:07 PM PDT 24
Peak memory 196528 kb
Host smart-557d3fff-1e8c-4375-9a8f-913e0793abb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983580772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.983580772
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2847290586
Short name T654
Test name
Test status
Simulation time 13870542245 ps
CPU time 87 seconds
Started Jun 07 07:37:12 PM PDT 24
Finished Jun 07 07:38:39 PM PDT 24
Peak memory 198248 kb
Host smart-2435bfeb-6e99-454d-bc75-1c1c228ed32b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847290586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2847290586
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.564087008
Short name T59
Test name
Test status
Simulation time 555607508942 ps
CPU time 935.65 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:52:50 PM PDT 24
Peak memory 198316 kb
Host smart-fdfef246-b4fa-4c2c-91f7-7e3a35c18806
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=564087008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.564087008
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1367841299
Short name T352
Test name
Test status
Simulation time 55125518 ps
CPU time 0.54 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 193948 kb
Host smart-f62cc024-311c-4788-9df9-03589d51ba45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367841299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1367841299
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1536703141
Short name T137
Test name
Test status
Simulation time 27812818 ps
CPU time 0.76 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 195316 kb
Host smart-a1286a22-e36f-4c6a-bad1-e1201e5d79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536703141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1536703141
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2379965585
Short name T414
Test name
Test status
Simulation time 229394741 ps
CPU time 4.36 seconds
Started Jun 07 07:37:15 PM PDT 24
Finished Jun 07 07:37:21 PM PDT 24
Peak memory 195576 kb
Host smart-864a1ff5-5dc0-4e01-b8ba-4a4d34caa46b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379965585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2379965585
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4095456126
Short name T355
Test name
Test status
Simulation time 73425717 ps
CPU time 1.06 seconds
Started Jun 07 07:37:16 PM PDT 24
Finished Jun 07 07:37:18 PM PDT 24
Peak memory 196500 kb
Host smart-e484adeb-d77f-40c3-806c-215570921fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095456126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4095456126
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2808543121
Short name T387
Test name
Test status
Simulation time 28769574 ps
CPU time 0.73 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 194376 kb
Host smart-da24a24b-51dd-4b94-af78-b93b4f384eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808543121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2808543121
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1287028780
Short name T624
Test name
Test status
Simulation time 197299586 ps
CPU time 2.21 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:17 PM PDT 24
Peak memory 198100 kb
Host smart-a720d953-a914-4fdc-b53d-e46c68f543ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287028780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1287028780
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.653775884
Short name T385
Test name
Test status
Simulation time 376961481 ps
CPU time 2.55 seconds
Started Jun 07 07:37:11 PM PDT 24
Finished Jun 07 07:37:15 PM PDT 24
Peak memory 197356 kb
Host smart-fe884ca7-fae1-4430-b61b-4fa65cd6bcfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653775884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
653775884
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3730172286
Short name T452
Test name
Test status
Simulation time 74044302 ps
CPU time 1.36 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:17 PM PDT 24
Peak memory 197116 kb
Host smart-487c4606-4166-4dc1-a503-5c9c4eb610ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730172286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3730172286
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3650296893
Short name T686
Test name
Test status
Simulation time 176135314 ps
CPU time 0.82 seconds
Started Jun 07 07:37:13 PM PDT 24
Finished Jun 07 07:37:14 PM PDT 24
Peak memory 195592 kb
Host smart-78b67276-d7eb-4a30-9609-f97e72e9b707
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650296893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3650296893
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2216490553
Short name T679
Test name
Test status
Simulation time 2870614959 ps
CPU time 6.93 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:22 PM PDT 24
Peak memory 198136 kb
Host smart-b829d449-7aa8-4541-80c5-9c3406c0e3b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216490553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2216490553
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2054019076
Short name T52
Test name
Test status
Simulation time 78224561 ps
CPU time 1.28 seconds
Started Jun 07 07:37:31 PM PDT 24
Finished Jun 07 07:37:34 PM PDT 24
Peak memory 198004 kb
Host smart-c0a9eb74-c3e8-4ad9-82ff-715d0b907c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054019076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2054019076
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1032670558
Short name T297
Test name
Test status
Simulation time 50391195 ps
CPU time 1.39 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 198028 kb
Host smart-1d134799-cf74-4bf0-a3fb-2d08ed690505
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032670558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1032670558
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1814230831
Short name T7
Test name
Test status
Simulation time 5276799071 ps
CPU time 30.5 seconds
Started Jun 07 07:37:15 PM PDT 24
Finished Jun 07 07:37:47 PM PDT 24
Peak memory 198244 kb
Host smart-807e0608-4c95-46c9-a730-2055961c8ce2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814230831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1814230831
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2611274588
Short name T27
Test name
Test status
Simulation time 740043029641 ps
CPU time 1706.89 seconds
Started Jun 07 07:37:13 PM PDT 24
Finished Jun 07 08:05:41 PM PDT 24
Peak memory 198272 kb
Host smart-10bfbb9a-4198-4376-8074-20a987a15772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2611274588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2611274588
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2433150037
Short name T144
Test name
Test status
Simulation time 53780201 ps
CPU time 0.58 seconds
Started Jun 07 07:37:21 PM PDT 24
Finished Jun 07 07:37:24 PM PDT 24
Peak memory 194808 kb
Host smart-e04822c2-6dd2-4231-9a23-9e038dfee321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433150037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2433150037
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2895625055
Short name T282
Test name
Test status
Simulation time 51772962 ps
CPU time 0.94 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:22 PM PDT 24
Peak memory 196012 kb
Host smart-800ac78e-cef1-4a95-8c35-564d79c5cd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895625055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2895625055
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.731382958
Short name T151
Test name
Test status
Simulation time 7022597235 ps
CPU time 18.22 seconds
Started Jun 07 07:37:18 PM PDT 24
Finished Jun 07 07:37:37 PM PDT 24
Peak memory 198244 kb
Host smart-9b2ea66b-bac1-4ce0-8607-80b907f5e46c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731382958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.731382958
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.405684010
Short name T166
Test name
Test status
Simulation time 171396723 ps
CPU time 0.93 seconds
Started Jun 07 07:37:21 PM PDT 24
Finished Jun 07 07:37:24 PM PDT 24
Peak memory 197112 kb
Host smart-09ff7869-a566-4faa-bc17-49ae5f6d4fcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405684010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.405684010
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2594609418
Short name T224
Test name
Test status
Simulation time 1147471065 ps
CPU time 1.01 seconds
Started Jun 07 07:37:18 PM PDT 24
Finished Jun 07 07:37:20 PM PDT 24
Peak memory 195864 kb
Host smart-840f02ad-8490-494d-9794-98b38fcfb812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594609418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2594609418
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2445399667
Short name T529
Test name
Test status
Simulation time 121060787 ps
CPU time 1.36 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:23 PM PDT 24
Peak memory 196816 kb
Host smart-511422b8-1901-4822-ad9c-039c6dee5a25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445399667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2445399667
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.682116103
Short name T484
Test name
Test status
Simulation time 31503842 ps
CPU time 0.87 seconds
Started Jun 07 07:37:22 PM PDT 24
Finished Jun 07 07:37:25 PM PDT 24
Peak memory 194588 kb
Host smart-b107617d-1362-4a90-82e0-371988e6b16f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682116103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
682116103
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3912054735
Short name T648
Test name
Test status
Simulation time 295323216 ps
CPU time 1.07 seconds
Started Jun 07 07:37:19 PM PDT 24
Finished Jun 07 07:37:22 PM PDT 24
Peak memory 196112 kb
Host smart-f930c208-1ec6-4dd1-8f64-d521640410a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912054735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3912054735
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2585683865
Short name T423
Test name
Test status
Simulation time 148685564 ps
CPU time 0.87 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:22 PM PDT 24
Peak memory 196700 kb
Host smart-263a1ef6-3e12-43b8-898a-9e393ebc7c9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585683865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2585683865
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3550832377
Short name T448
Test name
Test status
Simulation time 126803202 ps
CPU time 2.85 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:25 PM PDT 24
Peak memory 198056 kb
Host smart-de317daa-ca13-4015-9d3c-e1d83d286487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550832377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3550832377
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1673264906
Short name T685
Test name
Test status
Simulation time 170546810 ps
CPU time 0.97 seconds
Started Jun 07 07:37:14 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 196288 kb
Host smart-019df7d6-3d86-4369-a3a2-044ee83781ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673264906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1673264906
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4062560651
Short name T432
Test name
Test status
Simulation time 56273088 ps
CPU time 1.03 seconds
Started Jun 07 07:37:21 PM PDT 24
Finished Jun 07 07:37:24 PM PDT 24
Peak memory 195628 kb
Host smart-24fed370-c294-4a60-951d-fe1f9f576ef9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062560651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4062560651
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.123580725
Short name T513
Test name
Test status
Simulation time 10316914800 ps
CPU time 122.99 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:39:25 PM PDT 24
Peak memory 198224 kb
Host smart-5dee7c2d-bd08-4e62-bff2-9135549196cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123580725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.123580725
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1074734555
Short name T63
Test name
Test status
Simulation time 108637554353 ps
CPU time 2451.83 seconds
Started Jun 07 07:37:22 PM PDT 24
Finished Jun 07 08:18:16 PM PDT 24
Peak memory 198360 kb
Host smart-d0a28f7d-5dd4-4cdd-b19e-50826aafb812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1074734555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1074734555
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2042758031
Short name T594
Test name
Test status
Simulation time 41165482 ps
CPU time 0.56 seconds
Started Jun 07 07:37:27 PM PDT 24
Finished Jun 07 07:37:29 PM PDT 24
Peak memory 193976 kb
Host smart-d8d380a6-30cf-4a69-a828-927b16969975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042758031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2042758031
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.398909015
Short name T213
Test name
Test status
Simulation time 88905435 ps
CPU time 1.03 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:23 PM PDT 24
Peak memory 195892 kb
Host smart-7ca22e4e-3620-4a0a-814f-f0924203d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398909015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.398909015
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4265884628
Short name T465
Test name
Test status
Simulation time 1790906727 ps
CPU time 19.22 seconds
Started Jun 07 07:37:27 PM PDT 24
Finished Jun 07 07:37:49 PM PDT 24
Peak memory 196880 kb
Host smart-b9d68c7e-91f1-435a-be61-9f284084a5a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265884628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4265884628
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.662244762
Short name T678
Test name
Test status
Simulation time 249277668 ps
CPU time 1.01 seconds
Started Jun 07 07:37:27 PM PDT 24
Finished Jun 07 07:37:31 PM PDT 24
Peak memory 198004 kb
Host smart-dadfd9cb-7e92-421d-84a9-ac087ec1fc58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662244762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.662244762
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4039367593
Short name T267
Test name
Test status
Simulation time 321725697 ps
CPU time 1.21 seconds
Started Jun 07 07:37:21 PM PDT 24
Finished Jun 07 07:37:24 PM PDT 24
Peak memory 196680 kb
Host smart-93c49df0-423e-45fa-9dd2-146526d24119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039367593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4039367593
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1691609409
Short name T265
Test name
Test status
Simulation time 338114122 ps
CPU time 3.57 seconds
Started Jun 07 07:37:27 PM PDT 24
Finished Jun 07 07:37:33 PM PDT 24
Peak memory 198160 kb
Host smart-eb4b8494-a380-4cbd-9afd-65a416448882
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691609409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1691609409
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.488249544
Short name T11
Test name
Test status
Simulation time 141688602 ps
CPU time 2.59 seconds
Started Jun 07 07:37:18 PM PDT 24
Finished Jun 07 07:37:22 PM PDT 24
Peak memory 198136 kb
Host smart-aef2c8f4-4c7c-47f3-9dcc-9f158c25cbef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488249544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
488249544
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4159390519
Short name T527
Test name
Test status
Simulation time 74371712 ps
CPU time 0.83 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:23 PM PDT 24
Peak memory 196772 kb
Host smart-92afc83d-e152-44a6-8e72-1c78a956a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159390519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4159390519
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.712063811
Short name T362
Test name
Test status
Simulation time 18365861 ps
CPU time 0.68 seconds
Started Jun 07 07:37:19 PM PDT 24
Finished Jun 07 07:37:21 PM PDT 24
Peak memory 195060 kb
Host smart-0803612b-02d5-43aa-a82a-96a3a03f4db9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712063811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.712063811
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2800672765
Short name T535
Test name
Test status
Simulation time 368139536 ps
CPU time 4.39 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:37:36 PM PDT 24
Peak memory 198020 kb
Host smart-668825be-4ca9-4c46-969e-d55c74cc7060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800672765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2800672765
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2577081295
Short name T533
Test name
Test status
Simulation time 171021534 ps
CPU time 1.09 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:23 PM PDT 24
Peak memory 195684 kb
Host smart-6ba48a9d-e911-4805-a8f6-2d6294bcbaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577081295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2577081295
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.580668073
Short name T149
Test name
Test status
Simulation time 349098794 ps
CPU time 1.51 seconds
Started Jun 07 07:37:20 PM PDT 24
Finished Jun 07 07:37:24 PM PDT 24
Peak memory 196884 kb
Host smart-e3a85257-fd9e-42c3-8919-78975bf14c51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580668073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.580668073
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.332320815
Short name T485
Test name
Test status
Simulation time 154364176697 ps
CPU time 157.62 seconds
Started Jun 07 07:37:32 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 198200 kb
Host smart-5d93d694-67b8-4d30-b46d-1e281b78353b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332320815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.332320815
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3166316935
Short name T561
Test name
Test status
Simulation time 367385003654 ps
CPU time 643.11 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:48:16 PM PDT 24
Peak memory 198320 kb
Host smart-0366d9ae-3aca-4ce2-9ad2-fb5cc7656c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3166316935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3166316935
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.596958739
Short name T315
Test name
Test status
Simulation time 14595692 ps
CPU time 0.56 seconds
Started Jun 07 07:35:31 PM PDT 24
Finished Jun 07 07:35:32 PM PDT 24
Peak memory 194664 kb
Host smart-90e19d09-c9ae-4fec-a9bb-7a4495c52cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596958739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.596958739
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3248342319
Short name T424
Test name
Test status
Simulation time 56279864 ps
CPU time 0.89 seconds
Started Jun 07 07:35:34 PM PDT 24
Finished Jun 07 07:35:37 PM PDT 24
Peak memory 196088 kb
Host smart-b63b85d2-6fb2-42f1-a7bd-8fc9f206eab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248342319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3248342319
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3080140937
Short name T272
Test name
Test status
Simulation time 1049828275 ps
CPU time 15.51 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:35:51 PM PDT 24
Peak memory 198032 kb
Host smart-23663c89-f59a-478c-8a3f-1d4f70796714
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080140937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3080140937
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.223649688
Short name T482
Test name
Test status
Simulation time 34074782 ps
CPU time 0.75 seconds
Started Jun 07 07:35:32 PM PDT 24
Finished Jun 07 07:35:34 PM PDT 24
Peak memory 195912 kb
Host smart-637032f9-8642-44d1-b0fd-3d048c6358c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223649688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.223649688
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3179456593
Short name T663
Test name
Test status
Simulation time 115747979 ps
CPU time 1.46 seconds
Started Jun 07 07:35:32 PM PDT 24
Finished Jun 07 07:35:34 PM PDT 24
Peak memory 196864 kb
Host smart-0860f31a-ee5b-4783-a665-5bd23c4258d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179456593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3179456593
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1353191114
Short name T270
Test name
Test status
Simulation time 80818371 ps
CPU time 2.29 seconds
Started Jun 07 07:35:32 PM PDT 24
Finished Jun 07 07:35:35 PM PDT 24
Peak memory 196388 kb
Host smart-d1aaa529-c0e3-4e8c-afae-d121d67f98cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353191114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1353191114
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3434321979
Short name T441
Test name
Test status
Simulation time 123307509 ps
CPU time 2.45 seconds
Started Jun 07 07:35:34 PM PDT 24
Finished Jun 07 07:35:38 PM PDT 24
Peak memory 197144 kb
Host smart-baf5dfb6-a2b4-4ec1-aba1-6859588d58d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434321979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3434321979
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.699302275
Short name T633
Test name
Test status
Simulation time 105643198 ps
CPU time 1.24 seconds
Started Jun 07 07:35:35 PM PDT 24
Finished Jun 07 07:35:38 PM PDT 24
Peak memory 197156 kb
Host smart-e1f9bcee-27f4-40e2-951c-415ecdf9112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699302275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.699302275
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2366277804
Short name T427
Test name
Test status
Simulation time 133562343 ps
CPU time 0.96 seconds
Started Jun 07 07:35:36 PM PDT 24
Finished Jun 07 07:35:39 PM PDT 24
Peak memory 196092 kb
Host smart-f42eedc9-e8c7-407f-ab52-ab3acb92d4f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366277804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2366277804
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2461757461
Short name T227
Test name
Test status
Simulation time 353384987 ps
CPU time 1.88 seconds
Started Jun 07 07:35:35 PM PDT 24
Finished Jun 07 07:35:39 PM PDT 24
Peak memory 198012 kb
Host smart-f55c262e-186f-4d26-83d8-a6e1380bc22a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461757461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2461757461
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.299723601
Short name T34
Test name
Test status
Simulation time 290189893 ps
CPU time 0.86 seconds
Started Jun 07 07:35:32 PM PDT 24
Finished Jun 07 07:35:34 PM PDT 24
Peak memory 213968 kb
Host smart-252a53c3-9949-413d-b5d6-9cdaa5aa499e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299723601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.299723601
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.678618252
Short name T595
Test name
Test status
Simulation time 50945098 ps
CPU time 1.39 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:35:36 PM PDT 24
Peak memory 198052 kb
Host smart-d69dde58-6caf-4868-b359-3f421133214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678618252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.678618252
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3115431006
Short name T148
Test name
Test status
Simulation time 692075805 ps
CPU time 1.33 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:35:36 PM PDT 24
Peak memory 196920 kb
Host smart-ca7182c7-6ed6-4f4e-865c-5dcf1e09a94e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115431006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3115431006
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1204276764
Short name T354
Test name
Test status
Simulation time 12502805517 ps
CPU time 168.61 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:38:24 PM PDT 24
Peak memory 198268 kb
Host smart-ccd712f6-c2e6-4429-965a-fd8883cb57fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204276764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1204276764
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1126299590
Short name T472
Test name
Test status
Simulation time 49402818858 ps
CPU time 1621.27 seconds
Started Jun 07 07:35:37 PM PDT 24
Finished Jun 07 08:02:40 PM PDT 24
Peak memory 198304 kb
Host smart-3e4e86d6-6db2-4872-ab60-6920d4e2dc02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1126299590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1126299590
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3893332344
Short name T631
Test name
Test status
Simulation time 46895460 ps
CPU time 0.57 seconds
Started Jun 07 07:37:42 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 193956 kb
Host smart-260af1cf-6152-4d0a-ae95-83ba44841bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893332344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3893332344
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.994718643
Short name T351
Test name
Test status
Simulation time 26598969 ps
CPU time 0.77 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:37:32 PM PDT 24
Peak memory 196068 kb
Host smart-2b418536-d159-4040-b54a-efa3c7f4360c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994718643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.994718643
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.674646445
Short name T308
Test name
Test status
Simulation time 155754590 ps
CPU time 7.67 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:37:40 PM PDT 24
Peak memory 196324 kb
Host smart-f0f72305-0702-420e-953c-fdbb88a02707
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674646445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.674646445
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.112028884
Short name T304
Test name
Test status
Simulation time 81759678 ps
CPU time 0.96 seconds
Started Jun 07 07:37:41 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 196392 kb
Host smart-532ac483-50e9-44bc-9eb2-7e026b68c10c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112028884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.112028884
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1207671740
Short name T523
Test name
Test status
Simulation time 103656497 ps
CPU time 1.26 seconds
Started Jun 07 07:37:28 PM PDT 24
Finished Jun 07 07:37:32 PM PDT 24
Peak memory 197148 kb
Host smart-bb012c82-534d-42fa-aa05-a6443b0914fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207671740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1207671740
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1685563664
Short name T537
Test name
Test status
Simulation time 326976763 ps
CPU time 3.44 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:37:36 PM PDT 24
Peak memory 198092 kb
Host smart-7b0ae011-92c7-448d-a550-b61226bacc64
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685563664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1685563664
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.502946876
Short name T112
Test name
Test status
Simulation time 309235225 ps
CPU time 2.01 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:37:34 PM PDT 24
Peak memory 196844 kb
Host smart-cd66f9d0-1ee5-4bcc-b70d-220e4d8dd4db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502946876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
502946876
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3687791006
Short name T185
Test name
Test status
Simulation time 39516636 ps
CPU time 0.75 seconds
Started Jun 07 07:37:27 PM PDT 24
Finished Jun 07 07:37:30 PM PDT 24
Peak memory 195440 kb
Host smart-909a49c0-c2d7-4f67-8ab6-7d15133350fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687791006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3687791006
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2824445386
Short name T16
Test name
Test status
Simulation time 113141944 ps
CPU time 1.28 seconds
Started Jun 07 07:37:29 PM PDT 24
Finished Jun 07 07:37:33 PM PDT 24
Peak memory 198060 kb
Host smart-37f44465-9f28-4bfd-9ef9-4a60ea9c1a7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824445386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2824445386
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.856810919
Short name T402
Test name
Test status
Simulation time 2077210949 ps
CPU time 3.65 seconds
Started Jun 07 07:37:40 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 198028 kb
Host smart-7265105b-2764-472d-b57b-c70646d7727e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856810919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.856810919
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1383492832
Short name T615
Test name
Test status
Simulation time 120478910 ps
CPU time 0.81 seconds
Started Jun 07 07:37:28 PM PDT 24
Finished Jun 07 07:37:32 PM PDT 24
Peak memory 196036 kb
Host smart-092ec7ad-4980-433a-9e8d-884b3ea9abe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383492832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1383492832
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2790807204
Short name T324
Test name
Test status
Simulation time 72243002 ps
CPU time 1.25 seconds
Started Jun 07 07:37:28 PM PDT 24
Finished Jun 07 07:37:32 PM PDT 24
Peak memory 196424 kb
Host smart-96efeee0-8ffa-44b4-8c31-24c8432a6615
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790807204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2790807204
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3965852379
Short name T384
Test name
Test status
Simulation time 21963027224 ps
CPU time 139.41 seconds
Started Jun 07 07:37:42 PM PDT 24
Finished Jun 07 07:40:05 PM PDT 24
Peak memory 198288 kb
Host smart-285c7322-a876-4438-a024-9065df09d2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965852379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3965852379
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2563561012
Short name T650
Test name
Test status
Simulation time 49730540092 ps
CPU time 448.99 seconds
Started Jun 07 07:37:41 PM PDT 24
Finished Jun 07 07:45:13 PM PDT 24
Peak memory 198324 kb
Host smart-f8e9b0a4-2dec-4ecb-893b-03cc5ebec2dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2563561012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2563561012
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1871741680
Short name T636
Test name
Test status
Simulation time 19967527 ps
CPU time 0.57 seconds
Started Jun 07 07:37:56 PM PDT 24
Finished Jun 07 07:37:59 PM PDT 24
Peak memory 194688 kb
Host smart-c645dcce-46b6-48e6-9007-64eaf8384393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871741680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1871741680
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1401112269
Short name T440
Test name
Test status
Simulation time 179383878 ps
CPU time 0.8 seconds
Started Jun 07 07:37:42 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 195496 kb
Host smart-904bcc8d-5631-494e-a3d6-dd15427c8c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401112269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1401112269
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1798020351
Short name T496
Test name
Test status
Simulation time 994109990 ps
CPU time 13.06 seconds
Started Jun 07 07:37:41 PM PDT 24
Finished Jun 07 07:37:58 PM PDT 24
Peak memory 196916 kb
Host smart-73cde4fe-81c1-43da-b8f5-ee1c6167cd02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798020351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1798020351
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2505357435
Short name T724
Test name
Test status
Simulation time 87405524 ps
CPU time 1.06 seconds
Started Jun 07 07:37:41 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 197980 kb
Host smart-8339e064-1c5c-4279-8691-5ad7462d037b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505357435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2505357435
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1474686121
Short name T343
Test name
Test status
Simulation time 197883151 ps
CPU time 0.96 seconds
Started Jun 07 07:37:41 PM PDT 24
Finished Jun 07 07:37:45 PM PDT 24
Peak memory 196616 kb
Host smart-2daef75b-ed26-471f-9309-fe99ab2e769f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474686121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1474686121
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4074688428
Short name T344
Test name
Test status
Simulation time 78907414 ps
CPU time 3.19 seconds
Started Jun 07 07:37:42 PM PDT 24
Finished Jun 07 07:37:49 PM PDT 24
Peak memory 198084 kb
Host smart-d298a7c6-013f-4e39-9c59-879222408442
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074688428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4074688428
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2842712206
Short name T220
Test name
Test status
Simulation time 1196439342 ps
CPU time 3.5 seconds
Started Jun 07 07:37:42 PM PDT 24
Finished Jun 07 07:37:49 PM PDT 24
Peak memory 195704 kb
Host smart-0d219d53-309f-42c7-a276-b5a9bdd7f4c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842712206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2842712206
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2509866580
Short name T311
Test name
Test status
Simulation time 16603137 ps
CPU time 0.68 seconds
Started Jun 07 07:37:38 PM PDT 24
Finished Jun 07 07:37:41 PM PDT 24
Peak memory 194368 kb
Host smart-5314e6ca-340e-4ae3-91cb-54527c67187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509866580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2509866580
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3539046788
Short name T248
Test name
Test status
Simulation time 128972792 ps
CPU time 1.2 seconds
Started Jun 07 07:37:40 PM PDT 24
Finished Jun 07 07:37:44 PM PDT 24
Peak memory 196540 kb
Host smart-fe2e5849-f9c5-4e76-b1fd-989e1700276d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539046788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3539046788
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4092786431
Short name T196
Test name
Test status
Simulation time 305522115 ps
CPU time 2.97 seconds
Started Jun 07 07:37:39 PM PDT 24
Finished Jun 07 07:37:45 PM PDT 24
Peak memory 198052 kb
Host smart-2d60be01-06b6-42c8-b388-7558e0d450e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092786431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4092786431
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3862181675
Short name T244
Test name
Test status
Simulation time 68950266 ps
CPU time 1.09 seconds
Started Jun 07 07:37:42 PM PDT 24
Finished Jun 07 07:37:47 PM PDT 24
Peak memory 196448 kb
Host smart-9f7551d3-0da3-4939-a9d4-2275f98b5924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862181675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3862181675
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1973768224
Short name T238
Test name
Test status
Simulation time 31737647 ps
CPU time 0.99 seconds
Started Jun 07 07:37:40 PM PDT 24
Finished Jun 07 07:37:43 PM PDT 24
Peak memory 195828 kb
Host smart-d82020ba-2c14-405d-8fa2-cbd4cd8adc31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973768224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1973768224
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3951617452
Short name T582
Test name
Test status
Simulation time 4108145510 ps
CPU time 96.2 seconds
Started Jun 07 07:37:37 PM PDT 24
Finished Jun 07 07:39:16 PM PDT 24
Peak memory 198292 kb
Host smart-3e08dca4-e874-4df8-87cd-bbd700dbc38f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951617452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3951617452
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3075861405
Short name T516
Test name
Test status
Simulation time 20199352 ps
CPU time 0.56 seconds
Started Jun 07 07:37:50 PM PDT 24
Finished Jun 07 07:37:52 PM PDT 24
Peak memory 193984 kb
Host smart-f9e393d5-93c0-4254-9d72-89b52f094857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075861405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3075861405
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.289935112
Short name T358
Test name
Test status
Simulation time 89659527 ps
CPU time 0.73 seconds
Started Jun 07 07:37:54 PM PDT 24
Finished Jun 07 07:37:58 PM PDT 24
Peak memory 194248 kb
Host smart-c83979ce-d644-4817-8003-8da8a12457fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289935112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.289935112
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3778053601
Short name T421
Test name
Test status
Simulation time 182985659 ps
CPU time 4.36 seconds
Started Jun 07 07:37:50 PM PDT 24
Finished Jun 07 07:37:57 PM PDT 24
Peak memory 196608 kb
Host smart-b65dc5b1-917a-4b86-b81e-9cf9cf7a7595
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778053601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3778053601
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3419491953
Short name T4
Test name
Test status
Simulation time 136774464 ps
CPU time 0.9 seconds
Started Jun 07 07:37:52 PM PDT 24
Finished Jun 07 07:37:55 PM PDT 24
Peak memory 196156 kb
Host smart-6cec7f56-63c6-43de-9fb4-3b957ba6e340
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419491953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3419491953
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.513698077
Short name T269
Test name
Test status
Simulation time 147813087 ps
CPU time 1.48 seconds
Started Jun 07 07:37:55 PM PDT 24
Finished Jun 07 07:37:59 PM PDT 24
Peak memory 197212 kb
Host smart-44886e95-7044-483c-9c35-ea79aca2a4f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513698077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.513698077
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1073739790
Short name T71
Test name
Test status
Simulation time 263625598 ps
CPU time 2.95 seconds
Started Jun 07 07:37:58 PM PDT 24
Finished Jun 07 07:38:04 PM PDT 24
Peak memory 198132 kb
Host smart-6e49952e-eef7-4189-92de-6c1cf50bb55a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073739790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1073739790
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2549247444
Short name T711
Test name
Test status
Simulation time 141396815 ps
CPU time 2.99 seconds
Started Jun 07 07:37:50 PM PDT 24
Finished Jun 07 07:37:54 PM PDT 24
Peak memory 197160 kb
Host smart-9b847b7f-f4fa-4f6b-961d-cadef01883a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549247444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2549247444
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.960400247
Short name T585
Test name
Test status
Simulation time 78531587 ps
CPU time 0.93 seconds
Started Jun 07 07:37:57 PM PDT 24
Finished Jun 07 07:38:01 PM PDT 24
Peak memory 195868 kb
Host smart-905cd035-968a-49f3-825d-e3e41a10a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960400247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.960400247
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.398707720
Short name T382
Test name
Test status
Simulation time 33283189 ps
CPU time 0.82 seconds
Started Jun 07 07:37:54 PM PDT 24
Finished Jun 07 07:37:57 PM PDT 24
Peak memory 196340 kb
Host smart-9cc38f42-d1f9-4306-9ae3-8e73a873d6a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398707720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.398707720
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2020145571
Short name T684
Test name
Test status
Simulation time 269020241 ps
CPU time 4.34 seconds
Started Jun 07 07:37:54 PM PDT 24
Finished Jun 07 07:38:00 PM PDT 24
Peak memory 198052 kb
Host smart-70436876-1c26-441c-9f60-e8957d320d07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020145571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2020145571
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2007397760
Short name T467
Test name
Test status
Simulation time 90196151 ps
CPU time 0.97 seconds
Started Jun 07 07:37:51 PM PDT 24
Finished Jun 07 07:37:54 PM PDT 24
Peak memory 195864 kb
Host smart-abf4a60c-133e-4bea-820b-bfb67c73dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007397760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2007397760
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2194754170
Short name T445
Test name
Test status
Simulation time 46258716 ps
CPU time 1.39 seconds
Started Jun 07 07:37:54 PM PDT 24
Finished Jun 07 07:37:58 PM PDT 24
Peak memory 195804 kb
Host smart-03c71124-ddc1-41c7-a9f5-0a92eb85d6ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194754170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2194754170
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2980626316
Short name T399
Test name
Test status
Simulation time 46885330851 ps
CPU time 161.53 seconds
Started Jun 07 07:37:54 PM PDT 24
Finished Jun 07 07:40:39 PM PDT 24
Peak memory 198228 kb
Host smart-cac23419-65b5-489f-9883-dfddd50864e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980626316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2980626316
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.4176771210
Short name T635
Test name
Test status
Simulation time 118305298366 ps
CPU time 1667.86 seconds
Started Jun 07 07:37:56 PM PDT 24
Finished Jun 07 08:05:47 PM PDT 24
Peak memory 198300 kb
Host smart-9c3fc629-270b-4b29-b348-1c28d701e32c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4176771210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.4176771210
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2140092280
Short name T35
Test name
Test status
Simulation time 25048332 ps
CPU time 0.56 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 193964 kb
Host smart-23c3e4ae-4d45-419c-8bfc-b47511aa96b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140092280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2140092280
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1670028492
Short name T162
Test name
Test status
Simulation time 40556909 ps
CPU time 0.93 seconds
Started Jun 07 07:37:53 PM PDT 24
Finished Jun 07 07:37:57 PM PDT 24
Peak memory 197336 kb
Host smart-cc80ef8a-d6e1-4267-b4f8-5bcd488f9d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670028492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1670028492
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2122346452
Short name T276
Test name
Test status
Simulation time 4876740676 ps
CPU time 9.63 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:13 PM PDT 24
Peak memory 198136 kb
Host smart-225da92c-c3ff-447a-9548-e81f3f8ecb3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122346452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2122346452
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1413387004
Short name T554
Test name
Test status
Simulation time 24546411 ps
CPU time 0.64 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 194544 kb
Host smart-eadd63b3-43d9-4c89-9784-f547ba8f9b95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413387004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1413387004
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4015829698
Short name T396
Test name
Test status
Simulation time 64733402 ps
CPU time 1.11 seconds
Started Jun 07 07:37:52 PM PDT 24
Finished Jun 07 07:37:56 PM PDT 24
Peak memory 196188 kb
Host smart-c5747fdf-3d90-46df-80a5-49c533fd5011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015829698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4015829698
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2168733490
Short name T416
Test name
Test status
Simulation time 262054484 ps
CPU time 2.45 seconds
Started Jun 07 07:37:58 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 198096 kb
Host smart-61cb6b04-1522-4670-bd6b-7b498c9e7c55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168733490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2168733490
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3703750763
Short name T530
Test name
Test status
Simulation time 1317870528 ps
CPU time 3.08 seconds
Started Jun 07 07:37:56 PM PDT 24
Finished Jun 07 07:38:02 PM PDT 24
Peak memory 197232 kb
Host smart-0a8bd9a7-6567-4192-9d86-700054361588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703750763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3703750763
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3499706392
Short name T587
Test name
Test status
Simulation time 247646040 ps
CPU time 0.89 seconds
Started Jun 07 07:37:53 PM PDT 24
Finished Jun 07 07:37:55 PM PDT 24
Peak memory 196016 kb
Host smart-3ed4efd3-7412-4218-be6d-6a2e7805fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499706392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3499706392
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3414331145
Short name T505
Test name
Test status
Simulation time 63147562 ps
CPU time 0.83 seconds
Started Jun 07 07:37:59 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 195472 kb
Host smart-f4a9e9ed-ba74-4066-ad25-a8216f51cf6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414331145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3414331145
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3049161299
Short name T607
Test name
Test status
Simulation time 100704882 ps
CPU time 2.41 seconds
Started Jun 07 07:38:01 PM PDT 24
Finished Jun 07 07:38:07 PM PDT 24
Peak memory 198016 kb
Host smart-4e2e6d72-8e65-427a-bdb4-9b6759791ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049161299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3049161299
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.412517042
Short name T488
Test name
Test status
Simulation time 36280913 ps
CPU time 0.89 seconds
Started Jun 07 07:37:59 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 195484 kb
Host smart-465ddf6d-0cb0-4e1b-973b-1d52726d64a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412517042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.412517042
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2467928941
Short name T371
Test name
Test status
Simulation time 41164911 ps
CPU time 1.19 seconds
Started Jun 07 07:37:53 PM PDT 24
Finished Jun 07 07:37:57 PM PDT 24
Peak memory 196564 kb
Host smart-2ae3895e-93b5-492e-8592-91d0a57c70be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467928941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2467928941
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2858740227
Short name T125
Test name
Test status
Simulation time 7369415623 ps
CPU time 30.43 seconds
Started Jun 07 07:38:01 PM PDT 24
Finished Jun 07 07:38:34 PM PDT 24
Peak memory 198236 kb
Host smart-6ec5ed75-42b0-4959-a3de-47c829d3f1a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858740227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2858740227
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3673954546
Short name T58
Test name
Test status
Simulation time 233212489954 ps
CPU time 537.03 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:47:00 PM PDT 24
Peak memory 206440 kb
Host smart-8f574442-b406-4d1e-84ea-b694a2642337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3673954546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3673954546
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1030192641
Short name T380
Test name
Test status
Simulation time 36114638 ps
CPU time 0.57 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 193920 kb
Host smart-10a1cea9-01d4-4022-9441-93f1b38e3847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030192641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1030192641
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1635010016
Short name T630
Test name
Test status
Simulation time 41952326 ps
CPU time 0.83 seconds
Started Jun 07 07:37:59 PM PDT 24
Finished Jun 07 07:38:03 PM PDT 24
Peak memory 195324 kb
Host smart-0d6b4ccb-773e-41a7-a6d9-0c7cc83ba2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635010016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1635010016
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3672486123
Short name T160
Test name
Test status
Simulation time 1596359470 ps
CPU time 26.78 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:29 PM PDT 24
Peak memory 196852 kb
Host smart-2c75fa21-6c85-41e3-b840-77eaa04fbfb1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672486123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3672486123
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1279732377
Short name T19
Test name
Test status
Simulation time 54428994 ps
CPU time 0.91 seconds
Started Jun 07 07:38:01 PM PDT 24
Finished Jun 07 07:38:04 PM PDT 24
Peak memory 196976 kb
Host smart-f2882de7-eacd-40ae-9ab8-679e8b83df13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279732377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1279732377
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2182605558
Short name T591
Test name
Test status
Simulation time 65740539 ps
CPU time 0.71 seconds
Started Jun 07 07:38:05 PM PDT 24
Finished Jun 07 07:38:07 PM PDT 24
Peak memory 195568 kb
Host smart-1eda120c-0d1a-403b-b17e-d9b962a26b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182605558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2182605558
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.405175345
Short name T563
Test name
Test status
Simulation time 68896961 ps
CPU time 2.68 seconds
Started Jun 07 07:38:04 PM PDT 24
Finished Jun 07 07:38:09 PM PDT 24
Peak memory 198072 kb
Host smart-5d963a92-2092-46fc-a42d-df419365e0f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405175345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.405175345
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.148667057
Short name T463
Test name
Test status
Simulation time 178183831 ps
CPU time 2.19 seconds
Started Jun 07 07:37:59 PM PDT 24
Finished Jun 07 07:38:04 PM PDT 24
Peak memory 198148 kb
Host smart-9fbd00d2-1885-4f6d-a822-2b39aa24698d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148667057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
148667057
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2479506298
Short name T250
Test name
Test status
Simulation time 51104921 ps
CPU time 1.27 seconds
Started Jun 07 07:38:02 PM PDT 24
Finished Jun 07 07:38:06 PM PDT 24
Peak memory 196192 kb
Host smart-c54f89e5-4cd8-4622-9ddb-68db50ad2259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479506298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2479506298
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.870973321
Short name T510
Test name
Test status
Simulation time 63109217 ps
CPU time 1.42 seconds
Started Jun 07 07:38:01 PM PDT 24
Finished Jun 07 07:38:05 PM PDT 24
Peak memory 195860 kb
Host smart-696e120b-bf94-4752-8820-647fc3dc6b4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870973321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.870973321
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2382503591
Short name T430
Test name
Test status
Simulation time 1825231720 ps
CPU time 5.64 seconds
Started Jun 07 07:37:59 PM PDT 24
Finished Jun 07 07:38:07 PM PDT 24
Peak memory 198084 kb
Host smart-3e539031-3921-4535-9b3f-be65e5249eed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382503591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2382503591
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4114649228
Short name T264
Test name
Test status
Simulation time 205181956 ps
CPU time 1.31 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:04 PM PDT 24
Peak memory 196272 kb
Host smart-2b3971a2-222d-4181-92b6-bcd3bb04acff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114649228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4114649228
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1801549978
Short name T590
Test name
Test status
Simulation time 125038134 ps
CPU time 1.27 seconds
Started Jun 07 07:38:00 PM PDT 24
Finished Jun 07 07:38:05 PM PDT 24
Peak memory 196828 kb
Host smart-5fcff3dd-8314-4787-a14a-77119d191039
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801549978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1801549978
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3590118285
Short name T534
Test name
Test status
Simulation time 78570781974 ps
CPU time 142.41 seconds
Started Jun 07 07:38:08 PM PDT 24
Finished Jun 07 07:40:33 PM PDT 24
Peak memory 198208 kb
Host smart-c0129e10-91d0-4c2e-92b7-b91fd6388a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590118285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3590118285
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2974261885
Short name T632
Test name
Test status
Simulation time 28869481478 ps
CPU time 743.28 seconds
Started Jun 07 07:38:01 PM PDT 24
Finished Jun 07 07:50:27 PM PDT 24
Peak memory 198240 kb
Host smart-f101d7ef-e72d-4bf9-ba95-71a5c7fcafa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2974261885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2974261885
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2010839351
Short name T193
Test name
Test status
Simulation time 59768473 ps
CPU time 0.56 seconds
Started Jun 07 07:38:12 PM PDT 24
Finished Jun 07 07:38:16 PM PDT 24
Peak memory 193944 kb
Host smart-e16b9ed2-20af-4d88-a1bd-3e6449db2cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010839351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2010839351
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3168005926
Short name T687
Test name
Test status
Simulation time 27798389 ps
CPU time 0.92 seconds
Started Jun 07 07:38:11 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 196436 kb
Host smart-35c67a3e-a33e-435f-8a81-f0a5327b570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168005926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3168005926
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.284095635
Short name T214
Test name
Test status
Simulation time 6118720782 ps
CPU time 28.07 seconds
Started Jun 07 07:38:09 PM PDT 24
Finished Jun 07 07:38:40 PM PDT 24
Peak memory 198216 kb
Host smart-ead31192-6395-4f83-bd07-59e14038d778
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284095635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.284095635
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4196912328
Short name T553
Test name
Test status
Simulation time 287027213 ps
CPU time 0.99 seconds
Started Jun 07 07:38:09 PM PDT 24
Finished Jun 07 07:38:13 PM PDT 24
Peak memory 196660 kb
Host smart-be13bb19-fafa-4a3f-8c93-e84c9c3a8902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196912328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4196912328
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1566825060
Short name T75
Test name
Test status
Simulation time 396892210 ps
CPU time 1.38 seconds
Started Jun 07 07:38:15 PM PDT 24
Finished Jun 07 07:38:19 PM PDT 24
Peak memory 197288 kb
Host smart-b1ec0480-73dc-41ec-838c-44e95f123e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566825060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1566825060
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.958266929
Short name T370
Test name
Test status
Simulation time 90161962 ps
CPU time 2.81 seconds
Started Jun 07 07:38:09 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 196344 kb
Host smart-56b83c50-df99-409a-ab6f-6369935480ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958266929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.958266929
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.512091623
Short name T293
Test name
Test status
Simulation time 185726839 ps
CPU time 3.44 seconds
Started Jun 07 07:38:11 PM PDT 24
Finished Jun 07 07:38:18 PM PDT 24
Peak memory 197016 kb
Host smart-9065bc17-adec-45ad-8fbe-cf24962ea68e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512091623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
512091623
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1589276046
Short name T710
Test name
Test status
Simulation time 107623992 ps
CPU time 0.96 seconds
Started Jun 07 07:38:11 PM PDT 24
Finished Jun 07 07:38:15 PM PDT 24
Peak memory 196048 kb
Host smart-51e627c8-a516-470f-a205-9dc7d8965229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589276046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1589276046
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1012474997
Short name T17
Test name
Test status
Simulation time 45400157 ps
CPU time 1.13 seconds
Started Jun 07 07:38:10 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 196104 kb
Host smart-c29d5978-dc07-4380-9eba-35e97177c605
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012474997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1012474997
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_smoke.676014130
Short name T468
Test name
Test status
Simulation time 69008666 ps
CPU time 0.86 seconds
Started Jun 07 07:38:17 PM PDT 24
Finished Jun 07 07:38:20 PM PDT 24
Peak memory 195216 kb
Host smart-b13e7d73-bdba-4444-ac76-d7c93fbdc134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676014130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.676014130
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2606423310
Short name T696
Test name
Test status
Simulation time 122366777 ps
CPU time 0.83 seconds
Started Jun 07 07:38:12 PM PDT 24
Finished Jun 07 07:38:16 PM PDT 24
Peak memory 195436 kb
Host smart-c728f5a9-223c-4d56-987a-cfb0a32adad0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606423310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2606423310
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1779427770
Short name T469
Test name
Test status
Simulation time 10281799581 ps
CPU time 141.95 seconds
Started Jun 07 07:38:15 PM PDT 24
Finished Jun 07 07:40:40 PM PDT 24
Peak memory 198192 kb
Host smart-7cbe2956-0239-407f-a993-ba2779fc9ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779427770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1779427770
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.4113680405
Short name T338
Test name
Test status
Simulation time 80174862209 ps
CPU time 675.25 seconds
Started Jun 07 07:38:09 PM PDT 24
Finished Jun 07 07:49:27 PM PDT 24
Peak memory 198296 kb
Host smart-b3936201-272f-418f-a18d-4b8e919fd7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4113680405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.4113680405
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3801992509
Short name T694
Test name
Test status
Simulation time 14796862 ps
CPU time 0.57 seconds
Started Jun 07 07:38:18 PM PDT 24
Finished Jun 07 07:38:22 PM PDT 24
Peak memory 194668 kb
Host smart-c06369e2-3dbc-4a9f-a795-945454c99d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801992509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3801992509
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1654666241
Short name T658
Test name
Test status
Simulation time 126715442 ps
CPU time 0.88 seconds
Started Jun 07 07:38:10 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 196028 kb
Host smart-19a5a899-6b0b-44fc-8003-8cfa7e42a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654666241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1654666241
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3306540210
Short name T161
Test name
Test status
Simulation time 2297196673 ps
CPU time 15.31 seconds
Started Jun 07 07:38:10 PM PDT 24
Finished Jun 07 07:38:28 PM PDT 24
Peak memory 197096 kb
Host smart-18916eee-e001-44c5-975b-ae956587ba53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306540210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3306540210
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4028694778
Short name T346
Test name
Test status
Simulation time 137236726 ps
CPU time 0.78 seconds
Started Jun 07 07:38:10 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 196656 kb
Host smart-75a71894-de4a-4494-9ade-e487588dc769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028694778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4028694778
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3376583680
Short name T436
Test name
Test status
Simulation time 35441751 ps
CPU time 0.69 seconds
Started Jun 07 07:38:08 PM PDT 24
Finished Jun 07 07:38:11 PM PDT 24
Peak memory 194468 kb
Host smart-7d120b76-48b3-4b96-ac41-1ce06415c614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376583680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3376583680
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1254244968
Short name T164
Test name
Test status
Simulation time 42364463 ps
CPU time 1.7 seconds
Started Jun 07 07:38:08 PM PDT 24
Finished Jun 07 07:38:12 PM PDT 24
Peak memory 197316 kb
Host smart-fa6a4027-366e-4f46-bb6a-638b6f041248
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254244968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1254244968
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2614860798
Short name T320
Test name
Test status
Simulation time 40015146 ps
CPU time 0.98 seconds
Started Jun 07 07:38:09 PM PDT 24
Finished Jun 07 07:38:13 PM PDT 24
Peak memory 196348 kb
Host smart-4875c109-e68b-4eeb-8c55-55444d978da5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614860798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2614860798
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4073567085
Short name T218
Test name
Test status
Simulation time 58816868 ps
CPU time 0.74 seconds
Started Jun 07 07:38:13 PM PDT 24
Finished Jun 07 07:38:17 PM PDT 24
Peak memory 196120 kb
Host smart-3019e051-d49c-4fcf-bdf4-70b4c5ddca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073567085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4073567085
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4168019559
Short name T426
Test name
Test status
Simulation time 121005688 ps
CPU time 1.21 seconds
Started Jun 07 07:38:08 PM PDT 24
Finished Jun 07 07:38:12 PM PDT 24
Peak memory 198148 kb
Host smart-5080bea9-1a75-4852-a527-2b7b737e8eb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168019559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4168019559
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3702286495
Short name T610
Test name
Test status
Simulation time 1416094759 ps
CPU time 5.38 seconds
Started Jun 07 07:38:17 PM PDT 24
Finished Jun 07 07:38:25 PM PDT 24
Peak memory 197776 kb
Host smart-9c485e8f-927f-43f0-90aa-328b278f1c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702286495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3702286495
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.317920625
Short name T23
Test name
Test status
Simulation time 238861128 ps
CPU time 1.17 seconds
Started Jun 07 07:38:09 PM PDT 24
Finished Jun 07 07:38:13 PM PDT 24
Peak memory 195852 kb
Host smart-31acbe00-9e95-4f31-8def-dcc8725616c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317920625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.317920625
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2944762617
Short name T49
Test name
Test status
Simulation time 71794901 ps
CPU time 1.11 seconds
Started Jun 07 07:38:10 PM PDT 24
Finished Jun 07 07:38:15 PM PDT 24
Peak memory 195836 kb
Host smart-da1d9ee7-1f60-4098-978f-2854e205c2e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944762617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2944762617
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3233046472
Short name T559
Test name
Test status
Simulation time 96802692680 ps
CPU time 116.76 seconds
Started Jun 07 07:38:13 PM PDT 24
Finished Jun 07 07:40:13 PM PDT 24
Peak memory 198248 kb
Host smart-03fc77a0-1a70-4e81-ae49-5ba059b3d49f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233046472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3233046472
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3184046346
Short name T683
Test name
Test status
Simulation time 53713895925 ps
CPU time 1029 seconds
Started Jun 07 07:38:18 PM PDT 24
Finished Jun 07 07:55:31 PM PDT 24
Peak memory 198272 kb
Host smart-e19ff344-d1ec-43f4-9449-3080e80cca34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3184046346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3184046346
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3391957660
Short name T242
Test name
Test status
Simulation time 12381690 ps
CPU time 0.58 seconds
Started Jun 07 07:38:25 PM PDT 24
Finished Jun 07 07:38:29 PM PDT 24
Peak memory 193920 kb
Host smart-4878fe9d-680f-4516-9af2-5522d7e5de8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391957660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3391957660
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1604267335
Short name T677
Test name
Test status
Simulation time 30593477 ps
CPU time 0.9 seconds
Started Jun 07 07:38:19 PM PDT 24
Finished Jun 07 07:38:25 PM PDT 24
Peak memory 196620 kb
Host smart-fdfba89a-75ef-4fb5-a6ce-de5aed7e4c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604267335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1604267335
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.469107424
Short name T451
Test name
Test status
Simulation time 1865765379 ps
CPU time 13.53 seconds
Started Jun 07 07:38:19 PM PDT 24
Finished Jun 07 07:38:38 PM PDT 24
Peak memory 196940 kb
Host smart-df5899f4-7703-46a0-aed1-5c4b544eb177
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469107424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.469107424
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3061559338
Short name T184
Test name
Test status
Simulation time 54627234 ps
CPU time 0.94 seconds
Started Jun 07 07:38:19 PM PDT 24
Finished Jun 07 07:38:25 PM PDT 24
Peak memory 197200 kb
Host smart-dcfd257d-cd79-448b-9029-9a9305e2d041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061559338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3061559338
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1462775365
Short name T298
Test name
Test status
Simulation time 73588017 ps
CPU time 1.33 seconds
Started Jun 07 07:38:18 PM PDT 24
Finished Jun 07 07:38:24 PM PDT 24
Peak memory 196620 kb
Host smart-0cd0d295-34be-4d63-9cb1-70daa4f0cdbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462775365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1462775365
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.41699296
Short name T560
Test name
Test status
Simulation time 24181762 ps
CPU time 1.15 seconds
Started Jun 07 07:38:19 PM PDT 24
Finished Jun 07 07:38:25 PM PDT 24
Peak memory 197224 kb
Host smart-69cc1e0c-2fa6-4b61-aa35-56b913d1c1a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41699296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.gpio_intr_with_filter_rand_intr_event.41699296
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2296770172
Short name T539
Test name
Test status
Simulation time 55917298 ps
CPU time 1.37 seconds
Started Jun 07 07:38:21 PM PDT 24
Finished Jun 07 07:38:27 PM PDT 24
Peak memory 196736 kb
Host smart-0bfa29f4-6941-4406-b9de-6b70afa97a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296770172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2296770172
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2458026495
Short name T464
Test name
Test status
Simulation time 90551700 ps
CPU time 1.01 seconds
Started Jun 07 07:38:20 PM PDT 24
Finished Jun 07 07:38:26 PM PDT 24
Peak memory 195908 kb
Host smart-f9b2f6dc-23ac-44bd-92b9-40ba19ef66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458026495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2458026495
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1808300271
Short name T318
Test name
Test status
Simulation time 40793959 ps
CPU time 1.04 seconds
Started Jun 07 07:38:19 PM PDT 24
Finished Jun 07 07:38:25 PM PDT 24
Peak memory 196084 kb
Host smart-7f27a2fa-0775-4f12-af9e-d4196662255b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808300271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1808300271
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.695967265
Short name T5
Test name
Test status
Simulation time 6045206410 ps
CPU time 5.29 seconds
Started Jun 07 07:38:19 PM PDT 24
Finished Jun 07 07:38:29 PM PDT 24
Peak memory 198192 kb
Host smart-ce60c442-3a9a-4069-9b44-62971eede956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695967265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.695967265
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3444257078
Short name T292
Test name
Test status
Simulation time 55428409 ps
CPU time 1.02 seconds
Started Jun 07 07:38:17 PM PDT 24
Finished Jun 07 07:38:22 PM PDT 24
Peak memory 195840 kb
Host smart-082d6b26-5ad0-4d46-92e2-4f706487a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444257078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3444257078
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2733793016
Short name T596
Test name
Test status
Simulation time 69099407 ps
CPU time 1.24 seconds
Started Jun 07 07:38:18 PM PDT 24
Finished Jun 07 07:38:22 PM PDT 24
Peak memory 196636 kb
Host smart-e1e151a9-574d-45d7-aa53-181e2d97276e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733793016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2733793016
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1730487367
Short name T461
Test name
Test status
Simulation time 7482435675 ps
CPU time 92.57 seconds
Started Jun 07 07:38:18 PM PDT 24
Finished Jun 07 07:39:55 PM PDT 24
Peak memory 198216 kb
Host smart-f15217a7-5f43-4a39-9701-2c1b9b1d2acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730487367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1730487367
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3665508386
Short name T233
Test name
Test status
Simulation time 15253929 ps
CPU time 0.59 seconds
Started Jun 07 07:38:29 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 194676 kb
Host smart-98115168-63a8-4f6a-a447-b1eb87694d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665508386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3665508386
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3329233256
Short name T204
Test name
Test status
Simulation time 287853620 ps
CPU time 0.72 seconds
Started Jun 07 07:38:28 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 195412 kb
Host smart-665a1498-5d91-41ce-aa96-2c7b84e6806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329233256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3329233256
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1391478620
Short name T558
Test name
Test status
Simulation time 376494134 ps
CPU time 19.89 seconds
Started Jun 07 07:38:31 PM PDT 24
Finished Jun 07 07:38:52 PM PDT 24
Peak memory 196940 kb
Host smart-0f6fcf47-66c4-4b07-9818-04891eef4c3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391478620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1391478620
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2121876641
Short name T718
Test name
Test status
Simulation time 229415143 ps
CPU time 0.89 seconds
Started Jun 07 07:38:26 PM PDT 24
Finished Jun 07 07:38:30 PM PDT 24
Peak memory 196772 kb
Host smart-e1a73c06-35b4-41aa-b0b1-c5e5b6c2bad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121876641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2121876641
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2350368420
Short name T491
Test name
Test status
Simulation time 33846605 ps
CPU time 0.9 seconds
Started Jun 07 07:38:27 PM PDT 24
Finished Jun 07 07:38:31 PM PDT 24
Peak memory 195920 kb
Host smart-c28d3e9e-ae2a-4de9-a7c6-180e5ff1be3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350368420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2350368420
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1595813258
Short name T383
Test name
Test status
Simulation time 115279376 ps
CPU time 2.15 seconds
Started Jun 07 07:38:29 PM PDT 24
Finished Jun 07 07:38:34 PM PDT 24
Peak memory 197284 kb
Host smart-3c505656-d2a1-44c0-a839-e0c75b335797
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595813258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1595813258
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.946049635
Short name T77
Test name
Test status
Simulation time 86543035 ps
CPU time 0.82 seconds
Started Jun 07 07:38:29 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 195532 kb
Host smart-6cbfbb24-38b7-4fbd-b9d0-cc6fdb48b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946049635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.946049635
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3016169498
Short name T525
Test name
Test status
Simulation time 26469930 ps
CPU time 1.02 seconds
Started Jun 07 07:38:28 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 195908 kb
Host smart-d3384b08-06db-4a77-b65f-d58c3b6c5cfb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016169498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3016169498
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4277935537
Short name T127
Test name
Test status
Simulation time 23570614 ps
CPU time 1.02 seconds
Started Jun 07 07:38:27 PM PDT 24
Finished Jun 07 07:38:31 PM PDT 24
Peak memory 196444 kb
Host smart-b4324031-658c-431a-a5ee-2812e67c4d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277935537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4277935537
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2360323717
Short name T247
Test name
Test status
Simulation time 278426392 ps
CPU time 1.34 seconds
Started Jun 07 07:38:26 PM PDT 24
Finished Jun 07 07:38:30 PM PDT 24
Peak memory 196760 kb
Host smart-ca801246-f38c-42e9-a517-348519fa65da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360323717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2360323717
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3050519087
Short name T643
Test name
Test status
Simulation time 46434641 ps
CPU time 0.96 seconds
Started Jun 07 07:38:28 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 195656 kb
Host smart-f259d94f-f1b4-4abe-9644-34fb1518e0bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050519087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3050519087
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1365173356
Short name T475
Test name
Test status
Simulation time 37804003178 ps
CPU time 238.47 seconds
Started Jun 07 07:38:26 PM PDT 24
Finished Jun 07 07:42:28 PM PDT 24
Peak memory 198200 kb
Host smart-faafbd8f-884f-4ca5-b36a-da15a4a45f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365173356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1365173356
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.544095235
Short name T187
Test name
Test status
Simulation time 34263095 ps
CPU time 0.55 seconds
Started Jun 07 07:38:34 PM PDT 24
Finished Jun 07 07:38:36 PM PDT 24
Peak memory 193944 kb
Host smart-8decb6a6-96ab-4894-989e-5f0c62f6e4d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544095235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.544095235
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1681910162
Short name T457
Test name
Test status
Simulation time 91341496 ps
CPU time 0.76 seconds
Started Jun 07 07:38:40 PM PDT 24
Finished Jun 07 07:38:42 PM PDT 24
Peak memory 195332 kb
Host smart-4b59c1b7-f6ad-408d-9849-8fab6dd8b03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681910162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1681910162
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2986338550
Short name T518
Test name
Test status
Simulation time 714004238 ps
CPU time 25.05 seconds
Started Jun 07 07:38:42 PM PDT 24
Finished Jun 07 07:39:08 PM PDT 24
Peak memory 195564 kb
Host smart-c340149a-1e73-4ef2-a3a4-1acd34070652
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986338550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2986338550
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.264003745
Short name T449
Test name
Test status
Simulation time 96618150 ps
CPU time 1.11 seconds
Started Jun 07 07:38:35 PM PDT 24
Finished Jun 07 07:38:38 PM PDT 24
Peak memory 198008 kb
Host smart-4ecf0145-8acd-446c-b8ad-9270d564a27b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264003745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.264003745
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3714400406
Short name T690
Test name
Test status
Simulation time 45925571 ps
CPU time 1.23 seconds
Started Jun 07 07:38:33 PM PDT 24
Finished Jun 07 07:38:36 PM PDT 24
Peak memory 196044 kb
Host smart-e1c82650-4694-4545-b818-69f71b7fee94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714400406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3714400406
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.118436969
Short name T717
Test name
Test status
Simulation time 195573828 ps
CPU time 2.16 seconds
Started Jun 07 07:38:37 PM PDT 24
Finished Jun 07 07:38:41 PM PDT 24
Peak memory 198100 kb
Host smart-65fefe02-3aee-4012-a8cc-2a33f127e81a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118436969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.118436969
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2506957490
Short name T156
Test name
Test status
Simulation time 304631900 ps
CPU time 1.86 seconds
Started Jun 07 07:38:34 PM PDT 24
Finished Jun 07 07:38:37 PM PDT 24
Peak memory 195824 kb
Host smart-bad48418-a189-47eb-ae31-e512f0649a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506957490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2506957490
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2104440305
Short name T580
Test name
Test status
Simulation time 289325070 ps
CPU time 1.27 seconds
Started Jun 07 07:38:25 PM PDT 24
Finished Jun 07 07:38:30 PM PDT 24
Peak memory 196920 kb
Host smart-5f69def8-d877-4e3d-bb81-67dcec5caaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104440305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2104440305
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3014217082
Short name T405
Test name
Test status
Simulation time 94092930 ps
CPU time 0.89 seconds
Started Jun 07 07:38:27 PM PDT 24
Finished Jun 07 07:38:31 PM PDT 24
Peak memory 196752 kb
Host smart-e0f36e53-7767-409e-83a4-d4d6203c95b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014217082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3014217082
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1123303094
Short name T124
Test name
Test status
Simulation time 387829085 ps
CPU time 3.2 seconds
Started Jun 07 07:38:34 PM PDT 24
Finished Jun 07 07:38:39 PM PDT 24
Peak memory 198052 kb
Host smart-a37e099e-943d-4d62-bf03-84f8e720ddbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123303094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1123303094
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1644846788
Short name T583
Test name
Test status
Simulation time 136744465 ps
CPU time 1.24 seconds
Started Jun 07 07:38:27 PM PDT 24
Finished Jun 07 07:38:32 PM PDT 24
Peak memory 196696 kb
Host smart-ed652e21-8e54-4655-99f9-a829e402ab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644846788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1644846788
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3275356541
Short name T397
Test name
Test status
Simulation time 217098447 ps
CPU time 1.04 seconds
Started Jun 07 07:38:27 PM PDT 24
Finished Jun 07 07:38:31 PM PDT 24
Peak memory 195840 kb
Host smart-04309ce0-93d0-4634-a45d-cd9280773720
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275356541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3275356541
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2309604236
Short name T22
Test name
Test status
Simulation time 5381922688 ps
CPU time 33.05 seconds
Started Jun 07 07:38:42 PM PDT 24
Finished Jun 07 07:39:16 PM PDT 24
Peak memory 198216 kb
Host smart-82c231d4-a1b4-4232-b8f1-87821215b833
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309604236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2309604236
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.882957599
Short name T341
Test name
Test status
Simulation time 15478278 ps
CPU time 0.63 seconds
Started Jun 07 07:35:40 PM PDT 24
Finished Jun 07 07:35:43 PM PDT 24
Peak memory 194144 kb
Host smart-d70e156a-0728-4e1f-8ef2-162d1870226f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882957599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.882957599
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.953019268
Short name T404
Test name
Test status
Simulation time 49445765 ps
CPU time 0.71 seconds
Started Jun 07 07:35:35 PM PDT 24
Finished Jun 07 07:35:37 PM PDT 24
Peak memory 195396 kb
Host smart-1166b6f8-40c5-41b5-adf7-76c7f0aa8fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953019268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.953019268
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2429277200
Short name T376
Test name
Test status
Simulation time 722904759 ps
CPU time 5.72 seconds
Started Jun 07 07:35:38 PM PDT 24
Finished Jun 07 07:35:44 PM PDT 24
Peak memory 196560 kb
Host smart-d0c2efac-59fa-45e0-aa9b-440b93088b0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429277200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2429277200
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.905461574
Short name T642
Test name
Test status
Simulation time 62011324 ps
CPU time 0.66 seconds
Started Jun 07 07:35:40 PM PDT 24
Finished Jun 07 07:35:42 PM PDT 24
Peak memory 194744 kb
Host smart-453a78f1-80c1-49d0-8d1f-58f9ade5fab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905461574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.905461574
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.625789245
Short name T163
Test name
Test status
Simulation time 29287051 ps
CPU time 0.86 seconds
Started Jun 07 07:35:34 PM PDT 24
Finished Jun 07 07:35:37 PM PDT 24
Peak memory 196600 kb
Host smart-f6faffb9-83c9-4280-9337-4a7a81df3b46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625789245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.625789245
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1980254696
Short name T603
Test name
Test status
Simulation time 54219158 ps
CPU time 2.39 seconds
Started Jun 07 07:35:34 PM PDT 24
Finished Jun 07 07:35:39 PM PDT 24
Peak memory 198112 kb
Host smart-e9459ace-5047-4f44-a12c-730463b6df20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980254696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1980254696
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1659202686
Short name T593
Test name
Test status
Simulation time 377829690 ps
CPU time 2.58 seconds
Started Jun 07 07:35:34 PM PDT 24
Finished Jun 07 07:35:39 PM PDT 24
Peak memory 195816 kb
Host smart-645efd9b-f581-46ac-893c-38021ae07b94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659202686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1659202686
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1728818098
Short name T574
Test name
Test status
Simulation time 54293850 ps
CPU time 0.93 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:35:36 PM PDT 24
Peak memory 196064 kb
Host smart-464c9d7f-710c-40fc-96b0-437c66dc72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728818098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1728818098
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1263521156
Short name T571
Test name
Test status
Simulation time 61985211 ps
CPU time 0.82 seconds
Started Jun 07 07:35:33 PM PDT 24
Finished Jun 07 07:35:36 PM PDT 24
Peak memory 196336 kb
Host smart-507f83b0-025e-453e-9421-1210167a6fee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263521156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1263521156
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2960472790
Short name T577
Test name
Test status
Simulation time 263104580 ps
CPU time 6.35 seconds
Started Jun 07 07:35:40 PM PDT 24
Finished Jun 07 07:35:48 PM PDT 24
Peak memory 198064 kb
Host smart-572d0335-fd32-452f-8c72-1fd0c2ccd038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960472790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2960472790
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.1661057114
Short name T395
Test name
Test status
Simulation time 40181944 ps
CPU time 1.11 seconds
Started Jun 07 07:35:40 PM PDT 24
Finished Jun 07 07:35:43 PM PDT 24
Peak memory 195800 kb
Host smart-77c04db5-fd9c-40a1-bf66-c2a2790f1250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661057114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1661057114
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1088090802
Short name T500
Test name
Test status
Simulation time 81032499 ps
CPU time 1.2 seconds
Started Jun 07 07:35:37 PM PDT 24
Finished Jun 07 07:35:40 PM PDT 24
Peak memory 195896 kb
Host smart-8ea8b753-efaa-433d-96fb-fc9eda4452ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088090802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1088090802
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3023863057
Short name T73
Test name
Test status
Simulation time 3731089490 ps
CPU time 41.08 seconds
Started Jun 07 07:35:43 PM PDT 24
Finished Jun 07 07:36:27 PM PDT 24
Peak memory 198244 kb
Host smart-59e07d15-dbb4-4702-b951-6dc6584d7fbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023863057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3023863057
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2608970280
Short name T108
Test name
Test status
Simulation time 134848555866 ps
CPU time 1629.67 seconds
Started Jun 07 07:35:42 PM PDT 24
Finished Jun 07 08:02:55 PM PDT 24
Peak memory 198320 kb
Host smart-de0078ad-e350-4d31-8c3f-5405d89c9064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2608970280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2608970280
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.588182200
Short name T36
Test name
Test status
Simulation time 12741084 ps
CPU time 0.59 seconds
Started Jun 07 07:38:45 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 193984 kb
Host smart-439d0f05-fc98-4ec8-b96d-182f2dcb4470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588182200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.588182200
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1046201989
Short name T51
Test name
Test status
Simulation time 36758262 ps
CPU time 0.64 seconds
Started Jun 07 07:38:42 PM PDT 24
Finished Jun 07 07:38:45 PM PDT 24
Peak memory 193968 kb
Host smart-039bd5c3-012a-43bd-8b9e-bd88a64bd13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046201989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1046201989
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2431189190
Short name T692
Test name
Test status
Simulation time 5808957372 ps
CPU time 14.95 seconds
Started Jun 07 07:38:44 PM PDT 24
Finished Jun 07 07:39:02 PM PDT 24
Peak memory 197152 kb
Host smart-bb8db87c-92ea-4a7e-a669-72d066eae006
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431189190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2431189190
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.874509783
Short name T670
Test name
Test status
Simulation time 60775475 ps
CPU time 0.9 seconds
Started Jun 07 07:38:45 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 196260 kb
Host smart-e9d57d0b-ccaf-41f2-a4cc-5c57583211a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874509783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.874509783
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1443041154
Short name T675
Test name
Test status
Simulation time 73571334 ps
CPU time 1.33 seconds
Started Jun 07 07:38:44 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 196840 kb
Host smart-b47a359c-20c0-457d-812e-64f981ea3376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443041154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1443041154
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4036230480
Short name T433
Test name
Test status
Simulation time 265620992 ps
CPU time 2.84 seconds
Started Jun 07 07:38:43 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 198084 kb
Host smart-a3cc726b-31dd-408e-a1db-83b6a4d5c00b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036230480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4036230480
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1312065844
Short name T614
Test name
Test status
Simulation time 117789171 ps
CPU time 3.33 seconds
Started Jun 07 07:38:43 PM PDT 24
Finished Jun 07 07:38:50 PM PDT 24
Peak memory 197408 kb
Host smart-c4496435-6a13-4e68-b4af-c329748294f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312065844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1312065844
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2540761071
Short name T655
Test name
Test status
Simulation time 71861215 ps
CPU time 1.21 seconds
Started Jun 07 07:38:36 PM PDT 24
Finished Jun 07 07:38:39 PM PDT 24
Peak memory 196124 kb
Host smart-c606863f-fd3d-44ed-b873-0cc5ac04fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540761071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2540761071
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3990057857
Short name T618
Test name
Test status
Simulation time 107180648 ps
CPU time 1.28 seconds
Started Jun 07 07:38:42 PM PDT 24
Finished Jun 07 07:38:44 PM PDT 24
Peak memory 195908 kb
Host smart-f03657c6-5de6-406a-868a-d38c78372a4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990057857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3990057857
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.163918398
Short name T173
Test name
Test status
Simulation time 1310941241 ps
CPU time 5.61 seconds
Started Jun 07 07:38:44 PM PDT 24
Finished Jun 07 07:38:53 PM PDT 24
Peak memory 198020 kb
Host smart-6549d946-5d3c-4e8a-abc1-3aef452cf153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163918398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.163918398
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.595072128
Short name T622
Test name
Test status
Simulation time 144691811 ps
CPU time 1.19 seconds
Started Jun 07 07:38:35 PM PDT 24
Finished Jun 07 07:38:38 PM PDT 24
Peak memory 196512 kb
Host smart-edecb2e6-9bce-49a6-b440-7fdcd50f78a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595072128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.595072128
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4179684921
Short name T605
Test name
Test status
Simulation time 50662930 ps
CPU time 1.13 seconds
Started Jun 07 07:38:36 PM PDT 24
Finished Jun 07 07:38:39 PM PDT 24
Peak memory 195612 kb
Host smart-016c6a41-def7-445b-a5ef-cfba3c0b04b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179684921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4179684921
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2151462945
Short name T365
Test name
Test status
Simulation time 14892674243 ps
CPU time 131.51 seconds
Started Jun 07 07:38:43 PM PDT 24
Finished Jun 07 07:40:58 PM PDT 24
Peak memory 198184 kb
Host smart-05dd376f-426c-41a2-8a47-5066e778edf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151462945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2151462945
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3082684275
Short name T172
Test name
Test status
Simulation time 38690120 ps
CPU time 0.58 seconds
Started Jun 07 07:38:50 PM PDT 24
Finished Jun 07 07:38:53 PM PDT 24
Peak memory 194120 kb
Host smart-de7cf579-ff6f-459c-97cc-1936c74a87d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082684275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3082684275
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1535860191
Short name T14
Test name
Test status
Simulation time 37576453 ps
CPU time 0.87 seconds
Started Jun 07 07:38:44 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 195556 kb
Host smart-9ccef24d-8c0f-4709-8882-1b485b654737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535860191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1535860191
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3461830037
Short name T542
Test name
Test status
Simulation time 3374158742 ps
CPU time 13.93 seconds
Started Jun 07 07:38:50 PM PDT 24
Finished Jun 07 07:39:07 PM PDT 24
Peak memory 198224 kb
Host smart-735c282a-c622-4e45-b65c-e2742945ed2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461830037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3461830037
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.989902916
Short name T215
Test name
Test status
Simulation time 72749790 ps
CPU time 0.64 seconds
Started Jun 07 07:38:51 PM PDT 24
Finished Jun 07 07:38:54 PM PDT 24
Peak memory 195200 kb
Host smart-ac62d1b6-0ced-43bc-898b-5a1420269662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989902916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.989902916
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3348394283
Short name T280
Test name
Test status
Simulation time 692161838 ps
CPU time 1.26 seconds
Started Jun 07 07:38:42 PM PDT 24
Finished Jun 07 07:38:44 PM PDT 24
Peak memory 196196 kb
Host smart-1d478671-b658-4e5e-a1ac-4d4287fe463b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348394283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3348394283
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.538514078
Short name T688
Test name
Test status
Simulation time 257735937 ps
CPU time 2.56 seconds
Started Jun 07 07:38:43 PM PDT 24
Finished Jun 07 07:38:48 PM PDT 24
Peak memory 197072 kb
Host smart-a78ebc23-28b9-4972-97c9-15487b7f77ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538514078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.538514078
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3894683925
Short name T316
Test name
Test status
Simulation time 71466970 ps
CPU time 2.12 seconds
Started Jun 07 07:38:43 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 197992 kb
Host smart-110d338f-82a9-4e0e-86c2-4303432caca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894683925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3894683925
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1144191998
Short name T56
Test name
Test status
Simulation time 240792796 ps
CPU time 1.32 seconds
Started Jun 07 07:38:44 PM PDT 24
Finished Jun 07 07:38:49 PM PDT 24
Peak memory 197052 kb
Host smart-ddb13af3-38b8-4dcd-b7ba-5d931275b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144191998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1144191998
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2276825596
Short name T623
Test name
Test status
Simulation time 27215020 ps
CPU time 0.82 seconds
Started Jun 07 07:38:42 PM PDT 24
Finished Jun 07 07:38:45 PM PDT 24
Peak memory 195440 kb
Host smart-a62e3bec-301d-463e-bdee-72d68344c95f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276825596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2276825596
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.108701749
Short name T673
Test name
Test status
Simulation time 74394662 ps
CPU time 3.48 seconds
Started Jun 07 07:38:56 PM PDT 24
Finished Jun 07 07:39:02 PM PDT 24
Peak memory 198044 kb
Host smart-567b8343-ddf5-4b9a-bb3e-f85a14b53505
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108701749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.108701749
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1635733505
Short name T502
Test name
Test status
Simulation time 24792744 ps
CPU time 0.7 seconds
Started Jun 07 07:38:44 PM PDT 24
Finished Jun 07 07:38:48 PM PDT 24
Peak memory 194132 kb
Host smart-3691259e-ace3-47ff-a39e-1a2c7f0cc7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635733505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1635733505
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.833022306
Short name T629
Test name
Test status
Simulation time 25560801 ps
CPU time 0.79 seconds
Started Jun 07 07:38:43 PM PDT 24
Finished Jun 07 07:38:46 PM PDT 24
Peak memory 195432 kb
Host smart-463e33ee-50eb-48ca-b39b-fa98a1fb5323
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833022306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.833022306
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3126418344
Short name T74
Test name
Test status
Simulation time 19363889931 ps
CPU time 52.1 seconds
Started Jun 07 07:38:57 PM PDT 24
Finished Jun 07 07:39:51 PM PDT 24
Peak memory 198240 kb
Host smart-25aadab9-aea3-4b14-9cff-ce1043e5463c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126418344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3126418344
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3602908080
Short name T61
Test name
Test status
Simulation time 115033661199 ps
CPU time 1045.07 seconds
Started Jun 07 07:38:49 PM PDT 24
Finished Jun 07 07:56:16 PM PDT 24
Peak memory 198272 kb
Host smart-f3ad589d-3c84-49bd-a049-b74d5dd9b2d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3602908080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3602908080
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3020848826
Short name T199
Test name
Test status
Simulation time 136381917 ps
CPU time 0.56 seconds
Started Jun 07 07:38:58 PM PDT 24
Finished Jun 07 07:39:01 PM PDT 24
Peak memory 194636 kb
Host smart-7371a3ae-25f1-4429-a89a-fac778beffd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020848826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3020848826
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.920455111
Short name T330
Test name
Test status
Simulation time 161212873 ps
CPU time 0.95 seconds
Started Jun 07 07:38:57 PM PDT 24
Finished Jun 07 07:39:00 PM PDT 24
Peak memory 195968 kb
Host smart-2d93a368-4dcd-44d1-9dbe-c7ff56689dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920455111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.920455111
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2038799763
Short name T721
Test name
Test status
Simulation time 966502857 ps
CPU time 16.49 seconds
Started Jun 07 07:38:56 PM PDT 24
Finished Jun 07 07:39:14 PM PDT 24
Peak memory 197000 kb
Host smart-4bd81ac9-ac92-4f8e-8ecb-3d79570cc3e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038799763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2038799763
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4036576064
Short name T289
Test name
Test status
Simulation time 62919260 ps
CPU time 0.65 seconds
Started Jun 07 07:38:55 PM PDT 24
Finished Jun 07 07:38:58 PM PDT 24
Peak memory 194776 kb
Host smart-98b90cec-7459-477b-9f41-423bebb94b17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036576064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4036576064
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2342517009
Short name T361
Test name
Test status
Simulation time 167689125 ps
CPU time 0.85 seconds
Started Jun 07 07:38:50 PM PDT 24
Finished Jun 07 07:38:53 PM PDT 24
Peak memory 197252 kb
Host smart-e90afb7b-86c5-4f01-a758-993aad48e67f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342517009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2342517009
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3036626334
Short name T638
Test name
Test status
Simulation time 118387900 ps
CPU time 3.77 seconds
Started Jun 07 07:38:50 PM PDT 24
Finished Jun 07 07:38:56 PM PDT 24
Peak memory 198100 kb
Host smart-a8347946-e97b-48c5-b65c-d5eb8b4e1549
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036626334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3036626334
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.998306391
Short name T363
Test name
Test status
Simulation time 151858953 ps
CPU time 1.54 seconds
Started Jun 07 07:38:51 PM PDT 24
Finished Jun 07 07:38:55 PM PDT 24
Peak memory 196104 kb
Host smart-ed84ce31-40b3-4e29-8491-48feb8d432db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998306391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
998306391
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.679422949
Short name T252
Test name
Test status
Simulation time 52225908 ps
CPU time 1.28 seconds
Started Jun 07 07:38:50 PM PDT 24
Finished Jun 07 07:38:53 PM PDT 24
Peak memory 197088 kb
Host smart-91eed630-052e-48b4-bc2d-da2bd60ba0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679422949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.679422949
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1751073754
Short name T191
Test name
Test status
Simulation time 224895953 ps
CPU time 0.64 seconds
Started Jun 07 07:38:50 PM PDT 24
Finished Jun 07 07:38:54 PM PDT 24
Peak memory 194428 kb
Host smart-8a33c76e-d1cb-4e77-8903-2baa1516299e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751073754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1751073754
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.656078158
Short name T342
Test name
Test status
Simulation time 113775061 ps
CPU time 2.8 seconds
Started Jun 07 07:38:59 PM PDT 24
Finished Jun 07 07:39:05 PM PDT 24
Peak memory 197912 kb
Host smart-cc2beb5c-0975-4b3f-9d7e-4bf402e8cf66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656078158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.656078158
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1183956347
Short name T13
Test name
Test status
Simulation time 38716048 ps
CPU time 1.16 seconds
Started Jun 07 07:38:52 PM PDT 24
Finished Jun 07 07:38:55 PM PDT 24
Peak memory 196436 kb
Host smart-894529ef-260d-4867-9674-00642be3954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183956347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1183956347
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1926706970
Short name T450
Test name
Test status
Simulation time 45546437 ps
CPU time 1.25 seconds
Started Jun 07 07:38:56 PM PDT 24
Finished Jun 07 07:39:00 PM PDT 24
Peak memory 196896 kb
Host smart-c8408705-8415-4147-b07b-291765cc23ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926706970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1926706970
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3906808134
Short name T2
Test name
Test status
Simulation time 12754683653 ps
CPU time 68.33 seconds
Started Jun 07 07:38:55 PM PDT 24
Finished Jun 07 07:40:06 PM PDT 24
Peak memory 198212 kb
Host smart-477f6448-8e46-4a3c-8d33-f1bcd0591e90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906808134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3906808134
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.496789337
Short name T415
Test name
Test status
Simulation time 18896597 ps
CPU time 0.59 seconds
Started Jun 07 07:39:05 PM PDT 24
Finished Jun 07 07:39:08 PM PDT 24
Peak memory 194124 kb
Host smart-f648b0b8-9939-4b5b-9a7d-c98f1e2ea7e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496789337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.496789337
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.371350585
Short name T406
Test name
Test status
Simulation time 59098569 ps
CPU time 0.95 seconds
Started Jun 07 07:38:56 PM PDT 24
Finished Jun 07 07:38:59 PM PDT 24
Peak memory 197360 kb
Host smart-0f4e77b0-35d0-403d-9158-40e678e51e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371350585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.371350585
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3568047380
Short name T481
Test name
Test status
Simulation time 4449893072 ps
CPU time 24.96 seconds
Started Jun 07 07:38:56 PM PDT 24
Finished Jun 07 07:39:23 PM PDT 24
Peak memory 198068 kb
Host smart-27a23ed8-a799-437f-a53d-dfd04b9d69f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568047380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3568047380
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1385833365
Short name T372
Test name
Test status
Simulation time 126921359 ps
CPU time 0.89 seconds
Started Jun 07 07:38:56 PM PDT 24
Finished Jun 07 07:38:59 PM PDT 24
Peak memory 196664 kb
Host smart-0da1a94f-23bf-40cc-b2f5-a439717b1ea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385833365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1385833365
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2598972405
Short name T188
Test name
Test status
Simulation time 318893680 ps
CPU time 1.3 seconds
Started Jun 07 07:38:59 PM PDT 24
Finished Jun 07 07:39:03 PM PDT 24
Peak memory 196204 kb
Host smart-048d3ed5-39a9-4fc5-91ef-63826e7bbcb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598972405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2598972405
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1064858895
Short name T368
Test name
Test status
Simulation time 98288763 ps
CPU time 1.22 seconds
Started Jun 07 07:38:57 PM PDT 24
Finished Jun 07 07:39:01 PM PDT 24
Peak memory 196816 kb
Host smart-10313808-2bf8-4494-a6b9-ebfbc4f678a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064858895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1064858895
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.998038280
Short name T359
Test name
Test status
Simulation time 41668055 ps
CPU time 1.33 seconds
Started Jun 07 07:38:58 PM PDT 24
Finished Jun 07 07:39:02 PM PDT 24
Peak memory 196208 kb
Host smart-0156f9cf-d94a-4d23-b90c-5b81c47d75a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998038280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
998038280
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4240930068
Short name T142
Test name
Test status
Simulation time 303482452 ps
CPU time 1.4 seconds
Started Jun 07 07:38:58 PM PDT 24
Finished Jun 07 07:39:01 PM PDT 24
Peak memory 197140 kb
Host smart-37a08594-9188-4014-86d9-d6d794b00c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240930068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4240930068
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3991562389
Short name T178
Test name
Test status
Simulation time 78838106 ps
CPU time 1.04 seconds
Started Jun 07 07:38:57 PM PDT 24
Finished Jun 07 07:39:00 PM PDT 24
Peak memory 196076 kb
Host smart-8a23eedf-877d-4c64-9d0f-82ba94e97770
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991562389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3991562389
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.769128264
Short name T337
Test name
Test status
Simulation time 79934596 ps
CPU time 3.55 seconds
Started Jun 07 07:38:57 PM PDT 24
Finished Jun 07 07:39:03 PM PDT 24
Peak memory 198068 kb
Host smart-05c0bfde-d6ff-4e54-a74c-e75091a241b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769128264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.769128264
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.301903845
Short name T543
Test name
Test status
Simulation time 292727323 ps
CPU time 1.36 seconds
Started Jun 07 07:38:57 PM PDT 24
Finished Jun 07 07:39:01 PM PDT 24
Peak memory 195640 kb
Host smart-677210a2-dbec-4622-9dc7-f89a598650dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301903845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.301903845
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.315846936
Short name T345
Test name
Test status
Simulation time 37719685 ps
CPU time 1.11 seconds
Started Jun 07 07:38:58 PM PDT 24
Finished Jun 07 07:39:02 PM PDT 24
Peak memory 195720 kb
Host smart-6d03adbd-ad85-4d34-866f-5f305ac0a36e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315846936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.315846936
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3040201948
Short name T672
Test name
Test status
Simulation time 5536256274 ps
CPU time 88.05 seconds
Started Jun 07 07:39:00 PM PDT 24
Finished Jun 07 07:40:30 PM PDT 24
Peak memory 198216 kb
Host smart-53670376-3537-4736-8f5c-0319dda00d19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040201948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3040201948
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2997353362
Short name T307
Test name
Test status
Simulation time 315060306985 ps
CPU time 2363.9 seconds
Started Jun 07 07:38:58 PM PDT 24
Finished Jun 07 08:18:25 PM PDT 24
Peak memory 198344 kb
Host smart-05e9bffd-d832-4cf7-a688-5cc92feb787a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2997353362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2997353362
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.667441939
Short name T612
Test name
Test status
Simulation time 14610756 ps
CPU time 0.56 seconds
Started Jun 07 07:39:14 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 193956 kb
Host smart-03db4f1d-940c-4985-91eb-279ae598a48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667441939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.667441939
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4081989351
Short name T179
Test name
Test status
Simulation time 170388024 ps
CPU time 0.88 seconds
Started Jun 07 07:39:05 PM PDT 24
Finished Jun 07 07:39:08 PM PDT 24
Peak memory 195528 kb
Host smart-627d29da-34b0-41bb-b0b4-23c04cca0c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081989351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4081989351
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3104127872
Short name T115
Test name
Test status
Simulation time 1698465506 ps
CPU time 22.71 seconds
Started Jun 07 07:39:06 PM PDT 24
Finished Jun 07 07:39:31 PM PDT 24
Peak memory 196268 kb
Host smart-0ac022a4-e188-4fa5-88e3-282e4a3197f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104127872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3104127872
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2394001787
Short name T364
Test name
Test status
Simulation time 55036688 ps
CPU time 1.04 seconds
Started Jun 07 07:39:06 PM PDT 24
Finished Jun 07 07:39:10 PM PDT 24
Peak memory 197744 kb
Host smart-64848a27-40e7-47e0-9cd6-6ccc0f9f8d96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394001787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2394001787
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1883205582
Short name T439
Test name
Test status
Simulation time 34786764 ps
CPU time 1.18 seconds
Started Jun 07 07:39:06 PM PDT 24
Finished Jun 07 07:39:10 PM PDT 24
Peak memory 196092 kb
Host smart-6f96998d-0d0a-45a6-9692-3f8d8f34015c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883205582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1883205582
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3776328192
Short name T360
Test name
Test status
Simulation time 168389444 ps
CPU time 3.34 seconds
Started Jun 07 07:39:07 PM PDT 24
Finished Jun 07 07:39:13 PM PDT 24
Peak memory 198108 kb
Host smart-fac07d42-7f11-4a7b-b5db-3b16c86c9a9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776328192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3776328192
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.219652757
Short name T531
Test name
Test status
Simulation time 575559795 ps
CPU time 3.82 seconds
Started Jun 07 07:39:06 PM PDT 24
Finished Jun 07 07:39:12 PM PDT 24
Peak memory 195568 kb
Host smart-1c2fea6a-f02f-459a-99aa-ca4bf147c47b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219652757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
219652757
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3051593404
Short name T647
Test name
Test status
Simulation time 34894724 ps
CPU time 0.99 seconds
Started Jun 07 07:39:04 PM PDT 24
Finished Jun 07 07:39:05 PM PDT 24
Peak memory 196752 kb
Host smart-c888e514-4c5e-4c90-985f-499d2676bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051593404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3051593404
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1254676415
Short name T200
Test name
Test status
Simulation time 65735514 ps
CPU time 0.83 seconds
Started Jun 07 07:39:08 PM PDT 24
Finished Jun 07 07:39:11 PM PDT 24
Peak memory 197268 kb
Host smart-4732f593-aa3a-4f42-aa02-f0fa44ae8057
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254676415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1254676415
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3929212749
Short name T155
Test name
Test status
Simulation time 670697498 ps
CPU time 5.53 seconds
Started Jun 07 07:39:05 PM PDT 24
Finished Jun 07 07:39:12 PM PDT 24
Peak memory 198044 kb
Host smart-37505eb6-4532-4a87-b064-62159e666568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929212749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3929212749
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1151720292
Short name T601
Test name
Test status
Simulation time 40952796 ps
CPU time 0.96 seconds
Started Jun 07 07:39:06 PM PDT 24
Finished Jun 07 07:39:09 PM PDT 24
Peak memory 196380 kb
Host smart-c37c36d0-0bdd-4312-841f-6d08b1071182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151720292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1151720292
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3642052783
Short name T135
Test name
Test status
Simulation time 178962222 ps
CPU time 1.08 seconds
Started Jun 07 07:39:06 PM PDT 24
Finished Jun 07 07:39:10 PM PDT 24
Peak memory 195612 kb
Host smart-ff686212-a264-4a69-8187-c61da1892352
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642052783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3642052783
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2250764209
Short name T375
Test name
Test status
Simulation time 62221000247 ps
CPU time 125.21 seconds
Started Jun 07 07:39:04 PM PDT 24
Finished Jun 07 07:41:10 PM PDT 24
Peak memory 198308 kb
Host smart-9132de6d-1789-4c54-9354-1ffe799afcef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250764209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2250764209
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2749398941
Short name T107
Test name
Test status
Simulation time 175684615714 ps
CPU time 1240.03 seconds
Started Jun 07 07:39:14 PM PDT 24
Finished Jun 07 07:59:56 PM PDT 24
Peak memory 198304 kb
Host smart-7d4acecd-2a24-4540-925a-edda68010df2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2749398941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2749398941
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1765352036
Short name T277
Test name
Test status
Simulation time 44915316 ps
CPU time 0.55 seconds
Started Jun 07 07:39:14 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 193952 kb
Host smart-e85bb672-13fa-48d5-9bbb-40a20a57da9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765352036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1765352036
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.378057601
Short name T669
Test name
Test status
Simulation time 55086525 ps
CPU time 0.66 seconds
Started Jun 07 07:39:15 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 194984 kb
Host smart-100f3756-666d-4c53-b018-0f71691109b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378057601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.378057601
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3795126540
Short name T556
Test name
Test status
Simulation time 115659907 ps
CPU time 5.83 seconds
Started Jun 07 07:39:12 PM PDT 24
Finished Jun 07 07:39:20 PM PDT 24
Peak memory 195436 kb
Host smart-0eba2309-f2c4-4a17-af2b-13a8eac8d46a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795126540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3795126540
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.79762694
Short name T20
Test name
Test status
Simulation time 191402486 ps
CPU time 0.98 seconds
Started Jun 07 07:39:12 PM PDT 24
Finished Jun 07 07:39:15 PM PDT 24
Peak memory 196456 kb
Host smart-d6ab4d39-0b61-4f9a-bb6d-d94839283050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79762694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.79762694
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1886352371
Short name T126
Test name
Test status
Simulation time 96067144 ps
CPU time 1.25 seconds
Started Jun 07 07:39:12 PM PDT 24
Finished Jun 07 07:39:16 PM PDT 24
Peak memory 195880 kb
Host smart-a98fafc6-5e4b-4e15-9082-5203c9868f76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886352371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1886352371
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2031581453
Short name T176
Test name
Test status
Simulation time 67590306 ps
CPU time 2.46 seconds
Started Jun 07 07:39:12 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 197340 kb
Host smart-8b77bcd1-9055-4fb2-a074-877ab9f3ec6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031581453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2031581453
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3859339877
Short name T609
Test name
Test status
Simulation time 287251007 ps
CPU time 1.3 seconds
Started Jun 07 07:39:13 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 196976 kb
Host smart-19b83023-2b49-4f2c-967e-00963d613c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859339877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3859339877
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2784961595
Short name T532
Test name
Test status
Simulation time 55468155 ps
CPU time 1.31 seconds
Started Jun 07 07:39:15 PM PDT 24
Finished Jun 07 07:39:18 PM PDT 24
Peak memory 198092 kb
Host smart-756a842e-9e15-48ed-bef4-689612b05526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784961595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2784961595
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1549018823
Short name T285
Test name
Test status
Simulation time 36759006 ps
CPU time 1.15 seconds
Started Jun 07 07:39:13 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 196952 kb
Host smart-c31ba89f-2701-4780-96c0-1b4257fa015d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549018823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1549018823
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.571158833
Short name T454
Test name
Test status
Simulation time 350233512 ps
CPU time 4.54 seconds
Started Jun 07 07:39:14 PM PDT 24
Finished Jun 07 07:39:21 PM PDT 24
Peak memory 198028 kb
Host smart-10c1c902-2f45-418d-a4c2-57c08c00ea14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571158833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.571158833
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3052556581
Short name T645
Test name
Test status
Simulation time 200202591 ps
CPU time 1.4 seconds
Started Jun 07 07:39:12 PM PDT 24
Finished Jun 07 07:39:16 PM PDT 24
Peak memory 196876 kb
Host smart-7092d635-9c4e-42b2-9bc1-67fea3a3e06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052556581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3052556581
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2568943698
Short name T181
Test name
Test status
Simulation time 230739411 ps
CPU time 1.23 seconds
Started Jun 07 07:39:11 PM PDT 24
Finished Jun 07 07:39:15 PM PDT 24
Peak memory 196364 kb
Host smart-798a1ca7-2f0b-4fa7-84d5-51bae500de3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568943698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2568943698
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4289841216
Short name T369
Test name
Test status
Simulation time 8121042481 ps
CPU time 116.38 seconds
Started Jun 07 07:39:09 PM PDT 24
Finished Jun 07 07:41:07 PM PDT 24
Peak memory 198264 kb
Host smart-c3d05841-fe1e-406d-a3b5-89feac5d10c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289841216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4289841216
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1897502560
Short name T290
Test name
Test status
Simulation time 20398696 ps
CPU time 0.58 seconds
Started Jun 07 07:39:20 PM PDT 24
Finished Jun 07 07:39:22 PM PDT 24
Peak memory 194628 kb
Host smart-45593c7b-192b-4669-b82c-db14460e43e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897502560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1897502560
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1607095486
Short name T205
Test name
Test status
Simulation time 106074756 ps
CPU time 0.87 seconds
Started Jun 07 07:39:10 PM PDT 24
Finished Jun 07 07:39:12 PM PDT 24
Peak memory 196240 kb
Host smart-c5928134-c54e-4acb-8bdd-ebc9c423a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607095486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1607095486
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3466252260
Short name T146
Test name
Test status
Simulation time 1297828772 ps
CPU time 22.31 seconds
Started Jun 07 07:39:19 PM PDT 24
Finished Jun 07 07:39:44 PM PDT 24
Peak memory 195588 kb
Host smart-98a4ef2b-6763-4266-af0c-f9d1f0a65353
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466252260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3466252260
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3008114629
Short name T579
Test name
Test status
Simulation time 73858250 ps
CPU time 1.02 seconds
Started Jun 07 07:39:22 PM PDT 24
Finished Jun 07 07:39:25 PM PDT 24
Peak memory 196640 kb
Host smart-0c115f75-4741-4b4f-b9a3-bc8ab9ffeacf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008114629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3008114629
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1790139106
Short name T167
Test name
Test status
Simulation time 161708186 ps
CPU time 1.16 seconds
Started Jun 07 07:39:13 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 195816 kb
Host smart-27b60326-3c9c-45fd-8750-9ab2f08e8a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790139106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1790139106
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2190908292
Short name T150
Test name
Test status
Simulation time 354451121 ps
CPU time 3.78 seconds
Started Jun 07 07:39:19 PM PDT 24
Finished Jun 07 07:39:25 PM PDT 24
Peak memory 197928 kb
Host smart-5a8b2437-9caf-49f3-aff6-f13b144bac74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190908292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2190908292
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3784970719
Short name T141
Test name
Test status
Simulation time 319537876 ps
CPU time 2.39 seconds
Started Jun 07 07:39:20 PM PDT 24
Finished Jun 07 07:39:25 PM PDT 24
Peak memory 197024 kb
Host smart-57b29bba-b666-43fd-a658-abb060823fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784970719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3784970719
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2419650747
Short name T152
Test name
Test status
Simulation time 39447368 ps
CPU time 0.96 seconds
Started Jun 07 07:39:14 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 196064 kb
Host smart-071b7bcd-7fdd-4147-bf7c-4dfa23b47527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419650747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2419650747
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3830840816
Short name T390
Test name
Test status
Simulation time 46020805 ps
CPU time 1.08 seconds
Started Jun 07 07:39:11 PM PDT 24
Finished Jun 07 07:39:14 PM PDT 24
Peak memory 196064 kb
Host smart-7c84d3b2-8fcf-4f99-9f5f-67ab64856de5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830840816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3830840816
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1233922245
Short name T408
Test name
Test status
Simulation time 42240879 ps
CPU time 2.1 seconds
Started Jun 07 07:39:21 PM PDT 24
Finished Jun 07 07:39:26 PM PDT 24
Peak memory 198032 kb
Host smart-6829e92d-98eb-415e-a1c0-ebf4453e9781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233922245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1233922245
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3288301792
Short name T428
Test name
Test status
Simulation time 35262613 ps
CPU time 0.9 seconds
Started Jun 07 07:39:18 PM PDT 24
Finished Jun 07 07:39:20 PM PDT 24
Peak memory 195436 kb
Host smart-fdcbaf74-eb7b-44cc-8e2a-ba46b197adb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288301792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3288301792
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2523021810
Short name T437
Test name
Test status
Simulation time 198592530 ps
CPU time 1.12 seconds
Started Jun 07 07:39:12 PM PDT 24
Finished Jun 07 07:39:16 PM PDT 24
Peak memory 195516 kb
Host smart-81426f5f-0ed1-4d13-94ba-f656b57a3307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523021810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2523021810
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3895522002
Short name T545
Test name
Test status
Simulation time 19506780441 ps
CPU time 75.63 seconds
Started Jun 07 07:39:20 PM PDT 24
Finished Jun 07 07:40:38 PM PDT 24
Peak memory 198156 kb
Host smart-d4cd1143-fb39-471b-b03a-0efdfca45563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895522002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3895522002
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3243896320
Short name T154
Test name
Test status
Simulation time 49168969 ps
CPU time 0.55 seconds
Started Jun 07 07:39:27 PM PDT 24
Finished Jun 07 07:39:30 PM PDT 24
Peak memory 193932 kb
Host smart-36ebf536-b868-4a85-802e-07b7bb17d022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243896320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3243896320
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3352272219
Short name T174
Test name
Test status
Simulation time 190622057 ps
CPU time 0.86 seconds
Started Jun 07 07:39:19 PM PDT 24
Finished Jun 07 07:39:22 PM PDT 24
Peak memory 195444 kb
Host smart-29ea182e-3ab1-49bf-9887-330df44e007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352272219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3352272219
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1042141212
Short name T313
Test name
Test status
Simulation time 1433465974 ps
CPU time 18.36 seconds
Started Jun 07 07:39:29 PM PDT 24
Finished Jun 07 07:39:49 PM PDT 24
Peak memory 195588 kb
Host smart-e185cdcb-9a15-4f66-9053-20dfb291cc98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042141212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1042141212
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3596085371
Short name T8
Test name
Test status
Simulation time 141382165 ps
CPU time 0.74 seconds
Started Jun 07 07:39:28 PM PDT 24
Finished Jun 07 07:39:31 PM PDT 24
Peak memory 195860 kb
Host smart-3159260e-8d91-45f7-8dbd-7084a757aff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596085371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3596085371
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3355867745
Short name T134
Test name
Test status
Simulation time 72468815 ps
CPU time 1.1 seconds
Started Jun 07 07:39:19 PM PDT 24
Finished Jun 07 07:39:22 PM PDT 24
Peak memory 196164 kb
Host smart-600cb3f7-a055-4fb1-a98d-31bc7fb0e7b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355867745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3355867745
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3153182631
Short name T190
Test name
Test status
Simulation time 582240500 ps
CPU time 2.35 seconds
Started Jun 07 07:39:21 PM PDT 24
Finished Jun 07 07:39:26 PM PDT 24
Peak memory 198060 kb
Host smart-2a0177b2-5bee-423b-8200-1979f28b29ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153182631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3153182631
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.106641933
Short name T321
Test name
Test status
Simulation time 103416988 ps
CPU time 1.09 seconds
Started Jun 07 07:39:20 PM PDT 24
Finished Jun 07 07:39:24 PM PDT 24
Peak memory 195572 kb
Host smart-b7e79497-1962-49a9-b126-961d58014a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106641933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
106641933
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.646387198
Short name T232
Test name
Test status
Simulation time 305360932 ps
CPU time 0.83 seconds
Started Jun 07 07:39:22 PM PDT 24
Finished Jun 07 07:39:25 PM PDT 24
Peak memory 196716 kb
Host smart-088fbcbe-81e7-49f0-90b0-6b80d84f52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646387198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.646387198
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.421863274
Short name T552
Test name
Test status
Simulation time 49673742 ps
CPU time 0.76 seconds
Started Jun 07 07:39:22 PM PDT 24
Finished Jun 07 07:39:25 PM PDT 24
Peak memory 196264 kb
Host smart-f92b0b17-de39-4df0-bad8-80f0e4a46661
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421863274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.421863274
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4097044700
Short name T608
Test name
Test status
Simulation time 869728688 ps
CPU time 5.6 seconds
Started Jun 07 07:39:27 PM PDT 24
Finished Jun 07 07:39:34 PM PDT 24
Peak memory 198032 kb
Host smart-26f3bdee-c9c3-40cc-b82b-83feefbaed00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097044700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4097044700
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3491212108
Short name T722
Test name
Test status
Simulation time 89315837 ps
CPU time 1.11 seconds
Started Jun 07 07:39:20 PM PDT 24
Finished Jun 07 07:39:23 PM PDT 24
Peak memory 195872 kb
Host smart-ec977401-df40-487e-bdc9-e2572015ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491212108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3491212108
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4158925394
Short name T377
Test name
Test status
Simulation time 134171042 ps
CPU time 1.14 seconds
Started Jun 07 07:39:19 PM PDT 24
Finished Jun 07 07:39:22 PM PDT 24
Peak memory 198048 kb
Host smart-ae6d0c2e-6447-4919-b39e-8e3f3fec16bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158925394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4158925394
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3422472563
Short name T195
Test name
Test status
Simulation time 6952918139 ps
CPU time 83.7 seconds
Started Jun 07 07:39:29 PM PDT 24
Finished Jun 07 07:40:55 PM PDT 24
Peak memory 198240 kb
Host smart-705a43e0-2941-4d6c-bbc0-e86623764a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422472563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3422472563
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4173653862
Short name T60
Test name
Test status
Simulation time 45927575266 ps
CPU time 566.03 seconds
Started Jun 07 07:39:28 PM PDT 24
Finished Jun 07 07:48:55 PM PDT 24
Peak memory 198316 kb
Host smart-c9bf2fdb-0f72-4cb2-b532-c3ab1dece893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4173653862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4173653862
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1360396750
Short name T130
Test name
Test status
Simulation time 16793885 ps
CPU time 0.6 seconds
Started Jun 07 07:39:35 PM PDT 24
Finished Jun 07 07:39:38 PM PDT 24
Peak memory 194172 kb
Host smart-c93ede9d-534f-4f26-9190-1eece248c3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360396750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1360396750
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2787099914
Short name T443
Test name
Test status
Simulation time 21618399 ps
CPU time 0.74 seconds
Started Jun 07 07:39:36 PM PDT 24
Finished Jun 07 07:39:40 PM PDT 24
Peak memory 195260 kb
Host smart-38878cb8-7bef-4469-af19-4d0ea56d691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787099914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2787099914
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1840111311
Short name T381
Test name
Test status
Simulation time 809868759 ps
CPU time 28.21 seconds
Started Jun 07 07:39:27 PM PDT 24
Finished Jun 07 07:39:56 PM PDT 24
Peak memory 196916 kb
Host smart-cfeb6596-d72d-47f1-a0bd-34f3ae9174b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840111311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1840111311
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.775511177
Short name T584
Test name
Test status
Simulation time 112933633 ps
CPU time 0.77 seconds
Started Jun 07 07:39:27 PM PDT 24
Finished Jun 07 07:39:30 PM PDT 24
Peak memory 195892 kb
Host smart-3a1056b8-45b0-40ab-bb06-b7ac43845918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775511177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.775511177
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2373414019
Short name T317
Test name
Test status
Simulation time 60603104 ps
CPU time 0.69 seconds
Started Jun 07 07:39:35 PM PDT 24
Finished Jun 07 07:39:37 PM PDT 24
Peak memory 194396 kb
Host smart-967256af-cdff-4164-ba60-5287eb98881c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373414019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2373414019
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.259118720
Short name T245
Test name
Test status
Simulation time 271199565 ps
CPU time 2.66 seconds
Started Jun 07 07:39:27 PM PDT 24
Finished Jun 07 07:39:32 PM PDT 24
Peak memory 198076 kb
Host smart-a1f5d720-22b0-4717-a680-fa17e8ad569b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259118720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.259118720
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1573632841
Short name T323
Test name
Test status
Simulation time 193062411 ps
CPU time 1.98 seconds
Started Jun 07 07:39:26 PM PDT 24
Finished Jun 07 07:39:29 PM PDT 24
Peak memory 195840 kb
Host smart-f2f6c91b-0d40-4e0d-9f25-fe89edfe09e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573632841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1573632841
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2766814397
Short name T175
Test name
Test status
Simulation time 85072241 ps
CPU time 0.98 seconds
Started Jun 07 07:39:31 PM PDT 24
Finished Jun 07 07:39:34 PM PDT 24
Peak memory 196072 kb
Host smart-36fa5afa-082c-4485-bd1c-5633971db934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766814397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2766814397
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4246153560
Short name T70
Test name
Test status
Simulation time 32536536 ps
CPU time 1.1 seconds
Started Jun 07 07:39:30 PM PDT 24
Finished Jun 07 07:39:33 PM PDT 24
Peak memory 196112 kb
Host smart-2c046a9b-e519-4347-8008-26528d25c958
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246153560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4246153560
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2607344016
Short name T398
Test name
Test status
Simulation time 1096481718 ps
CPU time 4.34 seconds
Started Jun 07 07:39:30 PM PDT 24
Finished Jun 07 07:39:37 PM PDT 24
Peak memory 198020 kb
Host smart-2a6239a7-713f-4842-b92b-f5c90bcd027e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607344016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2607344016
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.620963029
Short name T64
Test name
Test status
Simulation time 34557279 ps
CPU time 1.07 seconds
Started Jun 07 07:39:27 PM PDT 24
Finished Jun 07 07:39:30 PM PDT 24
Peak memory 195520 kb
Host smart-461b64b9-e17a-42c8-90fa-da6df0ec5869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620963029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.620963029
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.915382569
Short name T712
Test name
Test status
Simulation time 63756908 ps
CPU time 1.16 seconds
Started Jun 07 07:39:29 PM PDT 24
Finished Jun 07 07:39:33 PM PDT 24
Peak memory 196296 kb
Host smart-6eb8b786-57ca-4b9e-a382-b85d81200e77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915382569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.915382569
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1601494233
Short name T578
Test name
Test status
Simulation time 64583553918 ps
CPU time 145.56 seconds
Started Jun 07 07:39:29 PM PDT 24
Finished Jun 07 07:41:56 PM PDT 24
Peak memory 198204 kb
Host smart-af0cf7b3-f9e5-4351-a25a-e8620d4fca93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601494233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1601494233
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.704244966
Short name T460
Test name
Test status
Simulation time 46167778 ps
CPU time 0.58 seconds
Started Jun 07 07:39:40 PM PDT 24
Finished Jun 07 07:39:42 PM PDT 24
Peak memory 194828 kb
Host smart-55359652-03fd-4d16-8355-4382b6161d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704244966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.704244966
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2301519715
Short name T695
Test name
Test status
Simulation time 46901969 ps
CPU time 0.61 seconds
Started Jun 07 07:39:37 PM PDT 24
Finished Jun 07 07:39:40 PM PDT 24
Peak memory 194668 kb
Host smart-8c710bcc-b57e-4027-8ad8-69042745a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301519715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2301519715
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3938145053
Short name T206
Test name
Test status
Simulation time 237579419 ps
CPU time 11.62 seconds
Started Jun 07 07:39:40 PM PDT 24
Finished Jun 07 07:39:53 PM PDT 24
Peak memory 196880 kb
Host smart-2ba57705-a8df-4700-9ec3-1e898f8ad791
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938145053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3938145053
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.528034788
Short name T476
Test name
Test status
Simulation time 44602426 ps
CPU time 0.79 seconds
Started Jun 07 07:39:38 PM PDT 24
Finished Jun 07 07:39:41 PM PDT 24
Peak memory 195916 kb
Host smart-241104e2-fe36-4026-abe5-f510cac3973c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528034788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.528034788
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3429884391
Short name T564
Test name
Test status
Simulation time 132022694 ps
CPU time 1.03 seconds
Started Jun 07 07:39:33 PM PDT 24
Finished Jun 07 07:39:36 PM PDT 24
Peak memory 195844 kb
Host smart-45b0999f-db95-4f6d-9f99-ee3e76ec9e2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429884391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3429884391
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3806627000
Short name T555
Test name
Test status
Simulation time 148384274 ps
CPU time 1.65 seconds
Started Jun 07 07:39:34 PM PDT 24
Finished Jun 07 07:39:38 PM PDT 24
Peak memory 198172 kb
Host smart-a9cd9927-a387-4322-9dc9-22d4804993f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806627000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3806627000
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1075209398
Short name T217
Test name
Test status
Simulation time 42645884 ps
CPU time 1.4 seconds
Started Jun 07 07:39:33 PM PDT 24
Finished Jun 07 07:39:37 PM PDT 24
Peak memory 196952 kb
Host smart-984b66a6-cc6f-4605-9b56-933473d9e44d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075209398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1075209398
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1641063647
Short name T301
Test name
Test status
Simulation time 29238793 ps
CPU time 0.81 seconds
Started Jun 07 07:39:34 PM PDT 24
Finished Jun 07 07:39:37 PM PDT 24
Peak memory 195564 kb
Host smart-901135af-4efe-45df-a058-7dac98725691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641063647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1641063647
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2032777628
Short name T236
Test name
Test status
Simulation time 35067307 ps
CPU time 1.31 seconds
Started Jun 07 07:39:37 PM PDT 24
Finished Jun 07 07:39:40 PM PDT 24
Peak memory 197080 kb
Host smart-8ecf507a-aa7a-41c2-be20-f409d59fe0e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032777628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2032777628
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1720252210
Short name T709
Test name
Test status
Simulation time 224453008 ps
CPU time 3.74 seconds
Started Jun 07 07:39:39 PM PDT 24
Finished Jun 07 07:39:45 PM PDT 24
Peak memory 198044 kb
Host smart-5a066603-95e6-4f04-8513-eeba1f20eb40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720252210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1720252210
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.177034106
Short name T597
Test name
Test status
Simulation time 65354073 ps
CPU time 1.27 seconds
Started Jun 07 07:39:35 PM PDT 24
Finished Jun 07 07:39:38 PM PDT 24
Peak memory 195700 kb
Host smart-8a97d6c4-c046-430a-bb60-e97325afa446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177034106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.177034106
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2029497008
Short name T498
Test name
Test status
Simulation time 156724267 ps
CPU time 1.17 seconds
Started Jun 07 07:39:34 PM PDT 24
Finished Jun 07 07:39:38 PM PDT 24
Peak memory 195856 kb
Host smart-1b7d9ab1-e792-4c8b-8ae6-6cd4da785a7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029497008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2029497008
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3348866298
Short name T514
Test name
Test status
Simulation time 7243080855 ps
CPU time 80.3 seconds
Started Jun 07 07:39:37 PM PDT 24
Finished Jun 07 07:40:59 PM PDT 24
Peak memory 198180 kb
Host smart-d0542897-b984-4e18-94b3-b386e8747d71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348866298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3348866298
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4277269644
Short name T295
Test name
Test status
Simulation time 259759186473 ps
CPU time 1525.91 seconds
Started Jun 07 07:39:38 PM PDT 24
Finished Jun 07 08:05:06 PM PDT 24
Peak memory 198264 kb
Host smart-b8a07a61-2c9c-4d1f-8754-ad8d06d71226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4277269644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4277269644
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.767422257
Short name T570
Test name
Test status
Simulation time 19405490 ps
CPU time 0.57 seconds
Started Jun 07 07:35:49 PM PDT 24
Finished Jun 07 07:35:52 PM PDT 24
Peak memory 193928 kb
Host smart-2ee1c1f7-9fb1-4549-9c57-f95c9528fe58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767422257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.767422257
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3832919474
Short name T157
Test name
Test status
Simulation time 26620321 ps
CPU time 0.78 seconds
Started Jun 07 07:35:43 PM PDT 24
Finished Jun 07 07:35:46 PM PDT 24
Peak memory 195984 kb
Host smart-53689235-dbdd-45e1-88d7-08c3f44fee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832919474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3832919474
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.182494845
Short name T335
Test name
Test status
Simulation time 1631227237 ps
CPU time 28.71 seconds
Started Jun 07 07:35:49 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 196708 kb
Host smart-886d894e-1fa8-47fe-b350-f6ce5dd4736a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182494845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.182494845
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3599790460
Short name T286
Test name
Test status
Simulation time 82551641 ps
CPU time 1.05 seconds
Started Jun 07 07:35:49 PM PDT 24
Finished Jun 07 07:35:52 PM PDT 24
Peak memory 196396 kb
Host smart-bf8b5369-9389-47e7-93f1-f406af301d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599790460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3599790460
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2561907630
Short name T389
Test name
Test status
Simulation time 303346894 ps
CPU time 1.39 seconds
Started Jun 07 07:35:42 PM PDT 24
Finished Jun 07 07:35:46 PM PDT 24
Peak memory 198144 kb
Host smart-7b43dc2f-f364-4471-9951-117ddf69eeb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561907630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2561907630
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3804892535
Short name T640
Test name
Test status
Simulation time 166194091 ps
CPU time 3.15 seconds
Started Jun 07 07:35:50 PM PDT 24
Finished Jun 07 07:35:56 PM PDT 24
Peak memory 198092 kb
Host smart-43afab42-4348-4a87-a8b7-c8d10354ef8a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804892535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3804892535
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3642139315
Short name T455
Test name
Test status
Simulation time 850891423 ps
CPU time 2.45 seconds
Started Jun 07 07:35:50 PM PDT 24
Finished Jun 07 07:35:55 PM PDT 24
Peak memory 196588 kb
Host smart-80bec5a3-fe53-41c3-9a96-7a86876c11cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642139315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3642139315
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3050321673
Short name T586
Test name
Test status
Simulation time 44222226 ps
CPU time 0.89 seconds
Started Jun 07 07:35:42 PM PDT 24
Finished Jun 07 07:35:45 PM PDT 24
Peak memory 196516 kb
Host smart-a8b52ce4-73d9-410a-983a-bba1b8e82b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050321673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3050321673
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.4004607743
Short name T541
Test name
Test status
Simulation time 51453384 ps
CPU time 1.11 seconds
Started Jun 07 07:35:41 PM PDT 24
Finished Jun 07 07:35:45 PM PDT 24
Peak memory 196784 kb
Host smart-85288da8-ab85-4a6a-a050-6ab858a37b90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004607743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.4004607743
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3989257420
Short name T3
Test name
Test status
Simulation time 260876135 ps
CPU time 4.07 seconds
Started Jun 07 07:35:50 PM PDT 24
Finished Jun 07 07:35:56 PM PDT 24
Peak memory 198040 kb
Host smart-9f794307-40a8-4759-ad60-02eca92de071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989257420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3989257420
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2453839806
Short name T47
Test name
Test status
Simulation time 78801795 ps
CPU time 0.94 seconds
Started Jun 07 07:35:54 PM PDT 24
Finished Jun 07 07:35:57 PM PDT 24
Peak memory 215036 kb
Host smart-069a514e-a2b7-4185-9e6b-60a14f22017c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453839806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2453839806
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3175313018
Short name T288
Test name
Test status
Simulation time 57292812 ps
CPU time 1.14 seconds
Started Jun 07 07:35:43 PM PDT 24
Finished Jun 07 07:35:47 PM PDT 24
Peak memory 195704 kb
Host smart-cc29113d-51d0-42be-9207-2c4f24b0a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175313018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3175313018
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3080189925
Short name T221
Test name
Test status
Simulation time 134130469 ps
CPU time 1.16 seconds
Started Jun 07 07:35:43 PM PDT 24
Finished Jun 07 07:35:48 PM PDT 24
Peak memory 195836 kb
Host smart-8c324ce0-2903-45be-8d24-87213ef955e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080189925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3080189925
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3283974475
Short name T171
Test name
Test status
Simulation time 22772101461 ps
CPU time 42.26 seconds
Started Jun 07 07:35:50 PM PDT 24
Finished Jun 07 07:36:35 PM PDT 24
Peak memory 198252 kb
Host smart-bd7fc2d2-e0ea-4065-9f19-afcdab0bffcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283974475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3283974475
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3736766939
Short name T147
Test name
Test status
Simulation time 13107482 ps
CPU time 0.57 seconds
Started Jun 07 07:39:43 PM PDT 24
Finished Jun 07 07:39:45 PM PDT 24
Peak memory 194988 kb
Host smart-65a412f3-4be2-4182-b26c-9cb8478ade3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736766939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3736766939
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3458199021
Short name T562
Test name
Test status
Simulation time 26494087 ps
CPU time 0.66 seconds
Started Jun 07 07:39:37 PM PDT 24
Finished Jun 07 07:39:40 PM PDT 24
Peak memory 194184 kb
Host smart-ba642a0d-f2e7-463e-845c-20bbd0e7a763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458199021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3458199021
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2690190789
Short name T606
Test name
Test status
Simulation time 733282490 ps
CPU time 19.47 seconds
Started Jun 07 07:39:46 PM PDT 24
Finished Jun 07 07:40:07 PM PDT 24
Peak memory 198076 kb
Host smart-06cb0ed6-ce93-4e62-afcb-d5d4da2c265d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690190789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2690190789
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.874117849
Short name T228
Test name
Test status
Simulation time 19363042 ps
CPU time 0.61 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:39:46 PM PDT 24
Peak memory 195088 kb
Host smart-faacaa93-a955-4ec6-8027-d5a5779c1345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874117849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.874117849
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.736280223
Short name T713
Test name
Test status
Simulation time 75131627 ps
CPU time 1.34 seconds
Started Jun 07 07:39:46 PM PDT 24
Finished Jun 07 07:39:49 PM PDT 24
Peak memory 198120 kb
Host smart-9e61bf8a-4273-45ac-9f81-5ef17e482495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736280223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.736280223
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1332418728
Short name T511
Test name
Test status
Simulation time 1209051666 ps
CPU time 3.43 seconds
Started Jun 07 07:39:48 PM PDT 24
Finished Jun 07 07:39:52 PM PDT 24
Peak memory 198176 kb
Host smart-e3ddcee8-bef1-411c-907c-c7508e187d34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332418728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1332418728
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2132021791
Short name T626
Test name
Test status
Simulation time 177623080 ps
CPU time 2.89 seconds
Started Jun 07 07:39:43 PM PDT 24
Finished Jun 07 07:39:48 PM PDT 24
Peak memory 197032 kb
Host smart-766832e7-ef19-4a29-9e99-09b67d6b2f1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132021791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2132021791
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.221517578
Short name T222
Test name
Test status
Simulation time 119958192 ps
CPU time 1.32 seconds
Started Jun 07 07:39:38 PM PDT 24
Finished Jun 07 07:39:41 PM PDT 24
Peak memory 198120 kb
Host smart-67793ff0-79e2-4584-a19c-a1a7396dc788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221517578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.221517578
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2447016568
Short name T66
Test name
Test status
Simulation time 18088952 ps
CPU time 0.68 seconds
Started Jun 07 07:39:35 PM PDT 24
Finished Jun 07 07:39:38 PM PDT 24
Peak memory 194336 kb
Host smart-e3db8581-9d46-43c8-bbec-fe3283363985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447016568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2447016568
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4149598957
Short name T9
Test name
Test status
Simulation time 922357258 ps
CPU time 5.68 seconds
Started Jun 07 07:39:45 PM PDT 24
Finished Jun 07 07:39:52 PM PDT 24
Peak memory 198044 kb
Host smart-f1a15ba0-2b91-4626-94d5-dbd8027a3fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149598957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4149598957
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2489971585
Short name T271
Test name
Test status
Simulation time 58158450 ps
CPU time 1.04 seconds
Started Jun 07 07:39:35 PM PDT 24
Finished Jun 07 07:39:38 PM PDT 24
Peak memory 195708 kb
Host smart-233f4bad-4479-4211-a7af-a16764b736c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489971585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2489971585
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1507253937
Short name T602
Test name
Test status
Simulation time 83850174 ps
CPU time 1.31 seconds
Started Jun 07 07:39:36 PM PDT 24
Finished Jun 07 07:39:39 PM PDT 24
Peak memory 195576 kb
Host smart-06909a04-9ad6-4d9a-bf64-7eac0ae6d4c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507253937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1507253937
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3249920285
Short name T661
Test name
Test status
Simulation time 4866270577 ps
CPU time 143.84 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:42:09 PM PDT 24
Peak memory 198248 kb
Host smart-da0cd5d9-90df-4808-b02e-2c5faf2c96bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249920285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3249920285
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.762884165
Short name T78
Test name
Test status
Simulation time 229433015804 ps
CPU time 1204.37 seconds
Started Jun 07 07:39:46 PM PDT 24
Finished Jun 07 07:59:52 PM PDT 24
Peak memory 198268 kb
Host smart-d026e8a8-d40f-4dd8-abdd-ce6cd32bbf7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=762884165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.762884165
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3884212261
Short name T546
Test name
Test status
Simulation time 40013391 ps
CPU time 0.58 seconds
Started Jun 07 07:39:56 PM PDT 24
Finished Jun 07 07:39:58 PM PDT 24
Peak memory 193064 kb
Host smart-c60ab48f-6e6b-4eac-ae16-4b687ad02185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884212261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3884212261
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2265572985
Short name T704
Test name
Test status
Simulation time 57413308 ps
CPU time 0.67 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:39:47 PM PDT 24
Peak memory 194988 kb
Host smart-81997647-d88e-4f3d-8752-fa226d8a6971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265572985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2265572985
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1036664164
Short name T273
Test name
Test status
Simulation time 2647345527 ps
CPU time 23.38 seconds
Started Jun 07 07:39:55 PM PDT 24
Finished Jun 07 07:40:20 PM PDT 24
Peak memory 197708 kb
Host smart-e39944ea-68c0-4589-b8aa-28b1e364ed56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036664164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1036664164
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.4230875186
Short name T447
Test name
Test status
Simulation time 32797243 ps
CPU time 0.62 seconds
Started Jun 07 07:39:52 PM PDT 24
Finished Jun 07 07:39:54 PM PDT 24
Peak memory 195252 kb
Host smart-d593f145-e3fa-40e0-83ef-285fca6cf6ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230875186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.4230875186
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3752077858
Short name T411
Test name
Test status
Simulation time 36052366 ps
CPU time 0.83 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:39:46 PM PDT 24
Peak memory 196212 kb
Host smart-a0412069-de20-4169-96b0-66d6d8108e89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752077858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3752077858
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.332694394
Short name T262
Test name
Test status
Simulation time 218852416 ps
CPU time 2.06 seconds
Started Jun 07 07:39:46 PM PDT 24
Finished Jun 07 07:39:50 PM PDT 24
Peak memory 198084 kb
Host smart-8b48a143-180c-4341-bae0-9bfce796b674
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332694394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.332694394
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.4031492485
Short name T412
Test name
Test status
Simulation time 34849276 ps
CPU time 1.12 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:39:46 PM PDT 24
Peak memory 195612 kb
Host smart-2089672f-d383-452d-af64-5f424605a71d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031492485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.4031492485
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3663396501
Short name T132
Test name
Test status
Simulation time 16304190 ps
CPU time 0.67 seconds
Started Jun 07 07:39:47 PM PDT 24
Finished Jun 07 07:39:48 PM PDT 24
Peak memory 195300 kb
Host smart-85b67720-21cd-425c-a02c-9c7c61e199ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663396501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3663396501
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3071520537
Short name T519
Test name
Test status
Simulation time 56757275 ps
CPU time 0.77 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:39:46 PM PDT 24
Peak memory 195528 kb
Host smart-69571bb7-d1fe-4ecf-a39c-a4facd651d0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071520537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3071520537
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1871557201
Short name T10
Test name
Test status
Simulation time 1548003304 ps
CPU time 4.28 seconds
Started Jun 07 07:39:52 PM PDT 24
Finished Jun 07 07:39:58 PM PDT 24
Peak memory 198032 kb
Host smart-189f329b-cf75-4c74-a9d4-a067947a3f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871557201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1871557201
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4145568409
Short name T210
Test name
Test status
Simulation time 95172851 ps
CPU time 1.36 seconds
Started Jun 07 07:39:44 PM PDT 24
Finished Jun 07 07:39:47 PM PDT 24
Peak memory 195572 kb
Host smart-980a9df9-5576-45c1-b750-a8bed17a6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145568409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4145568409
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2952418434
Short name T566
Test name
Test status
Simulation time 143552536 ps
CPU time 1.17 seconds
Started Jun 07 07:39:43 PM PDT 24
Finished Jun 07 07:39:46 PM PDT 24
Peak memory 195908 kb
Host smart-b60dae57-287c-4a72-b421-73f140210036
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952418434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2952418434
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.384079444
Short name T348
Test name
Test status
Simulation time 4429749466 ps
CPU time 45.61 seconds
Started Jun 07 07:39:54 PM PDT 24
Finished Jun 07 07:40:41 PM PDT 24
Peak memory 198260 kb
Host smart-fbea9ac6-d1bc-4198-9d07-49a378ca1e31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384079444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.384079444
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3601885578
Short name T459
Test name
Test status
Simulation time 24400001 ps
CPU time 0.59 seconds
Started Jun 07 07:40:00 PM PDT 24
Finished Jun 07 07:40:04 PM PDT 24
Peak memory 193988 kb
Host smart-c85f509b-d8ca-4485-b402-fe94523494fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601885578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3601885578
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4087237786
Short name T418
Test name
Test status
Simulation time 166232344 ps
CPU time 0.95 seconds
Started Jun 07 07:39:51 PM PDT 24
Finished Jun 07 07:39:53 PM PDT 24
Peak memory 196668 kb
Host smart-d86dc729-6f5c-4e4d-ae36-0aa4e5970c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087237786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4087237786
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2968863217
Short name T438
Test name
Test status
Simulation time 627897997 ps
CPU time 18.42 seconds
Started Jun 07 07:39:50 PM PDT 24
Finished Jun 07 07:40:10 PM PDT 24
Peak memory 197188 kb
Host smart-8e90407d-fa01-4107-9d70-7518ebe9130a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968863217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2968863217
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3397916027
Short name T621
Test name
Test status
Simulation time 105532678 ps
CPU time 1.05 seconds
Started Jun 07 07:39:51 PM PDT 24
Finished Jun 07 07:39:54 PM PDT 24
Peak memory 196584 kb
Host smart-b6deb60d-5ae0-483d-8989-814c641d46be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397916027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3397916027
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2302854631
Short name T652
Test name
Test status
Simulation time 52792537 ps
CPU time 0.9 seconds
Started Jun 07 07:39:55 PM PDT 24
Finished Jun 07 07:39:58 PM PDT 24
Peak memory 196868 kb
Host smart-c02cd5ec-a29e-4f26-b268-a2559af63290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302854631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2302854631
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.398159842
Short name T183
Test name
Test status
Simulation time 84528106 ps
CPU time 0.97 seconds
Started Jun 07 07:39:56 PM PDT 24
Finished Jun 07 07:39:59 PM PDT 24
Peak memory 195440 kb
Host smart-ac04b464-d8cd-47d0-a3af-12ae3907d4ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398159842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.398159842
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1443593574
Short name T202
Test name
Test status
Simulation time 146709667 ps
CPU time 1.2 seconds
Started Jun 07 07:39:52 PM PDT 24
Finished Jun 07 07:39:55 PM PDT 24
Peak memory 196288 kb
Host smart-a6a9e076-6dc7-4b2b-8009-51a74d5b56a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443593574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1443593574
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1371502309
Short name T357
Test name
Test status
Simulation time 112047410 ps
CPU time 1.17 seconds
Started Jun 07 07:39:52 PM PDT 24
Finished Jun 07 07:39:55 PM PDT 24
Peak memory 196644 kb
Host smart-c220eabc-772f-4d1b-af39-2be1813a81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371502309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1371502309
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2981451852
Short name T279
Test name
Test status
Simulation time 31635564 ps
CPU time 0.77 seconds
Started Jun 07 07:39:52 PM PDT 24
Finished Jun 07 07:39:54 PM PDT 24
Peak memory 195496 kb
Host smart-0f116ddc-58d0-4331-93c6-41daa1b283de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981451852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2981451852
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1936894688
Short name T65
Test name
Test status
Simulation time 649390635 ps
CPU time 2.85 seconds
Started Jun 07 07:39:53 PM PDT 24
Finished Jun 07 07:39:57 PM PDT 24
Peak memory 198004 kb
Host smart-e6a92ce8-6a24-4e60-8974-2e943710972f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936894688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1936894688
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2671611536
Short name T177
Test name
Test status
Simulation time 157076934 ps
CPU time 0.93 seconds
Started Jun 07 07:39:50 PM PDT 24
Finished Jun 07 07:39:52 PM PDT 24
Peak memory 196364 kb
Host smart-4f4a47ea-9e82-4739-8dce-d75ff83667fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671611536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2671611536
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.4001968904
Short name T158
Test name
Test status
Simulation time 80165066 ps
CPU time 1.25 seconds
Started Jun 07 07:39:51 PM PDT 24
Finished Jun 07 07:39:54 PM PDT 24
Peak memory 195628 kb
Host smart-51c153fb-9393-4a3b-a7a1-af97961e453b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001968904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.4001968904
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3638720513
Short name T682
Test name
Test status
Simulation time 6039187006 ps
CPU time 163.9 seconds
Started Jun 07 07:39:57 PM PDT 24
Finished Jun 07 07:42:43 PM PDT 24
Peak memory 198176 kb
Host smart-56c9d27a-4c5e-4529-bcb6-dcf0365235cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638720513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3638720513
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2333823383
Short name T617
Test name
Test status
Simulation time 82367041792 ps
CPU time 748.94 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:52:30 PM PDT 24
Peak memory 198296 kb
Host smart-77c8fdd5-ce2c-4c70-b3d4-2f2f83b3e718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2333823383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2333823383
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3367981449
Short name T478
Test name
Test status
Simulation time 15259348 ps
CPU time 0.58 seconds
Started Jun 07 07:40:00 PM PDT 24
Finished Jun 07 07:40:05 PM PDT 24
Peak memory 194644 kb
Host smart-3114346a-5acc-4687-832c-aeab9a7c95c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367981449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3367981449
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3864725856
Short name T548
Test name
Test status
Simulation time 16106570 ps
CPU time 0.66 seconds
Started Jun 07 07:39:59 PM PDT 24
Finished Jun 07 07:40:04 PM PDT 24
Peak memory 194160 kb
Host smart-ae9ea013-2331-4f17-b914-d4b2d0259f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864725856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3864725856
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.9718348
Short name T347
Test name
Test status
Simulation time 830341606 ps
CPU time 25.8 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:40:28 PM PDT 24
Peak memory 197176 kb
Host smart-76e7c3e1-4e05-4ee5-9012-e3d587355205
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9718348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stress.9718348
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.82462688
Short name T409
Test name
Test status
Simulation time 26157908 ps
CPU time 0.66 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:40:02 PM PDT 24
Peak memory 195240 kb
Host smart-96e53935-0b9e-4686-b33d-80a7c3e2aac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82462688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.82462688
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.851253495
Short name T246
Test name
Test status
Simulation time 288431509 ps
CPU time 1.2 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:40:02 PM PDT 24
Peak memory 196776 kb
Host smart-bc064928-9a07-4a8c-963d-328431590825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851253495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.851253495
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3187392977
Short name T353
Test name
Test status
Simulation time 491006086 ps
CPU time 3.03 seconds
Started Jun 07 07:39:59 PM PDT 24
Finished Jun 07 07:40:06 PM PDT 24
Peak memory 198112 kb
Host smart-b92c9d72-d9a8-4b18-afa6-88a446298b7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187392977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3187392977
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4142910255
Short name T407
Test name
Test status
Simulation time 83956133 ps
CPU time 0.98 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:40:03 PM PDT 24
Peak memory 196216 kb
Host smart-1a9c7d01-09f1-4032-9f79-968d99ee84c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142910255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4142910255
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2415820565
Short name T165
Test name
Test status
Simulation time 62818112 ps
CPU time 1.31 seconds
Started Jun 07 07:40:01 PM PDT 24
Finished Jun 07 07:40:06 PM PDT 24
Peak memory 198144 kb
Host smart-cf80604d-098f-4997-a610-70932de3d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415820565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2415820565
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1841529966
Short name T278
Test name
Test status
Simulation time 114068476 ps
CPU time 1 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:40:03 PM PDT 24
Peak memory 196760 kb
Host smart-5007d142-401a-4253-aa8f-cbd2dc09e147
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841529966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1841529966
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2185177084
Short name T611
Test name
Test status
Simulation time 313484595 ps
CPU time 3.44 seconds
Started Jun 07 07:39:57 PM PDT 24
Finished Jun 07 07:40:02 PM PDT 24
Peak memory 198108 kb
Host smart-d93d29a8-7e00-4f92-bac1-fc61ae22de86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185177084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2185177084
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2808790166
Short name T386
Test name
Test status
Simulation time 60999627 ps
CPU time 0.94 seconds
Started Jun 07 07:39:57 PM PDT 24
Finished Jun 07 07:40:00 PM PDT 24
Peak memory 196116 kb
Host smart-db2289c8-de4a-45dc-885a-1287bf84aa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808790166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2808790166
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.548330648
Short name T569
Test name
Test status
Simulation time 192828328 ps
CPU time 1.04 seconds
Started Jun 07 07:39:59 PM PDT 24
Finished Jun 07 07:40:04 PM PDT 24
Peak memory 195796 kb
Host smart-83547e7f-7e37-4da1-889d-5d04d24d77f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548330648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.548330648
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1230545802
Short name T21
Test name
Test status
Simulation time 141368899084 ps
CPU time 151.92 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 07:42:34 PM PDT 24
Peak memory 198264 kb
Host smart-29b80ea2-d72e-4779-9982-9ac30acdfe72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230545802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1230545802
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2024199678
Short name T69
Test name
Test status
Simulation time 36288925046 ps
CPU time 1224.62 seconds
Started Jun 07 07:39:58 PM PDT 24
Finished Jun 07 08:00:26 PM PDT 24
Peak memory 198260 kb
Host smart-b11a0fa7-a3e7-44fc-bca6-aaff660ce549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2024199678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2024199678
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.4114297601
Short name T435
Test name
Test status
Simulation time 43624569 ps
CPU time 0.54 seconds
Started Jun 07 07:40:08 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 194848 kb
Host smart-97e6273c-7012-4f35-8fb1-fa29eb0ff070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114297601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4114297601
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2305532893
Short name T392
Test name
Test status
Simulation time 103720098 ps
CPU time 0.78 seconds
Started Jun 07 07:40:06 PM PDT 24
Finished Jun 07 07:40:11 PM PDT 24
Peak memory 195480 kb
Host smart-44741423-7e28-4f06-b9dc-f83af7ba88b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305532893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2305532893
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.50757432
Short name T140
Test name
Test status
Simulation time 827907836 ps
CPU time 22.76 seconds
Started Jun 07 07:40:06 PM PDT 24
Finished Jun 07 07:40:33 PM PDT 24
Peak memory 196860 kb
Host smart-c9d737f1-a42c-4272-8184-05bbae6f8d03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50757432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress
.50757432
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3573316484
Short name T55
Test name
Test status
Simulation time 41415718 ps
CPU time 0.65 seconds
Started Jun 07 07:40:07 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 195296 kb
Host smart-ad14bced-ea05-4437-8e7e-4241925df570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573316484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3573316484
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3168979106
Short name T592
Test name
Test status
Simulation time 57620834 ps
CPU time 1.01 seconds
Started Jun 07 07:40:05 PM PDT 24
Finished Jun 07 07:40:11 PM PDT 24
Peak memory 196160 kb
Host smart-f7b5985b-ffc3-4298-9f75-ef4ed695aaab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168979106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3168979106
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1022053833
Short name T113
Test name
Test status
Simulation time 560506091 ps
CPU time 3.24 seconds
Started Jun 07 07:40:08 PM PDT 24
Finished Jun 07 07:40:15 PM PDT 24
Peak memory 198124 kb
Host smart-d10fecf5-f7b9-4b7f-be34-1f14c62077c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022053833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1022053833
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.43830999
Short name T453
Test name
Test status
Simulation time 113438612 ps
CPU time 2.11 seconds
Started Jun 07 07:40:06 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 196176 kb
Host smart-5d0b9dc5-5bfe-4563-ab63-fd03c2dadfc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43830999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.43830999
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3013977165
Short name T129
Test name
Test status
Simulation time 54190626 ps
CPU time 1.13 seconds
Started Jun 07 07:40:08 PM PDT 24
Finished Jun 07 07:40:13 PM PDT 24
Peak memory 197036 kb
Host smart-a0da4bd9-7f00-4e62-abac-4cdaa0b4b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013977165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3013977165
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1048575795
Short name T599
Test name
Test status
Simulation time 26171018 ps
CPU time 0.8 seconds
Started Jun 07 07:40:06 PM PDT 24
Finished Jun 07 07:40:11 PM PDT 24
Peak memory 196328 kb
Host smart-25e3af4c-a282-49da-9bb4-b9f8ee4286c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048575795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1048575795
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1902791704
Short name T50
Test name
Test status
Simulation time 279368443 ps
CPU time 1.51 seconds
Started Jun 07 07:40:05 PM PDT 24
Finished Jun 07 07:40:11 PM PDT 24
Peak memory 198044 kb
Host smart-24093be6-110e-4dcf-be85-e58af171f599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902791704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1902791704
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1084812928
Short name T689
Test name
Test status
Simulation time 109311830 ps
CPU time 1.28 seconds
Started Jun 07 07:39:59 PM PDT 24
Finished Jun 07 07:40:05 PM PDT 24
Peak memory 196884 kb
Host smart-d7172b3b-01e0-439e-bc1f-d203ad385f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084812928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1084812928
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.919653974
Short name T114
Test name
Test status
Simulation time 40489501 ps
CPU time 1.12 seconds
Started Jun 07 07:39:57 PM PDT 24
Finished Jun 07 07:40:00 PM PDT 24
Peak memory 195620 kb
Host smart-ae3b2911-c8c7-4829-b58e-73a944e0e724
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919653974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.919653974
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3119486292
Short name T325
Test name
Test status
Simulation time 123570885461 ps
CPU time 170.96 seconds
Started Jun 07 07:40:07 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 198252 kb
Host smart-ff3bc496-64ef-4a23-8738-364e02109435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119486292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3119486292
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3581295420
Short name T613
Test name
Test status
Simulation time 47737088 ps
CPU time 0.58 seconds
Started Jun 07 07:40:11 PM PDT 24
Finished Jun 07 07:40:15 PM PDT 24
Peak memory 193932 kb
Host smart-7c1d57d5-b815-4be3-b976-12a1e7ccbb7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581295420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3581295420
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.422941576
Short name T192
Test name
Test status
Simulation time 353641040 ps
CPU time 0.89 seconds
Started Jun 07 07:40:18 PM PDT 24
Finished Jun 07 07:40:20 PM PDT 24
Peak memory 196668 kb
Host smart-43709f70-fbba-4c54-80de-eb3bd19d2574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422941576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.422941576
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2166549078
Short name T216
Test name
Test status
Simulation time 361410422 ps
CPU time 9.77 seconds
Started Jun 07 07:40:11 PM PDT 24
Finished Jun 07 07:40:24 PM PDT 24
Peak memory 195544 kb
Host smart-a094fcab-93ec-42c3-a42c-6ffc6bcfd483
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166549078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2166549078
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3870537409
Short name T641
Test name
Test status
Simulation time 316030794 ps
CPU time 1.06 seconds
Started Jun 07 07:40:17 PM PDT 24
Finished Jun 07 07:40:20 PM PDT 24
Peak memory 196432 kb
Host smart-64b126bc-b594-4f54-aa24-cc81ec1d2529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870537409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3870537409
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3595985922
Short name T576
Test name
Test status
Simulation time 129021392 ps
CPU time 1.21 seconds
Started Jun 07 07:40:17 PM PDT 24
Finished Jun 07 07:40:19 PM PDT 24
Peak memory 196284 kb
Host smart-b0e3d60d-5241-460f-a98f-5abead0b40bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595985922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3595985922
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.66051392
Short name T229
Test name
Test status
Simulation time 123748198 ps
CPU time 2.6 seconds
Started Jun 07 07:40:18 PM PDT 24
Finished Jun 07 07:40:22 PM PDT 24
Peak memory 196404 kb
Host smart-3f38fba9-a1a6-4fc8-b485-4d67263c1876
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66051392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.gpio_intr_with_filter_rand_intr_event.66051392
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4279450234
Short name T656
Test name
Test status
Simulation time 81752100 ps
CPU time 2.35 seconds
Started Jun 07 07:40:12 PM PDT 24
Finished Jun 07 07:40:18 PM PDT 24
Peak memory 197304 kb
Host smart-4a895568-794f-4d4d-bce1-ee2aeee472f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279450234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4279450234
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2528452100
Short name T417
Test name
Test status
Simulation time 53572710 ps
CPU time 0.69 seconds
Started Jun 07 07:40:08 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 195100 kb
Host smart-7ee85e69-78d8-4fc0-b5eb-496f380160f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528452100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2528452100
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.878307847
Short name T495
Test name
Test status
Simulation time 109425619 ps
CPU time 0.94 seconds
Started Jun 07 07:40:07 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 196068 kb
Host smart-3bab3efd-e067-4e22-9935-8472270e0df2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878307847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.878307847
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.902262200
Short name T254
Test name
Test status
Simulation time 322054043 ps
CPU time 4 seconds
Started Jun 07 07:40:11 PM PDT 24
Finished Jun 07 07:40:18 PM PDT 24
Peak memory 197980 kb
Host smart-e8501925-c45e-442e-9922-7cd9f5f5978d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902262200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.902262200
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1770536577
Short name T664
Test name
Test status
Simulation time 78429527 ps
CPU time 1.36 seconds
Started Jun 07 07:40:05 PM PDT 24
Finished Jun 07 07:40:11 PM PDT 24
Peak memory 196624 kb
Host smart-aad4a5ea-0fa9-4724-80f0-1d0c3c65869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770536577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1770536577
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3356699418
Short name T572
Test name
Test status
Simulation time 48623866 ps
CPU time 1.22 seconds
Started Jun 07 07:40:07 PM PDT 24
Finished Jun 07 07:40:12 PM PDT 24
Peak memory 195932 kb
Host smart-25af3c50-3c07-4742-ab6a-133320c6e67e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356699418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3356699418
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1146201386
Short name T517
Test name
Test status
Simulation time 3698057317 ps
CPU time 74.34 seconds
Started Jun 07 07:40:14 PM PDT 24
Finished Jun 07 07:41:31 PM PDT 24
Peak memory 198236 kb
Host smart-77ef1592-b4b3-45cc-9c23-982629947f79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146201386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1146201386
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.865555843
Short name T57
Test name
Test status
Simulation time 31734433 ps
CPU time 0.56 seconds
Started Jun 07 07:40:24 PM PDT 24
Finished Jun 07 07:40:26 PM PDT 24
Peak memory 193920 kb
Host smart-872b6efb-1b85-4d42-91ae-b110385fe3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865555843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.865555843
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4259109296
Short name T536
Test name
Test status
Simulation time 42456351 ps
CPU time 0.94 seconds
Started Jun 07 07:40:18 PM PDT 24
Finished Jun 07 07:40:21 PM PDT 24
Peak memory 195784 kb
Host smart-83586329-7ab8-4b67-af5b-2f765e753723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259109296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4259109296
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3871213828
Short name T489
Test name
Test status
Simulation time 2869234450 ps
CPU time 19.94 seconds
Started Jun 07 07:40:21 PM PDT 24
Finished Jun 07 07:40:43 PM PDT 24
Peak memory 197052 kb
Host smart-5212312b-3a17-4ad2-b086-fc587939cd85
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871213828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3871213828
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.687405941
Short name T634
Test name
Test status
Simulation time 98820113 ps
CPU time 0.88 seconds
Started Jun 07 07:40:21 PM PDT 24
Finished Jun 07 07:40:24 PM PDT 24
Peak memory 196936 kb
Host smart-8017ca47-a885-4f5d-9f9b-9b5f0fecfa51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687405941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.687405941
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2474747128
Short name T356
Test name
Test status
Simulation time 98203345 ps
CPU time 1.33 seconds
Started Jun 07 07:40:22 PM PDT 24
Finished Jun 07 07:40:25 PM PDT 24
Peak memory 197012 kb
Host smart-c2bb772e-9d45-4723-a064-86e20071d6dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474747128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2474747128
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3864053062
Short name T706
Test name
Test status
Simulation time 121238387 ps
CPU time 2.61 seconds
Started Jun 07 07:40:19 PM PDT 24
Finished Jun 07 07:40:23 PM PDT 24
Peak memory 198168 kb
Host smart-ac475f90-17a7-4d87-a66e-6be89c21b82d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864053062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3864053062
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3199266958
Short name T668
Test name
Test status
Simulation time 118211794 ps
CPU time 3.29 seconds
Started Jun 07 07:40:21 PM PDT 24
Finished Jun 07 07:40:26 PM PDT 24
Peak memory 197128 kb
Host smart-0148f61c-66d5-4f72-8280-983cfa4b7183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199266958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3199266958
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.461991948
Short name T700
Test name
Test status
Simulation time 183660942 ps
CPU time 0.82 seconds
Started Jun 07 07:40:12 PM PDT 24
Finished Jun 07 07:40:16 PM PDT 24
Peak memory 196352 kb
Host smart-9b13bf74-3aa4-4b1d-825a-d4764e250a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461991948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.461991948
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3606759492
Short name T373
Test name
Test status
Simulation time 50109822 ps
CPU time 1.09 seconds
Started Jun 07 07:40:20 PM PDT 24
Finished Jun 07 07:40:23 PM PDT 24
Peak memory 196184 kb
Host smart-703a099b-e723-4857-8fba-115709da7848
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606759492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3606759492
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1267828824
Short name T544
Test name
Test status
Simulation time 1765995882 ps
CPU time 5.05 seconds
Started Jun 07 07:40:24 PM PDT 24
Finished Jun 07 07:40:30 PM PDT 24
Peak memory 198016 kb
Host smart-c6bbc45f-e747-4153-affb-d394630a2240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267828824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1267828824
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.454431494
Short name T18
Test name
Test status
Simulation time 77888215 ps
CPU time 1.23 seconds
Started Jun 07 07:40:11 PM PDT 24
Finished Jun 07 07:40:15 PM PDT 24
Peak memory 195580 kb
Host smart-98fbd2ea-a2d1-47ba-ae87-729293a6a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454431494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.454431494
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.491239979
Short name T153
Test name
Test status
Simulation time 22473129 ps
CPU time 0.87 seconds
Started Jun 07 07:40:13 PM PDT 24
Finished Jun 07 07:40:17 PM PDT 24
Peak memory 195420 kb
Host smart-ed0d1d0a-9853-4c85-a720-77a01adb28d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491239979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.491239979
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4114530201
Short name T287
Test name
Test status
Simulation time 23726789599 ps
CPU time 95.34 seconds
Started Jun 07 07:40:22 PM PDT 24
Finished Jun 07 07:41:59 PM PDT 24
Peak memory 198252 kb
Host smart-eccf5d30-57dc-4fe1-91fd-b3b78a6fae6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114530201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4114530201
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1123787417
Short name T255
Test name
Test status
Simulation time 12424892 ps
CPU time 0.64 seconds
Started Jun 07 07:40:32 PM PDT 24
Finished Jun 07 07:40:34 PM PDT 24
Peak memory 194668 kb
Host smart-b519315b-f67f-429f-ad53-ded18e0679b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123787417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1123787417
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3341429173
Short name T314
Test name
Test status
Simulation time 38876736 ps
CPU time 0.79 seconds
Started Jun 07 07:40:18 PM PDT 24
Finished Jun 07 07:40:20 PM PDT 24
Peak memory 195264 kb
Host smart-4ae4b6e2-aea0-4109-9fa7-c0e54332695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341429173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3341429173
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2551442916
Short name T332
Test name
Test status
Simulation time 1160147401 ps
CPU time 15.05 seconds
Started Jun 07 07:40:21 PM PDT 24
Finished Jun 07 07:40:37 PM PDT 24
Peak memory 196900 kb
Host smart-dc76624b-9a50-4294-8694-ec2ea0f46705
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551442916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2551442916
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3656312445
Short name T506
Test name
Test status
Simulation time 85683855 ps
CPU time 1.07 seconds
Started Jun 07 07:40:35 PM PDT 24
Finished Jun 07 07:40:37 PM PDT 24
Peak memory 196676 kb
Host smart-067e5b51-f880-4fd6-a759-993597748112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656312445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3656312445
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2543732478
Short name T702
Test name
Test status
Simulation time 179017097 ps
CPU time 1.41 seconds
Started Jun 07 07:40:23 PM PDT 24
Finished Jun 07 07:40:26 PM PDT 24
Peak memory 196568 kb
Host smart-f392b204-5039-4fcb-a254-67fd753ca3b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543732478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2543732478
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3518660068
Short name T322
Test name
Test status
Simulation time 84842151 ps
CPU time 3.51 seconds
Started Jun 07 07:40:19 PM PDT 24
Finished Jun 07 07:40:25 PM PDT 24
Peak memory 198140 kb
Host smart-9cc992a6-90a9-4090-a6f8-4d86c560b581
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518660068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3518660068
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3457407452
Short name T223
Test name
Test status
Simulation time 794142769 ps
CPU time 1.96 seconds
Started Jun 07 07:40:19 PM PDT 24
Finished Jun 07 07:40:23 PM PDT 24
Peak memory 196208 kb
Host smart-f05d55d6-4db1-4aa7-9ef5-245e507ee220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457407452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3457407452
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2421639074
Short name T374
Test name
Test status
Simulation time 270982166 ps
CPU time 1.33 seconds
Started Jun 07 07:40:19 PM PDT 24
Finished Jun 07 07:40:22 PM PDT 24
Peak memory 197040 kb
Host smart-be6bdf99-bc12-4523-9348-8126383aca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421639074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2421639074
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2270195823
Short name T291
Test name
Test status
Simulation time 513720398 ps
CPU time 1.24 seconds
Started Jun 07 07:40:25 PM PDT 24
Finished Jun 07 07:40:27 PM PDT 24
Peak memory 198132 kb
Host smart-15311070-1468-4621-bd9b-d47548582fbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270195823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2270195823
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1530648402
Short name T6
Test name
Test status
Simulation time 865260659 ps
CPU time 3.77 seconds
Started Jun 07 07:40:32 PM PDT 24
Finished Jun 07 07:40:36 PM PDT 24
Peak memory 197976 kb
Host smart-b2f00438-16cc-4a60-8c77-56df0f000e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530648402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1530648402
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1862740711
Short name T207
Test name
Test status
Simulation time 41420835 ps
CPU time 1.31 seconds
Started Jun 07 07:40:19 PM PDT 24
Finished Jun 07 07:40:22 PM PDT 24
Peak memory 195840 kb
Host smart-60e8775a-a824-4b8c-8ef4-edb319f8c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862740711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1862740711
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3536928397
Short name T133
Test name
Test status
Simulation time 62804939 ps
CPU time 1.21 seconds
Started Jun 07 07:40:22 PM PDT 24
Finished Jun 07 07:40:25 PM PDT 24
Peak memory 196604 kb
Host smart-b595fd4d-1084-4acb-9ca9-e8512044471b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536928397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3536928397
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2361684203
Short name T616
Test name
Test status
Simulation time 1303205931 ps
CPU time 36.3 seconds
Started Jun 07 07:40:36 PM PDT 24
Finished Jun 07 07:41:13 PM PDT 24
Peak memory 197764 kb
Host smart-bdbf0577-a8a4-4b1d-9280-03707d620895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361684203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2361684203
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1151466607
Short name T466
Test name
Test status
Simulation time 30220817 ps
CPU time 0.59 seconds
Started Jun 07 07:40:40 PM PDT 24
Finished Jun 07 07:40:42 PM PDT 24
Peak memory 194688 kb
Host smart-d9cde3a6-5511-4234-b9a1-63a3a80bc287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151466607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1151466607
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2683110672
Short name T294
Test name
Test status
Simulation time 19721285 ps
CPU time 0.64 seconds
Started Jun 07 07:40:31 PM PDT 24
Finished Jun 07 07:40:33 PM PDT 24
Peak memory 193924 kb
Host smart-42c6d152-8ed8-4c38-812c-1836b183aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683110672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2683110672
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1123807500
Short name T24
Test name
Test status
Simulation time 1820761243 ps
CPU time 16.39 seconds
Started Jun 07 07:40:32 PM PDT 24
Finished Jun 07 07:40:50 PM PDT 24
Peak memory 197980 kb
Host smart-1236702c-a164-4c68-96c0-9a4669e25d97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123807500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1123807500
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2568989385
Short name T462
Test name
Test status
Simulation time 205866976 ps
CPU time 0.76 seconds
Started Jun 07 07:40:38 PM PDT 24
Finished Jun 07 07:40:40 PM PDT 24
Peak memory 196580 kb
Host smart-cb5b6510-d7c0-43ee-bfae-b85bc74a323c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568989385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2568989385
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2745074173
Short name T388
Test name
Test status
Simulation time 77460471 ps
CPU time 1.26 seconds
Started Jun 07 07:40:33 PM PDT 24
Finished Jun 07 07:40:36 PM PDT 24
Peak memory 197308 kb
Host smart-800c00a4-801e-4eef-a6c5-f301686390e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745074173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2745074173
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3866436374
Short name T237
Test name
Test status
Simulation time 83030545 ps
CPU time 3.27 seconds
Started Jun 07 07:40:32 PM PDT 24
Finished Jun 07 07:40:36 PM PDT 24
Peak memory 198124 kb
Host smart-f8af03b2-e305-4089-9241-86829a57db15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866436374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3866436374
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1797151659
Short name T493
Test name
Test status
Simulation time 147619432 ps
CPU time 3.41 seconds
Started Jun 07 07:40:31 PM PDT 24
Finished Jun 07 07:40:35 PM PDT 24
Peak memory 196988 kb
Host smart-effc312f-5bf3-414f-92e6-c803cd873132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797151659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1797151659
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3921017977
Short name T471
Test name
Test status
Simulation time 199759204 ps
CPU time 0.84 seconds
Started Jun 07 07:40:31 PM PDT 24
Finished Jun 07 07:40:33 PM PDT 24
Peak memory 195668 kb
Host smart-a5caa9f3-af8e-46ba-8866-52cfa54a94e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921017977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3921017977
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2989928841
Short name T263
Test name
Test status
Simulation time 15384270 ps
CPU time 0.66 seconds
Started Jun 07 07:40:33 PM PDT 24
Finished Jun 07 07:40:36 PM PDT 24
Peak memory 195096 kb
Host smart-3415044c-2cab-4e31-a878-106742ad2925
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989928841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2989928841
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3580430221
Short name T367
Test name
Test status
Simulation time 2859503942 ps
CPU time 5 seconds
Started Jun 07 07:40:39 PM PDT 24
Finished Jun 07 07:40:46 PM PDT 24
Peak memory 198148 kb
Host smart-72645d05-e00e-4833-ba1b-ffe41e0235ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580430221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3580430221
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.879447460
Short name T302
Test name
Test status
Simulation time 104603316 ps
CPU time 1.04 seconds
Started Jun 07 07:40:31 PM PDT 24
Finished Jun 07 07:40:33 PM PDT 24
Peak memory 196464 kb
Host smart-e96e65e0-d1ca-41c0-94d6-74a7118df747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879447460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.879447460
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1780226825
Short name T600
Test name
Test status
Simulation time 203918504 ps
CPU time 1.08 seconds
Started Jun 07 07:40:32 PM PDT 24
Finished Jun 07 07:40:34 PM PDT 24
Peak memory 195856 kb
Host smart-e128ebd9-23c0-496b-a03f-83def32418ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780226825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1780226825
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.48984094
Short name T705
Test name
Test status
Simulation time 14589452929 ps
CPU time 90.66 seconds
Started Jun 07 07:40:39 PM PDT 24
Finished Jun 07 07:42:11 PM PDT 24
Peak memory 198116 kb
Host smart-91031b63-f86b-416a-9b9b-d8184f78b92d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48984094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gp
io_stress_all.48984094
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3780902449
Short name T649
Test name
Test status
Simulation time 145368626006 ps
CPU time 979.71 seconds
Started Jun 07 07:40:39 PM PDT 24
Finished Jun 07 07:57:00 PM PDT 24
Peak memory 198256 kb
Host smart-b3cfbd58-576d-468d-94fe-e75a3f2d3471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3780902449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3780902449
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.220534271
Short name T37
Test name
Test status
Simulation time 39640836 ps
CPU time 0.58 seconds
Started Jun 07 07:40:41 PM PDT 24
Finished Jun 07 07:40:44 PM PDT 24
Peak memory 193948 kb
Host smart-4188eae5-b062-4436-979e-2d9d0e9ab19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220534271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.220534271
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1261922763
Short name T520
Test name
Test status
Simulation time 45413439 ps
CPU time 0.88 seconds
Started Jun 07 07:40:43 PM PDT 24
Finished Jun 07 07:40:46 PM PDT 24
Peak memory 197156 kb
Host smart-7131465d-e093-478c-ad94-4a25d17571df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261922763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1261922763
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3135995451
Short name T458
Test name
Test status
Simulation time 527405325 ps
CPU time 15.57 seconds
Started Jun 07 07:40:37 PM PDT 24
Finished Jun 07 07:40:54 PM PDT 24
Peak memory 196300 kb
Host smart-721a6864-0093-4ff9-bbd2-4afec1ccca00
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135995451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3135995451
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1898942459
Short name T120
Test name
Test status
Simulation time 83604020 ps
CPU time 0.83 seconds
Started Jun 07 07:40:40 PM PDT 24
Finished Jun 07 07:40:42 PM PDT 24
Peak memory 196084 kb
Host smart-ae762ed6-6352-4710-8202-953482c239ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898942459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1898942459
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2500170515
Short name T189
Test name
Test status
Simulation time 41316907 ps
CPU time 1.05 seconds
Started Jun 07 07:40:42 PM PDT 24
Finished Jun 07 07:40:45 PM PDT 24
Peak memory 196192 kb
Host smart-efcff169-833d-4c0e-8033-0a2fea709b24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500170515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2500170515
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.732662817
Short name T639
Test name
Test status
Simulation time 236256903 ps
CPU time 2.54 seconds
Started Jun 07 07:40:37 PM PDT 24
Finished Jun 07 07:40:41 PM PDT 24
Peak memory 198080 kb
Host smart-9a4ec633-3884-4cbf-a036-eb12e598b93b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732662817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.732662817
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3104886408
Short name T628
Test name
Test status
Simulation time 157647547 ps
CPU time 2.69 seconds
Started Jun 07 07:40:40 PM PDT 24
Finished Jun 07 07:40:44 PM PDT 24
Peak memory 195868 kb
Host smart-8c822128-d3f2-4f8f-baeb-d2f448cea3cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104886408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3104886408
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1898339682
Short name T431
Test name
Test status
Simulation time 84158310 ps
CPU time 0.92 seconds
Started Jun 07 07:40:39 PM PDT 24
Finished Jun 07 07:40:41 PM PDT 24
Peak memory 195888 kb
Host smart-ffc888c7-3677-410d-a464-876c780890b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898339682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1898339682
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1690306456
Short name T653
Test name
Test status
Simulation time 205996000 ps
CPU time 1.19 seconds
Started Jun 07 07:40:37 PM PDT 24
Finished Jun 07 07:40:38 PM PDT 24
Peak memory 197216 kb
Host smart-ad682c87-8b8d-4e74-b2c1-2511f5fadaff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690306456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1690306456
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4278733252
Short name T470
Test name
Test status
Simulation time 247796155 ps
CPU time 2.52 seconds
Started Jun 07 07:40:42 PM PDT 24
Finished Jun 07 07:40:46 PM PDT 24
Peak memory 198028 kb
Host smart-d17c4139-9a3d-4e59-9895-e848ed155911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278733252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4278733252
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3120465830
Short name T194
Test name
Test status
Simulation time 161520595 ps
CPU time 0.89 seconds
Started Jun 07 07:40:39 PM PDT 24
Finished Jun 07 07:40:41 PM PDT 24
Peak memory 195404 kb
Host smart-7a13c95e-5746-4770-8544-9c04bc8b9245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120465830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3120465830
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3177119107
Short name T662
Test name
Test status
Simulation time 113515536 ps
CPU time 0.88 seconds
Started Jun 07 07:40:41 PM PDT 24
Finished Jun 07 07:40:44 PM PDT 24
Peak memory 196232 kb
Host smart-cd5f2a77-83d2-4d67-8b99-b8bb49f1e588
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177119107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3177119107
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1331996181
Short name T660
Test name
Test status
Simulation time 64764541684 ps
CPU time 193.45 seconds
Started Jun 07 07:40:40 PM PDT 24
Finished Jun 07 07:43:55 PM PDT 24
Peak memory 198256 kb
Host smart-ed538e90-401b-4271-b17d-3a9cd8584e23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331996181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1331996181
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2359759032
Short name T109
Test name
Test status
Simulation time 81533136337 ps
CPU time 331.86 seconds
Started Jun 07 07:40:40 PM PDT 24
Finished Jun 07 07:46:13 PM PDT 24
Peak memory 198324 kb
Host smart-699cdfee-c35e-4439-8cb5-889ff0e834c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2359759032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2359759032
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3763088035
Short name T393
Test name
Test status
Simulation time 12180228 ps
CPU time 0.58 seconds
Started Jun 07 07:36:02 PM PDT 24
Finished Jun 07 07:36:04 PM PDT 24
Peak memory 193712 kb
Host smart-25b35228-5680-4b58-9ad9-37dcf6175705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763088035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3763088035
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2326700571
Short name T281
Test name
Test status
Simulation time 24757361 ps
CPU time 0.71 seconds
Started Jun 07 07:35:55 PM PDT 24
Finished Jun 07 07:35:58 PM PDT 24
Peak memory 195376 kb
Host smart-e25b3eb3-ffed-468e-8b76-9b7dd0eb15d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326700571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2326700571
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3818836093
Short name T699
Test name
Test status
Simulation time 2617517981 ps
CPU time 22.24 seconds
Started Jun 07 07:35:57 PM PDT 24
Finished Jun 07 07:36:21 PM PDT 24
Peak memory 198240 kb
Host smart-f7048e38-e19d-4097-ada7-34abd38e4104
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818836093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3818836093
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2939947691
Short name T720
Test name
Test status
Simulation time 428415716 ps
CPU time 0.66 seconds
Started Jun 07 07:35:56 PM PDT 24
Finished Jun 07 07:35:59 PM PDT 24
Peak memory 194892 kb
Host smart-6d631ba0-7494-46f1-ae8e-025555203b2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939947691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2939947691
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.31030694
Short name T296
Test name
Test status
Simulation time 65627679 ps
CPU time 0.86 seconds
Started Jun 07 07:35:57 PM PDT 24
Finished Jun 07 07:36:00 PM PDT 24
Peak memory 196576 kb
Host smart-ea5b011f-aafe-4b45-937a-01107a8402a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.31030694
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2663921966
Short name T136
Test name
Test status
Simulation time 71007926 ps
CPU time 2.81 seconds
Started Jun 07 07:35:57 PM PDT 24
Finished Jun 07 07:36:02 PM PDT 24
Peak memory 198140 kb
Host smart-d96515cb-fe41-4ffe-8804-3edf11119320
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663921966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2663921966
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1655178540
Short name T657
Test name
Test status
Simulation time 191011391 ps
CPU time 2.83 seconds
Started Jun 07 07:35:57 PM PDT 24
Finished Jun 07 07:36:02 PM PDT 24
Peak memory 198164 kb
Host smart-2a4ef1cf-1973-4115-b059-b7399e1df51f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655178540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1655178540
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2383845876
Short name T456
Test name
Test status
Simulation time 55492350 ps
CPU time 0.84 seconds
Started Jun 07 07:35:56 PM PDT 24
Finished Jun 07 07:35:58 PM PDT 24
Peak memory 196696 kb
Host smart-f89a9ccf-a9bd-47d8-abb8-54f370ff24dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383845876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2383845876
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.119057443
Short name T249
Test name
Test status
Simulation time 554173248 ps
CPU time 1.05 seconds
Started Jun 07 07:35:57 PM PDT 24
Finished Jun 07 07:36:00 PM PDT 24
Peak memory 196084 kb
Host smart-806103ee-12af-4417-8c0a-be4442a89d38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119057443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.119057443
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1305924302
Short name T442
Test name
Test status
Simulation time 383674976 ps
CPU time 6.33 seconds
Started Jun 07 07:36:02 PM PDT 24
Finished Jun 07 07:36:10 PM PDT 24
Peak memory 197760 kb
Host smart-66e7cc1e-5070-4a45-87e5-2225889e7610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305924302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1305924302
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.406057340
Short name T299
Test name
Test status
Simulation time 22450611 ps
CPU time 0.8 seconds
Started Jun 07 07:35:50 PM PDT 24
Finished Jun 07 07:35:53 PM PDT 24
Peak memory 195308 kb
Host smart-26b6d02f-919a-4fa9-8b95-13fbfb2b409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406057340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.406057340
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2570005503
Short name T226
Test name
Test status
Simulation time 121640809 ps
CPU time 1.11 seconds
Started Jun 07 07:35:47 PM PDT 24
Finished Jun 07 07:35:51 PM PDT 24
Peak memory 195444 kb
Host smart-437713cd-f396-4311-a59d-dfcdd9226c6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570005503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2570005503
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1295235709
Short name T225
Test name
Test status
Simulation time 53735527219 ps
CPU time 198.08 seconds
Started Jun 07 07:35:58 PM PDT 24
Finished Jun 07 07:39:18 PM PDT 24
Peak memory 198216 kb
Host smart-1ddd2fe2-0b32-40cc-a20e-ef388128f38f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295235709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1295235709
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1727365786
Short name T283
Test name
Test status
Simulation time 30035122 ps
CPU time 0.57 seconds
Started Jun 07 07:36:03 PM PDT 24
Finished Jun 07 07:36:06 PM PDT 24
Peak memory 194144 kb
Host smart-200fc8e3-01be-4c0a-a5ad-3c21d9e0e25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727365786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1727365786
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3295230498
Short name T486
Test name
Test status
Simulation time 50730777 ps
CPU time 0.88 seconds
Started Jun 07 07:36:08 PM PDT 24
Finished Jun 07 07:36:10 PM PDT 24
Peak memory 196740 kb
Host smart-2ea7351e-415c-4a61-ba43-569366c685eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295230498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3295230498
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1051948952
Short name T620
Test name
Test status
Simulation time 1547143256 ps
CPU time 27.47 seconds
Started Jun 07 07:36:04 PM PDT 24
Finished Jun 07 07:36:33 PM PDT 24
Peak memory 195552 kb
Host smart-7a0735fb-10c2-468c-adaf-28a3aacbe07a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051948952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1051948952
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3345553795
Short name T680
Test name
Test status
Simulation time 365778051 ps
CPU time 1.08 seconds
Started Jun 07 07:36:04 PM PDT 24
Finished Jun 07 07:36:07 PM PDT 24
Peak memory 196700 kb
Host smart-460c8365-9fd1-4f6a-88fb-7707dcb0db47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345553795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3345553795
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3205891602
Short name T565
Test name
Test status
Simulation time 146713784 ps
CPU time 1.18 seconds
Started Jun 07 07:36:02 PM PDT 24
Finished Jun 07 07:36:04 PM PDT 24
Peak memory 197192 kb
Host smart-2282310f-1ad6-4649-b7df-4899449f6c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205891602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3205891602
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2119340224
Short name T168
Test name
Test status
Simulation time 171089991 ps
CPU time 3.63 seconds
Started Jun 07 07:36:03 PM PDT 24
Finished Jun 07 07:36:09 PM PDT 24
Peak memory 198176 kb
Host smart-64ba5d77-20dc-4054-9aeb-b91f85d1d452
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119340224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2119340224
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.275835607
Short name T180
Test name
Test status
Simulation time 252396830 ps
CPU time 2.46 seconds
Started Jun 07 07:36:04 PM PDT 24
Finished Jun 07 07:36:08 PM PDT 24
Peak memory 198096 kb
Host smart-2159dbb4-8097-4ece-8bd6-f0644fac3c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275835607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.275835607
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.461405916
Short name T473
Test name
Test status
Simulation time 50342259 ps
CPU time 0.67 seconds
Started Jun 07 07:35:58 PM PDT 24
Finished Jun 07 07:36:01 PM PDT 24
Peak memory 195032 kb
Host smart-94d27a0a-edd6-49e6-a67e-8fe3ebdd2a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461405916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.461405916
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4285054192
Short name T251
Test name
Test status
Simulation time 51359242 ps
CPU time 1.06 seconds
Started Jun 07 07:36:03 PM PDT 24
Finished Jun 07 07:36:05 PM PDT 24
Peak memory 196116 kb
Host smart-7d7901e7-15d9-4015-bbd1-bec46cb57f42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285054192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4285054192
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1137871660
Short name T703
Test name
Test status
Simulation time 341642159 ps
CPU time 3.78 seconds
Started Jun 07 07:36:04 PM PDT 24
Finished Jun 07 07:36:10 PM PDT 24
Peak memory 197996 kb
Host smart-ea153e48-0889-4db4-9aa5-b98925599fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137871660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1137871660
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.658612593
Short name T284
Test name
Test status
Simulation time 38563327 ps
CPU time 1.09 seconds
Started Jun 07 07:35:57 PM PDT 24
Finished Jun 07 07:36:01 PM PDT 24
Peak memory 195768 kb
Host smart-5cc6fbea-0d9b-4bac-a78f-2de5d8c4ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658612593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.658612593
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3392213529
Short name T275
Test name
Test status
Simulation time 166099619 ps
CPU time 1.19 seconds
Started Jun 07 07:35:55 PM PDT 24
Finished Jun 07 07:35:57 PM PDT 24
Peak memory 196564 kb
Host smart-09d0850c-0ae2-4755-bb6a-5913ad664a08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392213529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3392213529
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2856055112
Short name T72
Test name
Test status
Simulation time 13899227875 ps
CPU time 59.9 seconds
Started Jun 07 07:36:06 PM PDT 24
Finished Jun 07 07:37:08 PM PDT 24
Peak memory 198180 kb
Host smart-8efb5d1f-e863-4f59-81ac-a8e645c5973c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856055112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2856055112
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1804559163
Short name T62
Test name
Test status
Simulation time 236218154592 ps
CPU time 1184.59 seconds
Started Jun 07 07:36:06 PM PDT 24
Finished Jun 07 07:55:53 PM PDT 24
Peak memory 198316 kb
Host smart-4aef3bef-b16e-48ef-8750-f78f47311924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1804559163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1804559163
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1320810317
Short name T379
Test name
Test status
Simulation time 47371370 ps
CPU time 0.59 seconds
Started Jun 07 07:36:10 PM PDT 24
Finished Jun 07 07:36:13 PM PDT 24
Peak memory 194132 kb
Host smart-5c4704ea-ef8b-4b87-8b05-351826aa4194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320810317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1320810317
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1518942283
Short name T268
Test name
Test status
Simulation time 34085146 ps
CPU time 0.64 seconds
Started Jun 07 07:36:13 PM PDT 24
Finished Jun 07 07:36:16 PM PDT 24
Peak memory 193972 kb
Host smart-9b6e45ae-3575-406c-add0-11d0d5acf008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518942283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1518942283
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1817949138
Short name T159
Test name
Test status
Simulation time 10274466066 ps
CPU time 26.82 seconds
Started Jun 07 07:36:11 PM PDT 24
Finished Jun 07 07:36:40 PM PDT 24
Peak memory 198192 kb
Host smart-f42e4dd0-180d-47e9-bcb4-78cfddc79726
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817949138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1817949138
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2917366943
Short name T659
Test name
Test status
Simulation time 81109003 ps
CPU time 0.98 seconds
Started Jun 07 07:36:12 PM PDT 24
Finished Jun 07 07:36:15 PM PDT 24
Peak memory 198080 kb
Host smart-4a552885-e46c-420f-b3fb-3ee862ed6aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917366943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2917366943
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4133467715
Short name T12
Test name
Test status
Simulation time 93620590 ps
CPU time 0.97 seconds
Started Jun 07 07:36:12 PM PDT 24
Finished Jun 07 07:36:15 PM PDT 24
Peak memory 195808 kb
Host smart-1a733edb-ba86-44ad-bf58-0f7d51fbfd98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133467715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4133467715
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3488875300
Short name T575
Test name
Test status
Simulation time 23388560 ps
CPU time 1 seconds
Started Jun 07 07:36:13 PM PDT 24
Finished Jun 07 07:36:16 PM PDT 24
Peak memory 196336 kb
Host smart-e268afd9-7b6f-4d60-9cb9-a8315df76575
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488875300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3488875300
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4008644150
Short name T366
Test name
Test status
Simulation time 116570145 ps
CPU time 2.69 seconds
Started Jun 07 07:36:13 PM PDT 24
Finished Jun 07 07:36:17 PM PDT 24
Peak memory 195840 kb
Host smart-47cde2a5-cfb2-481f-bb89-27b28863d079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008644150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4008644150
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3749685799
Short name T549
Test name
Test status
Simulation time 83024008 ps
CPU time 1.05 seconds
Started Jun 07 07:36:03 PM PDT 24
Finished Jun 07 07:36:06 PM PDT 24
Peak memory 196016 kb
Host smart-f1d2fad0-9d88-4713-a9d7-a308d9fb2da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749685799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3749685799
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1092089650
Short name T410
Test name
Test status
Simulation time 151448199 ps
CPU time 0.94 seconds
Started Jun 07 07:36:03 PM PDT 24
Finished Jun 07 07:36:06 PM PDT 24
Peak memory 196732 kb
Host smart-d497db47-b06b-40df-9bec-dc2ae802b075
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092089650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1092089650
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4210469138
Short name T241
Test name
Test status
Simulation time 164518203 ps
CPU time 2.81 seconds
Started Jun 07 07:36:13 PM PDT 24
Finished Jun 07 07:36:18 PM PDT 24
Peak memory 198104 kb
Host smart-f26c4ae3-3e0a-4610-9846-a0df20fe11ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210469138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4210469138
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.892998301
Short name T512
Test name
Test status
Simulation time 62418781 ps
CPU time 1.33 seconds
Started Jun 07 07:36:03 PM PDT 24
Finished Jun 07 07:36:06 PM PDT 24
Peak memory 195876 kb
Host smart-a660af4a-ce5c-4f5c-92cd-25ee9c89a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892998301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.892998301
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.305002426
Short name T231
Test name
Test status
Simulation time 69640922 ps
CPU time 0.85 seconds
Started Jun 07 07:36:08 PM PDT 24
Finished Jun 07 07:36:10 PM PDT 24
Peak memory 195432 kb
Host smart-5f75d3fa-277c-4928-b1f2-6768cee7e368
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305002426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.305002426
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3053554775
Short name T257
Test name
Test status
Simulation time 1860486163 ps
CPU time 26.11 seconds
Started Jun 07 07:36:12 PM PDT 24
Finished Jun 07 07:36:40 PM PDT 24
Peak memory 198084 kb
Host smart-cd903f71-f504-4089-af1b-e0e63f4ae8a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053554775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3053554775
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2900768197
Short name T521
Test name
Test status
Simulation time 37135954 ps
CPU time 0.59 seconds
Started Jun 07 07:36:23 PM PDT 24
Finished Jun 07 07:36:25 PM PDT 24
Peak memory 194116 kb
Host smart-f36c00bb-0da3-4767-ac90-341eff916216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900768197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2900768197
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2940762811
Short name T540
Test name
Test status
Simulation time 38909170 ps
CPU time 0.84 seconds
Started Jun 07 07:36:18 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 195344 kb
Host smart-469fda04-4a20-4206-9e6f-61ae2774c483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940762811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2940762811
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1020582770
Short name T169
Test name
Test status
Simulation time 212105034 ps
CPU time 7.06 seconds
Started Jun 07 07:36:19 PM PDT 24
Finished Jun 07 07:36:28 PM PDT 24
Peak memory 196896 kb
Host smart-cc620bf6-f53c-4445-80f5-b78037c7a62a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020582770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1020582770
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3590051819
Short name T665
Test name
Test status
Simulation time 356398837 ps
CPU time 1.03 seconds
Started Jun 07 07:36:18 PM PDT 24
Finished Jun 07 07:36:22 PM PDT 24
Peak memory 196688 kb
Host smart-5e4735b6-f9ea-4206-a346-d2f5db2e5849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590051819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3590051819
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1898444798
Short name T522
Test name
Test status
Simulation time 168116418 ps
CPU time 1.01 seconds
Started Jun 07 07:36:17 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 195980 kb
Host smart-4f409d8e-095d-4352-923a-633c5ae26585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898444798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1898444798
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.457327994
Short name T581
Test name
Test status
Simulation time 294929868 ps
CPU time 3.44 seconds
Started Jun 07 07:36:24 PM PDT 24
Finished Jun 07 07:36:29 PM PDT 24
Peak memory 198156 kb
Host smart-e9efe1d3-620b-4406-bfc2-2b38d2f4c02e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457327994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.457327994
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2733183969
Short name T117
Test name
Test status
Simulation time 74040245 ps
CPU time 1.78 seconds
Started Jun 07 07:36:17 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 196896 kb
Host smart-f70648c3-8ade-451a-b5da-21e84ce79adf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733183969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2733183969
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2069650977
Short name T256
Test name
Test status
Simulation time 36068787 ps
CPU time 0.98 seconds
Started Jun 07 07:36:14 PM PDT 24
Finished Jun 07 07:36:16 PM PDT 24
Peak memory 196668 kb
Host smart-bf9e165f-b145-453f-8236-05ff0282c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069650977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2069650977
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1398676521
Short name T400
Test name
Test status
Simulation time 24935100 ps
CPU time 0.97 seconds
Started Jun 07 07:36:12 PM PDT 24
Finished Jun 07 07:36:15 PM PDT 24
Peak memory 195976 kb
Host smart-7335caa2-0fb4-488c-84dc-10de46e976e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398676521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1398676521
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2175149658
Short name T499
Test name
Test status
Simulation time 59852311 ps
CPU time 1.18 seconds
Started Jun 07 07:36:17 PM PDT 24
Finished Jun 07 07:36:19 PM PDT 24
Peak memory 196552 kb
Host smart-751de5c4-8018-44d4-96c3-823bad32240e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175149658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2175149658
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.830601037
Short name T312
Test name
Test status
Simulation time 166927940 ps
CPU time 1.37 seconds
Started Jun 07 07:36:13 PM PDT 24
Finished Jun 07 07:36:16 PM PDT 24
Peak memory 196908 kb
Host smart-d57db8c7-c56a-478e-a56c-56920ae7faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830601037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.830601037
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1060676633
Short name T327
Test name
Test status
Simulation time 152088478 ps
CPU time 1.38 seconds
Started Jun 07 07:36:12 PM PDT 24
Finished Jun 07 07:36:16 PM PDT 24
Peak memory 197160 kb
Host smart-e2d4441e-4f5d-4bcd-b05a-06f013616842
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060676633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1060676633
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2731558400
Short name T309
Test name
Test status
Simulation time 12883492287 ps
CPU time 151.86 seconds
Started Jun 07 07:36:20 PM PDT 24
Finished Jun 07 07:38:55 PM PDT 24
Peak memory 198224 kb
Host smart-3666df4a-940b-4aad-8a8a-22664393ee5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731558400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2731558400
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3420488305
Short name T340
Test name
Test status
Simulation time 12974791 ps
CPU time 0.6 seconds
Started Jun 07 07:36:27 PM PDT 24
Finished Jun 07 07:36:28 PM PDT 24
Peak memory 194176 kb
Host smart-1846f466-d489-4368-b76b-d3012300f47e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420488305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3420488305
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3355984501
Short name T714
Test name
Test status
Simulation time 31174407 ps
CPU time 0.77 seconds
Started Jun 07 07:36:23 PM PDT 24
Finished Jun 07 07:36:26 PM PDT 24
Peak memory 196060 kb
Host smart-978d4f08-4319-45c7-bf09-f6db1bd95388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355984501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3355984501
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2512414403
Short name T328
Test name
Test status
Simulation time 251293506 ps
CPU time 7.54 seconds
Started Jun 07 07:36:20 PM PDT 24
Finished Jun 07 07:36:31 PM PDT 24
Peak memory 198044 kb
Host smart-18596e47-b4b4-418e-a5d0-ebc2ba05ae25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512414403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2512414403
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4187047167
Short name T487
Test name
Test status
Simulation time 48709697 ps
CPU time 0.86 seconds
Started Jun 07 07:36:21 PM PDT 24
Finished Jun 07 07:36:24 PM PDT 24
Peak memory 196672 kb
Host smart-1124b4ea-b2a1-4ed8-b20a-a2afc8cbfe39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187047167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4187047167
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1946353012
Short name T515
Test name
Test status
Simulation time 1111317485 ps
CPU time 1.66 seconds
Started Jun 07 07:36:23 PM PDT 24
Finished Jun 07 07:36:27 PM PDT 24
Peak memory 197100 kb
Host smart-2416ffc6-81ad-4d35-bd22-159166e19a7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946353012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1946353012
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1312792463
Short name T378
Test name
Test status
Simulation time 331156084 ps
CPU time 3.6 seconds
Started Jun 07 07:36:21 PM PDT 24
Finished Jun 07 07:36:27 PM PDT 24
Peak memory 198100 kb
Host smart-93943c64-46fc-4a49-8769-31c273bcbdeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312792463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1312792463
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.461758646
Short name T329
Test name
Test status
Simulation time 435800295 ps
CPU time 3.39 seconds
Started Jun 07 07:36:19 PM PDT 24
Finished Jun 07 07:36:25 PM PDT 24
Peak memory 198136 kb
Host smart-2883f3e1-e992-4a1e-9126-36206b85e23c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461758646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.461758646
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1362064251
Short name T550
Test name
Test status
Simulation time 259974384 ps
CPU time 1.34 seconds
Started Jun 07 07:36:19 PM PDT 24
Finished Jun 07 07:36:24 PM PDT 24
Peak memory 198068 kb
Host smart-51986fa1-6fd9-40f5-b1ff-4b946dd9d237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362064251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1362064251
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3099446514
Short name T671
Test name
Test status
Simulation time 205439705 ps
CPU time 0.76 seconds
Started Jun 07 07:36:18 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 195460 kb
Host smart-79d44737-ef0d-4fdc-b24b-adf574847140
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099446514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3099446514
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2826203495
Short name T434
Test name
Test status
Simulation time 934001427 ps
CPU time 4.78 seconds
Started Jun 07 07:36:20 PM PDT 24
Finished Jun 07 07:36:28 PM PDT 24
Peak memory 197988 kb
Host smart-c2a77033-e437-4c16-9da1-b47261b3b889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826203495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2826203495
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2261468142
Short name T211
Test name
Test status
Simulation time 340977908 ps
CPU time 1.14 seconds
Started Jun 07 07:36:19 PM PDT 24
Finished Jun 07 07:36:23 PM PDT 24
Peak memory 195596 kb
Host smart-326d9ab4-6602-48aa-8350-5055c8e414aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261468142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2261468142
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2713557948
Short name T674
Test name
Test status
Simulation time 126900122 ps
CPU time 0.92 seconds
Started Jun 07 07:36:20 PM PDT 24
Finished Jun 07 07:36:24 PM PDT 24
Peak memory 196320 kb
Host smart-980c1c05-0030-4292-a517-e8d802d00fd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713557948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2713557948
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1576884354
Short name T118
Test name
Test status
Simulation time 22052667714 ps
CPU time 77.32 seconds
Started Jun 07 07:36:21 PM PDT 24
Finished Jun 07 07:37:41 PM PDT 24
Peak memory 198172 kb
Host smart-9a8261d9-037f-4dd2-be76-52dd9ea81423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576884354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1576884354
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4222346505
Short name T882
Test name
Test status
Simulation time 967005252 ps
CPU time 1.35 seconds
Started Jun 07 08:03:52 PM PDT 24
Finished Jun 07 08:03:55 PM PDT 24
Peak memory 196156 kb
Host smart-8380d314-f87b-48dd-aca5-3f34da22e458
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4222346505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.4222346505
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4058956323
Short name T903
Test name
Test status
Simulation time 19936398 ps
CPU time 0.73 seconds
Started Jun 07 08:04:29 PM PDT 24
Finished Jun 07 08:04:31 PM PDT 24
Peak memory 194704 kb
Host smart-75f7231f-28f6-463c-8cea-6a083091580b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058956323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4058956323
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4106574250
Short name T860
Test name
Test status
Simulation time 180388881 ps
CPU time 1.26 seconds
Started Jun 07 08:04:32 PM PDT 24
Finished Jun 07 08:04:34 PM PDT 24
Peak memory 196196 kb
Host smart-eb99ab67-e639-40e0-94e3-4c2f1b522699
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4106574250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4106574250
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3254426477
Short name T865
Test name
Test status
Simulation time 481405737 ps
CPU time 1.45 seconds
Started Jun 07 08:04:35 PM PDT 24
Finished Jun 07 08:04:38 PM PDT 24
Peak memory 198228 kb
Host smart-9e3450de-d971-47f3-8289-8c6477b76e02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254426477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3254426477
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.346827369
Short name T866
Test name
Test status
Simulation time 218331615 ps
CPU time 1.28 seconds
Started Jun 07 08:04:31 PM PDT 24
Finished Jun 07 08:04:33 PM PDT 24
Peak memory 195856 kb
Host smart-51195339-4ee0-4a84-b5b8-7659f109d39c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=346827369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.346827369
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2155655686
Short name T890
Test name
Test status
Simulation time 55452795 ps
CPU time 1.05 seconds
Started Jun 07 08:04:32 PM PDT 24
Finished Jun 07 08:04:34 PM PDT 24
Peak memory 195880 kb
Host smart-adfe5bd0-7c02-4f56-863a-bad1489e122b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155655686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2155655686
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.618164
Short name T883
Test name
Test status
Simulation time 438375602 ps
CPU time 0.97 seconds
Started Jun 07 08:04:33 PM PDT 24
Finished Jun 07 08:04:35 PM PDT 24
Peak memory 197380 kb
Host smart-b81299be-830a-4bad-a988-0c8eb1217701
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=618164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.618164
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3023400153
Short name T868
Test name
Test status
Simulation time 78508347 ps
CPU time 1.24 seconds
Started Jun 07 08:04:23 PM PDT 24
Finished Jun 07 08:04:26 PM PDT 24
Peak memory 196252 kb
Host smart-82408ad2-9e3e-4682-837f-ff4ed393d0a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023400153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3023400153
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3885114399
Short name T948
Test name
Test status
Simulation time 109783954 ps
CPU time 1 seconds
Started Jun 07 08:04:29 PM PDT 24
Finished Jun 07 08:04:32 PM PDT 24
Peak memory 196740 kb
Host smart-c89887ec-1634-4aca-99a4-3f061f6d25bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3885114399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3885114399
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2503963681
Short name T856
Test name
Test status
Simulation time 392635227 ps
CPU time 1.14 seconds
Started Jun 07 08:04:26 PM PDT 24
Finished Jun 07 08:04:29 PM PDT 24
Peak memory 198308 kb
Host smart-3a4904a1-6651-42bf-a52c-6c9510f43c4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503963681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2503963681
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2218394515
Short name T874
Test name
Test status
Simulation time 45281933 ps
CPU time 0.97 seconds
Started Jun 07 08:04:29 PM PDT 24
Finished Jun 07 08:04:32 PM PDT 24
Peak memory 195916 kb
Host smart-e854066a-05e1-4aeb-aad4-80d487ef6ca6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2218394515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2218394515
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.989249993
Short name T879
Test name
Test status
Simulation time 225351076 ps
CPU time 1.22 seconds
Started Jun 07 08:04:33 PM PDT 24
Finished Jun 07 08:04:36 PM PDT 24
Peak memory 198244 kb
Host smart-8e682799-bdaa-478d-b620-c8522c09ddfc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989249993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.989249993
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3855753845
Short name T877
Test name
Test status
Simulation time 73580956 ps
CPU time 1.06 seconds
Started Jun 07 08:04:29 PM PDT 24
Finished Jun 07 08:04:32 PM PDT 24
Peak memory 196848 kb
Host smart-61d78a01-055d-4d65-b274-171050adaac3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3855753845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3855753845
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.408008571
Short name T916
Test name
Test status
Simulation time 34870724 ps
CPU time 1.03 seconds
Started Jun 07 08:04:24 PM PDT 24
Finished Jun 07 08:04:27 PM PDT 24
Peak memory 196884 kb
Host smart-bc80f094-056c-4da6-bfd4-c48c5f4c5afd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408008571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.408008571
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.698770644
Short name T911
Test name
Test status
Simulation time 205968538 ps
CPU time 1.32 seconds
Started Jun 07 08:04:24 PM PDT 24
Finished Jun 07 08:04:27 PM PDT 24
Peak memory 197044 kb
Host smart-09ec76af-0bb2-49d3-8243-aa31ada69acf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=698770644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.698770644
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.41782152
Short name T873
Test name
Test status
Simulation time 97542230 ps
CPU time 0.98 seconds
Started Jun 07 08:04:33 PM PDT 24
Finished Jun 07 08:04:35 PM PDT 24
Peak memory 195856 kb
Host smart-21bc7c12-0d32-4b3a-9d1f-51b256dc4428
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41782152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.41782152
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2110710498
Short name T909
Test name
Test status
Simulation time 288647072 ps
CPU time 1.36 seconds
Started Jun 07 08:04:27 PM PDT 24
Finished Jun 07 08:04:30 PM PDT 24
Peak memory 197016 kb
Host smart-770fb483-742d-48c5-bbd5-448bf82ae1e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2110710498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2110710498
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861542593
Short name T935
Test name
Test status
Simulation time 212644134 ps
CPU time 0.77 seconds
Started Jun 07 08:04:27 PM PDT 24
Finished Jun 07 08:04:29 PM PDT 24
Peak memory 195828 kb
Host smart-8e137c20-c2dc-4e14-a404-fa205e70c02d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861542593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.861542593
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1541160855
Short name T871
Test name
Test status
Simulation time 36248832 ps
CPU time 0.9 seconds
Started Jun 07 08:04:25 PM PDT 24
Finished Jun 07 08:04:27 PM PDT 24
Peak memory 196492 kb
Host smart-b2b3abf6-cf18-49eb-9e0d-0e33121cac46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1541160855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1541160855
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1796662183
Short name T907
Test name
Test status
Simulation time 63547164 ps
CPU time 1.05 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 198084 kb
Host smart-f46d090d-3542-4a04-a2e7-3720386c8ea5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796662183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1796662183
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.352231152
Short name T906
Test name
Test status
Simulation time 42457903 ps
CPU time 0.8 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 195696 kb
Host smart-1bbc8212-1195-4d32-812a-2ae033493bc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=352231152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.352231152
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1116576496
Short name T936
Test name
Test status
Simulation time 151394743 ps
CPU time 1.27 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 197484 kb
Host smart-ba0bdb32-aa00-4538-9763-e55ebdc55231
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116576496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1116576496
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4294890828
Short name T876
Test name
Test status
Simulation time 44324842 ps
CPU time 1.19 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 197016 kb
Host smart-e1255478-43aa-4939-bc10-f3b0c78f8c91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4294890828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4294890828
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.230033935
Short name T861
Test name
Test status
Simulation time 347612553 ps
CPU time 1.31 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 196996 kb
Host smart-f412e533-376a-4350-9795-34c3f46664e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230033935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.230033935
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1347511571
Short name T917
Test name
Test status
Simulation time 27229189 ps
CPU time 0.93 seconds
Started Jun 07 08:04:31 PM PDT 24
Finished Jun 07 08:04:33 PM PDT 24
Peak memory 196068 kb
Host smart-5b432184-ec80-485e-9104-93f53c0f5139
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1347511571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1347511571
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3171414545
Short name T869
Test name
Test status
Simulation time 39700603 ps
CPU time 1.12 seconds
Started Jun 07 08:04:32 PM PDT 24
Finished Jun 07 08:04:34 PM PDT 24
Peak memory 196812 kb
Host smart-f8c81914-9b96-4a6b-834a-ba95e05f6095
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171414545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3171414545
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2855022986
Short name T898
Test name
Test status
Simulation time 174129521 ps
CPU time 1.26 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196992 kb
Host smart-68bb6206-7232-4c96-8662-191b0bc8613e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2855022986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2855022986
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353668838
Short name T852
Test name
Test status
Simulation time 82237530 ps
CPU time 1.12 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 195852 kb
Host smart-da1e39bd-9f2d-4ea2-9b96-56ebed7bbc02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353668838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2353668838
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4002783946
Short name T939
Test name
Test status
Simulation time 35145132 ps
CPU time 1.11 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 196168 kb
Host smart-ce35c196-3bf8-4622-a9d2-732a52573913
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4002783946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4002783946
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1735394719
Short name T930
Test name
Test status
Simulation time 127746750 ps
CPU time 1.59 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196632 kb
Host smart-8fb778ff-14ed-40f6-bb94-bce77cc1315b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735394719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1735394719
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1577528910
Short name T895
Test name
Test status
Simulation time 79279180 ps
CPU time 0.87 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 196616 kb
Host smart-9c68c683-df17-4080-ac71-6df8c5810ba2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1577528910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1577528910
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1185802833
Short name T880
Test name
Test status
Simulation time 19163410 ps
CPU time 0.77 seconds
Started Jun 07 08:04:11 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 194632 kb
Host smart-e7fc57d1-fdd1-454d-8fde-9c93e7ca932b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185802833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1185802833
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1681718819
Short name T893
Test name
Test status
Simulation time 30617494 ps
CPU time 0.93 seconds
Started Jun 07 08:04:08 PM PDT 24
Finished Jun 07 08:04:09 PM PDT 24
Peak memory 196456 kb
Host smart-fd5717f5-f866-4ed9-93d9-7ba8ed1afae0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1681718819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1681718819
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482618870
Short name T922
Test name
Test status
Simulation time 150364707 ps
CPU time 1.1 seconds
Started Jun 07 08:04:08 PM PDT 24
Finished Jun 07 08:04:10 PM PDT 24
Peak memory 197012 kb
Host smart-40434c9b-5b2f-49ac-ae35-70bf267bacaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482618870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2482618870
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1111346747
Short name T915
Test name
Test status
Simulation time 110698442 ps
CPU time 1.63 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 197076 kb
Host smart-1ecbeefe-ab68-43fd-965d-89859c30623c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1111346747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1111346747
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138905743
Short name T899
Test name
Test status
Simulation time 32403106 ps
CPU time 0.91 seconds
Started Jun 07 08:04:12 PM PDT 24
Finished Jun 07 08:04:14 PM PDT 24
Peak memory 195348 kb
Host smart-98b1bf11-dc5b-4f47-bad4-9953aabec05d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138905743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.138905743
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3635608478
Short name T905
Test name
Test status
Simulation time 172519794 ps
CPU time 1.48 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196772 kb
Host smart-8e71081d-d3b9-4175-8049-b9b00199c9ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3635608478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3635608478
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1902640153
Short name T940
Test name
Test status
Simulation time 176653923 ps
CPU time 1.4 seconds
Started Jun 07 08:04:11 PM PDT 24
Finished Jun 07 08:04:14 PM PDT 24
Peak memory 196976 kb
Host smart-e55c2949-6683-4989-9220-2cb7750a24bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902640153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1902640153
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1331574937
Short name T937
Test name
Test status
Simulation time 208400339 ps
CPU time 1.25 seconds
Started Jun 07 08:04:11 PM PDT 24
Finished Jun 07 08:04:14 PM PDT 24
Peak memory 196868 kb
Host smart-51680307-e91b-44e8-a08d-0a7c4d2839ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1331574937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1331574937
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3288578580
Short name T925
Test name
Test status
Simulation time 109572088 ps
CPU time 0.82 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 195672 kb
Host smart-dd82b1dc-001b-40a3-a82a-17e025671231
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288578580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3288578580
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3390945734
Short name T947
Test name
Test status
Simulation time 215855581 ps
CPU time 1.33 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196840 kb
Host smart-51b4e31b-ab12-4440-b15a-ab771770a283
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3390945734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3390945734
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1549779114
Short name T904
Test name
Test status
Simulation time 49999295 ps
CPU time 1.48 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:14 PM PDT 24
Peak memory 197004 kb
Host smart-b8cdf69a-3559-4220-81d4-aabdcba0253a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549779114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1549779114
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.493322909
Short name T912
Test name
Test status
Simulation time 380270803 ps
CPU time 1.62 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196972 kb
Host smart-a8c3638c-be30-43ca-a539-7795ccd274e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=493322909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.493322909
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4243619504
Short name T858
Test name
Test status
Simulation time 174607182 ps
CPU time 1.11 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 196864 kb
Host smart-522bd07c-de1e-4ce7-87a6-b8a069faced7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243619504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4243619504
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2882655399
Short name T889
Test name
Test status
Simulation time 937035020 ps
CPU time 1.29 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 198180 kb
Host smart-24c8d1e9-a16e-40b2-a064-95ba04176e8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2882655399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2882655399
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.712565199
Short name T927
Test name
Test status
Simulation time 70764382 ps
CPU time 1.21 seconds
Started Jun 07 08:04:08 PM PDT 24
Finished Jun 07 08:04:10 PM PDT 24
Peak memory 196840 kb
Host smart-5514587a-1ae7-4856-bc6f-5895b407dc1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712565199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.712565199
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2717947152
Short name T933
Test name
Test status
Simulation time 139412003 ps
CPU time 1.39 seconds
Started Jun 07 08:04:28 PM PDT 24
Finished Jun 07 08:04:31 PM PDT 24
Peak memory 198116 kb
Host smart-0796b3a9-29bb-489c-bf61-baa9aa15951f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2717947152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2717947152
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1295586618
Short name T851
Test name
Test status
Simulation time 39801327 ps
CPU time 1.01 seconds
Started Jun 07 08:03:55 PM PDT 24
Finished Jun 07 08:03:57 PM PDT 24
Peak memory 196832 kb
Host smart-76d52384-f6e6-4642-8090-b6872ce1e69e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295586618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1295586618
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1239996696
Short name T875
Test name
Test status
Simulation time 180905478 ps
CPU time 1.08 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196712 kb
Host smart-442990ec-2275-4fcf-8f49-0c3903ced5d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1239996696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1239996696
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.990497223
Short name T863
Test name
Test status
Simulation time 556808910 ps
CPU time 1.47 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 197184 kb
Host smart-bceafdaa-e081-47aa-94c8-90dcb3245f92
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990497223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.990497223
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1096836704
Short name T908
Test name
Test status
Simulation time 219381609 ps
CPU time 1.47 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:14 PM PDT 24
Peak memory 196852 kb
Host smart-4f345a2c-9417-41df-a2ed-c61004d030a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1096836704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1096836704
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710777063
Short name T900
Test name
Test status
Simulation time 50854048 ps
CPU time 1.31 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 197068 kb
Host smart-9a9f672f-9e8f-49b1-9eb3-344825548568
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710777063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2710777063
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1806894512
Short name T853
Test name
Test status
Simulation time 66592664 ps
CPU time 1.11 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 196736 kb
Host smart-71a7bf6a-3efa-4b9c-bf1b-17c2d6def91b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1806894512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1806894512
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193235235
Short name T914
Test name
Test status
Simulation time 45150388 ps
CPU time 1.33 seconds
Started Jun 07 08:04:12 PM PDT 24
Finished Jun 07 08:04:15 PM PDT 24
Peak memory 196780 kb
Host smart-a9bf6031-46f4-4ae2-9af9-5889f47a90b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193235235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.193235235
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1305436972
Short name T884
Test name
Test status
Simulation time 73762179 ps
CPU time 0.93 seconds
Started Jun 07 08:04:10 PM PDT 24
Finished Jun 07 08:04:13 PM PDT 24
Peak memory 196704 kb
Host smart-f2770a6c-e662-4fca-8508-f64b2ac41d12
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1305436972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1305436972
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.691471046
Short name T945
Test name
Test status
Simulation time 96898522 ps
CPU time 0.78 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 195728 kb
Host smart-4e041ba2-7578-4dd3-94cd-3271457d1582
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691471046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.691471046
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3139982251
Short name T864
Test name
Test status
Simulation time 131566664 ps
CPU time 0.87 seconds
Started Jun 07 08:04:11 PM PDT 24
Finished Jun 07 08:04:15 PM PDT 24
Peak memory 195568 kb
Host smart-65114b85-5fde-4253-958b-03ba70359a20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3139982251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3139982251
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2201360293
Short name T934
Test name
Test status
Simulation time 162890225 ps
CPU time 1.23 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:12 PM PDT 24
Peak memory 196184 kb
Host smart-da76b2a3-bbf6-4155-9996-3f77f01cb5d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201360293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2201360293
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.449785273
Short name T862
Test name
Test status
Simulation time 569950991 ps
CPU time 1.43 seconds
Started Jun 07 08:04:09 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 196792 kb
Host smart-28ad8de5-7c36-4f88-a850-7e1fa9532735
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=449785273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.449785273
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3431721143
Short name T850
Test name
Test status
Simulation time 76251001 ps
CPU time 0.94 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 195604 kb
Host smart-1aecfd0b-8989-48a9-aaa9-ff51c153d045
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431721143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3431721143
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.543642644
Short name T942
Test name
Test status
Simulation time 376429176 ps
CPU time 0.86 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:42 PM PDT 24
Peak memory 195784 kb
Host smart-e237575b-bb7b-4681-b9bf-065f153d1441
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=543642644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.543642644
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3441386983
Short name T928
Test name
Test status
Simulation time 308495353 ps
CPU time 1.23 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:42 PM PDT 24
Peak memory 197060 kb
Host smart-6fed7ad4-c798-4b23-b586-33d899d8fd59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441386983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3441386983
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2013291620
Short name T902
Test name
Test status
Simulation time 75382316 ps
CPU time 1.19 seconds
Started Jun 07 08:04:40 PM PDT 24
Finished Jun 07 08:04:45 PM PDT 24
Peak memory 198232 kb
Host smart-9beff435-36c9-417f-82ac-bdb47493a823
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2013291620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2013291620
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.733416323
Short name T924
Test name
Test status
Simulation time 27349087 ps
CPU time 0.84 seconds
Started Jun 07 08:04:34 PM PDT 24
Finished Jun 07 08:04:37 PM PDT 24
Peak memory 196784 kb
Host smart-f25d3910-0c14-4e3b-bbb2-c200b443efee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733416323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.733416323
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.260553762
Short name T849
Test name
Test status
Simulation time 88160709 ps
CPU time 1.22 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:42 PM PDT 24
Peak memory 197232 kb
Host smart-615f5fba-fab7-4395-a57b-047ef7864447
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=260553762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.260553762
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525499376
Short name T901
Test name
Test status
Simulation time 508733227 ps
CPU time 1.07 seconds
Started Jun 07 08:04:39 PM PDT 24
Finished Jun 07 08:04:43 PM PDT 24
Peak memory 198212 kb
Host smart-ef057a7a-d542-477f-8216-ef697159ef41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525499376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3525499376
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2931775996
Short name T878
Test name
Test status
Simulation time 327044768 ps
CPU time 1.22 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:42 PM PDT 24
Peak memory 196128 kb
Host smart-a5ec5fdb-d03e-4a83-8999-a00bfbb86261
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2931775996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2931775996
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2590211785
Short name T857
Test name
Test status
Simulation time 263341586 ps
CPU time 0.91 seconds
Started Jun 07 08:04:40 PM PDT 24
Finished Jun 07 08:04:44 PM PDT 24
Peak memory 195940 kb
Host smart-2763531d-9341-41a8-9f34-6faf897f9fe8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590211785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2590211785
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3839130936
Short name T932
Test name
Test status
Simulation time 95365718 ps
CPU time 0.92 seconds
Started Jun 07 08:04:23 PM PDT 24
Finished Jun 07 08:04:26 PM PDT 24
Peak memory 197660 kb
Host smart-8666734f-a4a3-44a6-b0c4-b8d1943acba5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3839130936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3839130936
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.948703537
Short name T855
Test name
Test status
Simulation time 29071290 ps
CPU time 0.96 seconds
Started Jun 07 08:04:24 PM PDT 24
Finished Jun 07 08:04:27 PM PDT 24
Peak memory 196800 kb
Host smart-8808507a-dcb6-4996-9465-1389fcea07fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948703537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.948703537
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3183706369
Short name T896
Test name
Test status
Simulation time 180151594 ps
CPU time 0.97 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:42 PM PDT 24
Peak memory 196856 kb
Host smart-bdd8f50d-85f3-44aa-95f5-3307461720b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3183706369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3183706369
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.447120589
Short name T919
Test name
Test status
Simulation time 363117463 ps
CPU time 1.38 seconds
Started Jun 07 08:04:39 PM PDT 24
Finished Jun 07 08:04:43 PM PDT 24
Peak memory 197200 kb
Host smart-2065e509-f781-4e2d-a397-5de66ba53c6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447120589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.447120589
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1615472733
Short name T913
Test name
Test status
Simulation time 400824843 ps
CPU time 0.94 seconds
Started Jun 07 08:04:41 PM PDT 24
Finished Jun 07 08:04:46 PM PDT 24
Peak memory 195904 kb
Host smart-3c2b0769-2e44-4170-ada6-d6c2693d4704
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1615472733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1615472733
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1751407298
Short name T923
Test name
Test status
Simulation time 114206898 ps
CPU time 0.97 seconds
Started Jun 07 08:04:35 PM PDT 24
Finished Jun 07 08:04:37 PM PDT 24
Peak memory 196716 kb
Host smart-6570e10c-7083-424f-9550-ae75197f32b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751407298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1751407298
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1765479618
Short name T920
Test name
Test status
Simulation time 52243673 ps
CPU time 1.02 seconds
Started Jun 07 08:04:39 PM PDT 24
Finished Jun 07 08:04:43 PM PDT 24
Peak memory 196124 kb
Host smart-b96ee532-dd41-4949-b584-02d06ac8b5ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1765479618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1765479618
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3491376350
Short name T885
Test name
Test status
Simulation time 56515356 ps
CPU time 0.97 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 196812 kb
Host smart-02017d12-85fa-46d7-b584-d5527be0731b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491376350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3491376350
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2979052087
Short name T929
Test name
Test status
Simulation time 443973748 ps
CPU time 0.91 seconds
Started Jun 07 08:04:40 PM PDT 24
Finished Jun 07 08:04:45 PM PDT 24
Peak memory 196876 kb
Host smart-9e93f0fd-4f1a-4f0d-835d-626f8fb89f0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2979052087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2979052087
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908756898
Short name T867
Test name
Test status
Simulation time 95909863 ps
CPU time 0.72 seconds
Started Jun 07 08:04:37 PM PDT 24
Finished Jun 07 08:04:39 PM PDT 24
Peak memory 195284 kb
Host smart-16450e0e-dbf5-4d16-a21d-800fef2712d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908756898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3908756898
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4223813002
Short name T872
Test name
Test status
Simulation time 121672112 ps
CPU time 1.26 seconds
Started Jun 07 08:04:37 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 196204 kb
Host smart-9996d275-7541-4886-a40c-7bda84baadcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4223813002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4223813002
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525780809
Short name T926
Test name
Test status
Simulation time 43933645 ps
CPU time 0.94 seconds
Started Jun 07 08:04:35 PM PDT 24
Finished Jun 07 08:04:37 PM PDT 24
Peak memory 195688 kb
Host smart-6da82ef8-c6e3-439f-9a59-7321a0ce2080
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525780809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3525780809
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4046049021
Short name T946
Test name
Test status
Simulation time 113898054 ps
CPU time 1.18 seconds
Started Jun 07 08:04:37 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 197036 kb
Host smart-8b76002a-f952-4ca3-9be4-ab52596e838d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4046049021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4046049021
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2050683652
Short name T854
Test name
Test status
Simulation time 198140143 ps
CPU time 1.13 seconds
Started Jun 07 08:04:35 PM PDT 24
Finished Jun 07 08:04:37 PM PDT 24
Peak memory 196776 kb
Host smart-dcc72002-5c7c-4204-befb-095c28b85e47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050683652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2050683652
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2263666121
Short name T943
Test name
Test status
Simulation time 60753496 ps
CPU time 1.17 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 196848 kb
Host smart-948ab8da-cb44-4d74-878c-9f6abff7dfbb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2263666121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2263666121
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594702848
Short name T938
Test name
Test status
Simulation time 186279352 ps
CPU time 1.31 seconds
Started Jun 07 08:04:39 PM PDT 24
Finished Jun 07 08:04:43 PM PDT 24
Peak memory 197016 kb
Host smart-dbd15f47-b7e0-4931-8b3c-925996c35ebd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594702848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2594702848
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3161112383
Short name T941
Test name
Test status
Simulation time 168606523 ps
CPU time 1.06 seconds
Started Jun 07 08:04:37 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 198192 kb
Host smart-0492a4e7-62ad-4af4-a0c5-2ec85fea7da2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3161112383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3161112383
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2845952879
Short name T859
Test name
Test status
Simulation time 120899949 ps
CPU time 1.12 seconds
Started Jun 07 08:04:36 PM PDT 24
Finished Jun 07 08:04:39 PM PDT 24
Peak memory 195880 kb
Host smart-efd179f7-a833-4075-9140-7a3ee1f21b24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845952879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2845952879
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1994660985
Short name T887
Test name
Test status
Simulation time 74955834 ps
CPU time 0.8 seconds
Started Jun 07 08:04:37 PM PDT 24
Finished Jun 07 08:04:40 PM PDT 24
Peak memory 195788 kb
Host smart-5fe73d56-f95d-41a8-9a63-ddea69c39bbe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1994660985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1994660985
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.908813147
Short name T931
Test name
Test status
Simulation time 71349542 ps
CPU time 1.42 seconds
Started Jun 07 08:04:40 PM PDT 24
Finished Jun 07 08:04:46 PM PDT 24
Peak memory 198212 kb
Host smart-7d485927-6c23-440d-bdfe-47427c5d5661
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908813147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.908813147
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1607908029
Short name T918
Test name
Test status
Simulation time 37970137 ps
CPU time 0.77 seconds
Started Jun 07 08:04:40 PM PDT 24
Finished Jun 07 08:04:44 PM PDT 24
Peak memory 194632 kb
Host smart-3515b25c-2d0d-4b81-ae1f-9a5e9eebc46c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1607908029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1607908029
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3859463381
Short name T894
Test name
Test status
Simulation time 43413476 ps
CPU time 1.32 seconds
Started Jun 07 08:04:40 PM PDT 24
Finished Jun 07 08:04:46 PM PDT 24
Peak memory 198188 kb
Host smart-0986c096-8399-414b-b229-5735dc5c1df6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859463381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3859463381
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1517487387
Short name T897
Test name
Test status
Simulation time 37026562 ps
CPU time 1.06 seconds
Started Jun 07 08:04:25 PM PDT 24
Finished Jun 07 08:04:28 PM PDT 24
Peak memory 196084 kb
Host smart-e6f146e6-9452-4e20-8e5f-98255f46aa18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1517487387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1517487387
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4000722384
Short name T921
Test name
Test status
Simulation time 54075220 ps
CPU time 0.81 seconds
Started Jun 07 08:04:30 PM PDT 24
Finished Jun 07 08:04:32 PM PDT 24
Peak memory 195752 kb
Host smart-1a6f5ae9-dcc6-45b1-8e56-d2fb8bc61926
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000722384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4000722384
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4261630538
Short name T881
Test name
Test status
Simulation time 154444373 ps
CPU time 1.21 seconds
Started Jun 07 08:04:32 PM PDT 24
Finished Jun 07 08:04:34 PM PDT 24
Peak memory 197032 kb
Host smart-585d7558-8cb8-470e-85ba-77c573bba2fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4261630538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.4261630538
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1190398631
Short name T870
Test name
Test status
Simulation time 357431394 ps
CPU time 1.42 seconds
Started Jun 07 08:04:31 PM PDT 24
Finished Jun 07 08:04:33 PM PDT 24
Peak memory 197096 kb
Host smart-95b30bec-392b-4230-bb92-3e7972aef70e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190398631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1190398631
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2541337225
Short name T892
Test name
Test status
Simulation time 105482944 ps
CPU time 1.56 seconds
Started Jun 07 08:04:30 PM PDT 24
Finished Jun 07 08:04:33 PM PDT 24
Peak memory 196776 kb
Host smart-68b99818-2ccc-4281-85cf-17212d3244cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2541337225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2541337225
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.378435379
Short name T891
Test name
Test status
Simulation time 35056938 ps
CPU time 0.97 seconds
Started Jun 07 08:04:29 PM PDT 24
Finished Jun 07 08:04:31 PM PDT 24
Peak memory 196136 kb
Host smart-17bad9ad-58f8-4b9f-b45b-5c30f5fff4d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378435379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.378435379
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1170168571
Short name T886
Test name
Test status
Simulation time 379247878 ps
CPU time 1.32 seconds
Started Jun 07 08:04:23 PM PDT 24
Finished Jun 07 08:04:26 PM PDT 24
Peak memory 196820 kb
Host smart-a83b41d6-6a48-4643-81af-22124d734d16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1170168571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1170168571
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.888838073
Short name T910
Test name
Test status
Simulation time 38173599 ps
CPU time 1.06 seconds
Started Jun 07 08:04:24 PM PDT 24
Finished Jun 07 08:04:27 PM PDT 24
Peak memory 196576 kb
Host smart-cff6735f-0332-46ad-93e4-78e86eddddd4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888838073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.888838073
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3509419362
Short name T944
Test name
Test status
Simulation time 23579910 ps
CPU time 0.84 seconds
Started Jun 07 08:04:38 PM PDT 24
Finished Jun 07 08:04:41 PM PDT 24
Peak memory 195772 kb
Host smart-6386ffa3-2638-4381-b4fc-040aefadff85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3509419362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3509419362
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4149484384
Short name T888
Test name
Test status
Simulation time 77040515 ps
CPU time 1.39 seconds
Started Jun 07 08:04:30 PM PDT 24
Finished Jun 07 08:04:33 PM PDT 24
Peak memory 197232 kb
Host smart-2d5af631-0fd2-49b2-b8da-fb8cbada4d3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149484384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4149484384
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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